afonso360 opened PR #6266 from afonso360:riscv-vec-size
to bytecodealliance:main
:
:wave: Hey,
This is a small follow up to #6240. This PR does a couple of things:
- We now recognize the
Zvl*
family of extensions, which really just specify the minimum size of a vector register.- Instead of gating our vector lowerings on
has_v
and assuming 128 bit registers, we now allow lowering any size as long as they fit in a single register.
- We switch the type extractor to
ty_vec_fits_in_register
which feels slightly neater than(if-let $true (has_v))
everywhereThis isn't really required, but it's neat that we get all of these lowerings without pretty much any effort, so I figured it would be worth it.
afonso360 requested fitzgen for a review on PR #6266.
afonso360 requested wasmtime-compiler-reviewers for a review on PR #6266.
afonso360 edited PR #6266:
:wave: Hey,
This is a small follow up to #6240. This PR does a couple of things:
- We now recognize the
Zvl*
family of extensions, which really just specify the minimum size of a vector register.- Instead of gating our vector lowerings on
has_v
and assuming 128 bit registers, we now allow lowering any size as long as they fit in a single register.
- We switch the type extractor to
ty_vec_fits_in_register
which feels slightly neater than(if-let $true (has_v))
everywhere- Also
iadd
usesfits_in_64
which also matches small vectors, so I switched the rules to usingty_int_ref_scalar_64
which only match scalars.This isn't really required, but it's neat that we get all of these lowerings without pretty much any effort, so I figured it would be worth it.
afonso360 updated PR #6266.
alexcrichton submitted PR review:
Looks good to me!
Should
zvl128b
imply thev
extension or vice-versa?
afonso360 merged PR #6266.
Last updated: Dec 23 2024 at 12:05 UTC