Stream: git-wasmtime

Topic: wasmtime / PR #6001 fuzzgen: Generate random ISA flags

Wasmtime GitHub notifications bot (Mar 13 2023 at 13:54):

afonso360 opened PR #6001 from fuzz-isa to main:

:wave: Hey,

This PR allows fuzzgen to generate random ISA flags and run the tests with them. It has two modes, for icache since we are just compiling the code we enable all flags, but for fuzzgen we actually need to execute them, so we use cranelift-native and only allow flags available in the host.

So far this has found the following issues on icache, so we need to fix them before merging:

• #5857
  • Here with zbb we generate an invalid lowering using integer instruction on float registers
• #5854
  • The issue here is that with zbb we accidentally lose a lowering for ctz
• #5979

I also don't have AVX-512 hardware, so It would be really nice if someone could run this on one of those fancy machines before merging, or we can also let OSS-Fuzz do it.

This has otherwise found nothing on AArch64 and RISC-V.

Fixes #5816

Wasmtime GitHub notifications bot (Mar 13 2023 at 13:54):

afonso360 requested jameysharp for a review on PR #6001.

Wasmtime GitHub notifications bot (Mar 13 2023 at 13:55):

afonso360 edited PR #6001 from fuzz-isa to main:

:wave: Hey,

This PR allows fuzzgen to generate random ISA flags and run the tests with them. It has two modes, for icache since we are just compiling the code we enable all flags, but for fuzzgen we actually need to execute them, so we use cranelift-native and only allow flags available in the host.

This has found the following issues on icache, so we need to fix them before merging:

• #5857
  • Here with zbb we generate an invalid lowering using integer instruction on float registers
• #5854
  • The issue here is that with zbb we accidentally lose a lowering for ctz
• #5979

I also don't have AVX-512 hardware, so It would be really nice if someone could run this on one of those fancy machines before merging, or we can also let OSS-Fuzz do it.

This has otherwise found nothing on AArch64 and RISC-V.

Fixes #5816

Wasmtime GitHub notifications bot (Mar 13 2023 at 14:23):

afonso360 edited PR #6001 from fuzz-isa to main:

:wave: Hey,

This PR allows fuzzgen to generate random ISA flags and run the tests with them. It has two modes, for icache since we are just compiling the code we enable all flags, but for fuzzgen we actually need to execute them, so we use cranelift-native and only allow flags available in the host.

This has found the following issues on icache, so we need to fix them before merging:

• #5857
  • Here with zbb we generate an invalid lowering using integer instructions on float registers
• #5854
  • The issue here is that with zbb we accidentally lose a lowering for ctz
• #5979

I also don't have AVX-512 hardware, so It would be really nice if someone could run this on one of those fancy machines before merging, or we can also let OSS-Fuzz do it.

This has otherwise found nothing on AArch64 and RISC-V.

Fixes #5816

Wasmtime GitHub notifications bot (Mar 13 2023 at 14:27):

afonso360 edited PR #6001 from fuzz-isa to main:

:wave: Hey,

This PR allows fuzzgen to generate random ISA flags and run the tests with them.

It has two modes:

• On icache since we are just compiling the code we enable all flags
• On fuzzgen we actually need to execute them, so we use cranelift-native and only allow flags available in the host.

This has found the following issues on icache, so we need to fix them before merging:

• #5857
  • Here with zbb we generate an invalid lowering using integer instructions on float registers
• #5854
  • The issue here is that with zbb we accidentally lose a lowering for ctz
• #5979

I also don't have AVX-512 hardware, so It would be really nice if someone could run this on one of those fancy machines before merging, or we can also let OSS-Fuzz do it.

This has otherwise found nothing on AArch64 and RISC-V.

Fixes #5816

Wasmtime GitHub notifications bot (Mar 13 2023 at 14:27):

afonso360 edited PR #6001 from fuzz-isa to main:

:wave: Hey,

This PR allows fuzzgen to generate random ISA flags and run the tests with them.

It has two modes:

• On icache since we are just compiling the code we allow all flags
• On fuzzgen we actually need to execute them, so we use cranelift-native and only allow flags available in the host.

This has found the following issues on icache, so we need to fix them before merging:

• #5857
  • Here with zbb we generate an invalid lowering using integer instructions on float registers
• #5854
  • The issue here is that with zbb we accidentally lose a lowering for ctz
• #5979

I also don't have AVX-512 hardware, so It would be really nice if someone could run this on one of those fancy machines before merging, or we can also let OSS-Fuzz do it.

This has otherwise found nothing on AArch64 and RISC-V.

Fixes #5816

Wasmtime GitHub notifications bot (Mar 13 2023 at 14:35):

afonso360 edited PR #6001 from fuzz-isa to main:

:wave: Hey,

This PR allows fuzzgen to generate random ISA flags and run the tests with them.

It has two modes:

• On icache since we are just compiling the code we allow all flags
• On fuzzgen we actually need to execute them, so we use cranelift-native and only allow flags available in the host.

This has found the following issues on icache, so we need to fix them before merging:

• #5857
  • Here with zbb we generate an invalid lowering using integer instructions on float registers
• #5854
  • The issue here is that with zbb we accidentally lose a lowering for ctz
• #5979

I also don't have AVX-512 hardware, so It would be really nice if someone could run this on one of those fancy machines before merging, or we can also let OSS-Fuzz do it.

This has otherwise found nothing on any arch via fuzzgen.

Fixes #5816

Wasmtime GitHub notifications bot (Mar 13 2023 at 22:47):

jameysharp submitted PR review.

Wasmtime GitHub notifications bot (Mar 21 2023 at 15:56):

afonso360 has marked PR #6001 as ready for review.

Wasmtime GitHub notifications bot (Mar 22 2023 at 11:42):

afonso360 merged PR #6001.

Last updated: Nov 22 2024 at 17:03 UTC