cfallin opened PR #5987 from fix-5985
to main
:
One of the cases for a splat operation, as updated in #5370, wrote to a temp reg but then only conditionally transformed the temp into the final destination register. In another codepath,
rd
was left undefined. This causes a panic later when regalloc2 verifies SSA properties of its input (here, value not def'd before use).Fixes #5985.
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cfallin requested elliottt for a review on PR #5987.
cfallin requested fitzgen for a review on PR #5987.
alexcrichton submitted PR review.
fitzgen submitted PR review.
cfallin merged PR #5987.
Last updated: Dec 23 2024 at 12:05 UTC