Stream: git-wasmtime

Topic: wasmtime / PR #5489 Cranelift: include return values in i...

Wasmtime GitHub notifications bot (Dec 24 2022 at 16:32):

KarelPeeters opened PR #5489 from isa-pretty-ret to main:

While experimenting I noticed that the VCode debug output did not include the operands of return instructions. This can be annoying to follow the data flow and see the full register allocation constraints.

For example:

[2022-12-24T16:28:14Z TRACE cranelift_codegen::machinst::lower] built vcode: VCode {
      Entry block: 0
      v130 := v132
    Block 0:
        (original IR block: block0)
        (successor: Block 1)
        (instruction range: 0 .. 3)
      Inst 0: args %v128=%rcx %v129=%rdx
      Inst 1: addq    %v128, %v129, %v132
      Inst 2: jmp     label1
    Block 1:
        (original IR block: block1)
        (instruction range: 3 .. 4)
      Inst 3: ret
    }

This PR fixes that for all ISAs, the new output looks like this:

      Inst 3: ret %v131=%rax

I didn't create an issue for this since it seemed like an easy and non-controversial fix. When formatting registers I always followed what the code around it was doing, which is a bit different for each of them.

I'm not sure who should review this.

Wasmtime GitHub notifications bot (Dec 24 2022 at 16:49):

KarelPeeters updated PR #5489 from isa-pretty-ret to main.

Wasmtime GitHub notifications bot (Dec 24 2022 at 16:52):

KarelPeeters updated PR #5489 from isa-pretty-ret to main.

Wasmtime GitHub notifications bot (Dec 24 2022 at 16:53):

KarelPeeters updated PR #5489 from isa-pretty-ret to main.

Wasmtime GitHub notifications bot (Jan 03 2023 at 17:06):

jameysharp submitted PR review.

Wasmtime GitHub notifications bot (Jan 03 2023 at 17:06):

jameysharp merged PR #5489.

Last updated: Dec 23 2024 at 12:05 UTC