elliottt opened PR #5381 from trevor/ssa-riscv64-remaining-bb-issues
to main
:
This PR fixes two bugs in the riscv64 backend, where branch instructions were emitted in the middle of a basic block:
- Constant emission, where the constants are inlined into the vcode and are jumped over at runtime,
- The
BrTableCheck
pseudo-instruction, which was always emitted before aBrTable
instruction, and would handle jumping to the default label.The first bug was resolved by introducing two new psuedo instructions,
LoadConst32
andLoadConst64
. Both of these instructions serve to delay the original encoding to emission time, after regalloc2 has run.The second bug was fixed by removing the
BrTableCheck
instruction. As it was always emitted directly beforeBrTable
, it was easier to remove it and merge the two into a single instruction.<!--
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elliottt updated PR #5381 from trevor/ssa-riscv64-remaining-bb-issues
to main
.
elliottt requested cfallin for a review on PR #5381.
cfallin submitted PR review.
elliottt merged PR #5381.
Last updated: Dec 23 2024 at 12:05 UTC