Wasmtime GitHub notifications bot (Dec 06 2022 at 04:37): Wasmtime GitHub notifications bot (Dec 06 2022 at 04:37):elliottt opened PR #5381 from trevor/ssa-riscv64-remaining-bb-issues to main:
This PR fixes two bugs in the riscv64 backend, where branch instructions were emitted in the middle of a basic block:
- Constant emission, where the constants are inlined into the vcode and are jumped over at runtime,
- The
BrTableCheckpseudo-instruction, which was always emitted before aBrTableinstruction, and would handle jumping to the default label.The first bug was resolved by introducing two new psuedo instructions,
LoadConst32andLoadConst64. Both of these instructions serve to delay the original encoding to emission time, after regalloc2 has run.The second bug was fixed by removing the
BrTableCheckinstruction. As it was always emitted directly beforeBrTable, it was easier to remove it and merge the two into a single instruction.<!--
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Wasmtime GitHub notifications bot (Dec 06 2022 at 04:44):elliottt updated PR #5381 from trevor/ssa-riscv64-remaining-bb-issues to main.
Wasmtime GitHub notifications bot (Dec 06 2022 at 04:45):elliottt requested cfallin for a review on PR #5381.
Wasmtime GitHub notifications bot (Dec 06 2022 at 18:37):cfallin submitted PR review.
Wasmtime GitHub notifications bot (Dec 06 2022 at 18:54):elliottt merged PR #5381.
Last updated: Oct 23 2024 at 20:03 UTC