Stream: git-wasmtime

Topic: wasmtime / PR #5132 Debug assertions for SSA

Wasmtime GitHub notifications bot (Oct 26 2022 at 18:49):

elliottt opened PR #5132 from trevor/ssa-assertions to main:

• Rework the compile interface to require fewer args
• Plumb the machine_env through the lowering context
• Plumb the MachineEnv through to the OperandCollector
• Assert that fixed allocations are to allocatable registers

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Wasmtime GitHub notifications bot (Oct 26 2022 at 20:17):

elliottt updated PR #5132 from trevor/ssa-assertions to main.

Wasmtime GitHub notifications bot (Oct 26 2022 at 20:41):

elliottt updated PR #5132 from trevor/ssa-assertions to main.

Wasmtime GitHub notifications bot (Oct 26 2022 at 21:03):

bjorn3 submitted PR review.

Wasmtime GitHub notifications bot (Oct 26 2022 at 21:03):

bjorn3 created PR review comment:

Doesn't this depend on the calling convention in some cases? Like for the spidermonkey integration which uses to reserve some registers.

Wasmtime GitHub notifications bot (Oct 26 2022 at 21:03):

bjorn3 edited PR review comment.

Wasmtime GitHub notifications bot (Oct 26 2022 at 22:29):

elliottt updated PR #5132 from trevor/ssa-assertions to main.

Wasmtime GitHub notifications bot (Oct 26 2022 at 23:20):

cfallin created PR review comment:

That was actually handled as an ISA flag; in principle which registers we allocate within a function body and which ABI we implement at caller and callee boundaries are orthogonal, and changing which registers we use is an optimization (so controlling this via compiler settings is adequate).

Wasmtime GitHub notifications bot (Oct 26 2022 at 23:20):

cfallin submitted PR review.

Wasmtime GitHub notifications bot (Oct 28 2022 at 19:11):

cfallin submitted PR review.

Wasmtime GitHub notifications bot (Oct 28 2022 at 19:11):

cfallin submitted PR review.

Wasmtime GitHub notifications bot (Oct 28 2022 at 19:11):

cfallin created PR review comment:

Hmm, this is pretty unfortunate (forcing the need to have a MachineEnv in the EmitInfo). One might not always have a MachineEnv when emitting: specifically, for Winch, we need to be able to operate more or less without regalloc2.

Can we find a way to do this without the MachineEnv? Maybe the OperandCollector is parameterized on a second function, a "validator", that checks whether each operand is actually valid? Then the use of the OperandCollector in the main lowering path can insert it, and other uses (e.g. by s390x) can insert a vacuous |_| true validator callback.

Wasmtime GitHub notifications bot (Nov 01 2022 at 16:57):

elliottt updated PR #5132 from trevor/ssa-assertions to main.

Wasmtime GitHub notifications bot (Nov 01 2022 at 23:47):

elliottt submitted PR review.

Wasmtime GitHub notifications bot (Nov 01 2022 at 23:47):

elliottt created PR review comment:

Fixed in #5164 by removing count_operands.

Wasmtime GitHub notifications bot (Nov 09 2022 at 00:24):

elliottt updated PR #5132 from trevor/ssa-assertions to main.

Wasmtime GitHub notifications bot (Nov 09 2022 at 00:33):

elliottt updated PR #5132 from trevor/ssa-assertions to main.

Wasmtime GitHub notifications bot (Nov 10 2022 at 21:48):

elliottt updated PR #5132 from trevor/ssa-assertions to main.

Wasmtime GitHub notifications bot (Nov 11 2022 at 02:15):

elliottt updated PR #5132 from trevor/ssa-assertions to main.

Wasmtime GitHub notifications bot (Nov 15 2022 at 20:51):

elliottt updated PR #5132 from trevor/ssa-assertions to main.

Wasmtime GitHub notifications bot (Nov 15 2022 at 20:51):

elliottt edited PR #5132 from trevor/ssa-assertions to main:

Add assertions to the OperandCollector that show we're not using pinned vregs.
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Wasmtime GitHub notifications bot (Nov 15 2022 at 22:01):

elliottt updated PR #5132 from trevor/ssa-assertions to main.

Wasmtime GitHub notifications bot (Nov 16 2022 at 19:35):

elliottt updated PR #5132 from trevor/ssa-assertions to main.

Wasmtime GitHub notifications bot (Nov 16 2022 at 20:00):

elliottt updated PR #5132 from trevor/ssa-assertions to main.

Wasmtime GitHub notifications bot (Nov 17 2022 at 19:40):

elliottt updated PR #5132 from trevor/ssa-assertions to main.

Wasmtime GitHub notifications bot (Nov 18 2022 at 17:44):

elliottt updated PR #5132 from trevor/ssa-assertions to main.

Wasmtime GitHub notifications bot (Nov 18 2022 at 19:45):

elliottt updated PR #5132 from trevor/ssa-assertions to main.

Wasmtime GitHub notifications bot (Nov 19 2022 at 00:31):

elliottt updated PR #5132 from trevor/ssa-assertions to main.

Wasmtime GitHub notifications bot (Nov 19 2022 at 06:43):

elliottt updated PR #5132 from trevor/ssa-assertions to main.

Wasmtime GitHub notifications bot (Nov 19 2022 at 09:06):

elliottt updated PR #5132 from trevor/ssa-assertions to main.

Wasmtime GitHub notifications bot (Nov 19 2022 at 09:13):

elliottt edited PR #5132 from trevor/ssa-assertions to main:

Add assertions to the OperandCollector that show we're not using pinned vregs, and use reg_fixed_nonallocatable constraints when a real register is used with other constraint generation functions like reg_use etc.

I experimented with adding debug assertions that the reused operand referenced in reg_reuse_def constraints was compatible with the new constraint that would be generated. This didn't end up being possible as some backends will recursively process instructions when collecting operands, making it impossible without more invasive changes to tell where that operand is in the operand vector. Given that we would need to plumb through somewhat substantial changes to support adding debug assertions, I decided that rephrasing the existing warning comment about real registers would be good enough.
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Last updated: Oct 23 2024 at 20:03 UTC