yuyang-ok opened PR #5078 from risc-fencei
to main
:
This is trying to fix https://github.com/bytecodealliance/wasmtime/issues/5033.
Thanks @afonso360, I think he is done all of the investigation,I didn't do a lot of work.
But I am still have question about the flag parameter.
look likeSYS_RISCV_FLUSH_ICACHE_LOCAL
andSYS_RISCV_FLUSH_ICACHE_LOCAL
have the same value.
yuyang-ok updated PR #5078 from risc-fencei
to main
.
yuyang-ok updated PR #5078 from risc-fencei
to main
.
yuyang-ok edited PR #5078 from risc-fencei
to main
:
This is trying to fix https://github.com/bytecodealliance/wasmtime/issues/5033.
Thanks @afonso360, I think he is done all of the investigation,I didn't do a lot of work.
But I am still have question about the flag parameter.
look likeSYS_RISCV_FLUSH_ICACHE_ALL
andSYS_RISCV_FLUSH_ICACHE_LOCAL
have the same value.
bjorn3 submitted PR review.
bjorn3 created PR review comment:
num_cpus::get()
does multiple syscalls and as such may be more expensive than theSYS_RISCV_FLUSH_ICACHE_ALL
syscall it is meant to avoid.
afonso360 submitted PR review.
afonso360 submitted PR review.
afonso360 created PR review comment:
Although it's not currently use we should really provide these values. These represent the range of addresses for which we should flush the cache (as far as I understand it). We can get these if we move this operation to the
clear_cache
function below which is a more appropriate place for it.There we have the start address and the length which we can easily convert into a start and end address.
afonso360 created PR review comment:
We might want to call this something along the lines of
SYS_RISCV_FLUSH_ICACHE
so that it provides a bit more context as to what this is doing.
afonso360 created PR review comment:
I'm also a bit confused as to why the kernel decide to alias both of these settings, but it seems as it was just to represent the state of things at the time. I think we should be OK just referencing
SYS_RISCV_FLUSH_ICACHE_ALL
which is the operation that we want but adding a comment on the current situation.
afonso360 edited PR review comment.
afonso360 edited PR review comment.
yuyang-ok submitted PR review.
yuyang-ok created PR review comment:
Ok,My main consideration is that detected at runtime make it is more easy to use. use this library need no configuration.Maybe I will add a feature
one-core
. Because of multi-core is the most case.
yuyang-ok created PR review comment:
yeah.
yuyang-ok submitted PR review.
yuyang-ok submitted PR review.
yuyang-ok created PR review comment:
ok.
yuyang-ok updated PR #5078 from risc-fencei
to main
.
yuyang-ok updated PR #5078 from risc-fencei
to main
.
yuyang-ok updated PR #5078 from risc-fencei
to main
.
afonso360 created PR review comment:
riscv_flush_icache(ptr as u64, (ptr as u64) + (len as u64))?;
afonso360 submitted PR review.
afonso360 created PR review comment:
I don't think we need to do this here. With the way the API for this crate is set up, we should always have a
clear_cache
operation preceding this. So we are effectively doing the cache flushing twice!
afonso360 submitted PR review.
yuyang-ok submitted PR review.
yuyang-ok created PR review comment:
ok.
yuyang-ok created PR review comment:
ok,thanks.
yuyang-ok submitted PR review.
yuyang-ok updated PR #5078 from risc-fencei
to main
.
yuyang-ok has marked PR #5078 as ready for review.
cfallin submitted PR review.
cfallin created PR review comment:
Writing/grammar fix: let's reword this as
# Most modern CPUs are SMP (multicore). However, when only one core is present, # some aspects of coherence are much cheaper. For example, RISC-V can use # one instruction `fence.i` rather than a syscall that invokes all other cores. # This feature enables such optimizations, but the resulting program will *only* # be safe to run on one-core systems.
cfallin created PR review comment:
// The syscall isn't defined in `libc`, so we definfe the syscall number here.
cfallin created PR review comment:
Missing space before
else
cfallin created PR review comment:
return
isn't necessary here, I think: the wholeif
is an expression that will return the last value in the block.
cfallin created PR review comment:
Missing newline after this line
cfallin created PR review comment:
LIkewise for these two lines:
return
isn't needed in either case.
cfallin created PR review comment:
// Currently these parameters are not used, but they are still defined.
cfallin submitted PR review.
alexcrichton created PR review comment:
I may have missed some discussion on this, but how come this is a crate feature? It seems like this would be better detected by the crate dynamically since many folks compiling code aren't certain what the target system looks like.
alexcrichton submitted PR review.
afonso360 submitted PR review.
afonso360 created PR review comment:
There a comment about detecting the number of cpu's at runtime: https://github.com/bytecodealliance/wasmtime/pull/5078#discussion_r1000502204
I'd prefer if we could call the vDSO implementation, since that would also do the exact same thing for non SMP kernels, and avoid the syscalls.
afonso360 edited PR review comment.
alexcrichton submitted PR review.
alexcrichton created PR review comment:
Could the result of
num_cpus::get
be stored in astatic
? That would incur syscalls on the first hit but none subsequently.
afonso360 edited PR review comment.
yuyang-ok submitted PR review.
yuyang-ok created PR review comment:
@alexcrichton That is a good idea save
num_cpus::get
instatic
.
yuyang-ok created PR review comment:
ok.
yuyang-ok submitted PR review.
yuyang-ok updated PR #5078 from risc-fencei
to main
.
yuyang-ok updated PR #5078 from risc-fencei
to main
.
yuyang-ok updated PR #5078 from risc-fencei
to main
.
yuyang-ok updated PR #5078 from risc-fencei
to main
.
bjorn3 created PR review comment:
I don't think
num_cpus::get()
is safe. Linux supports hotplugging entire cpus and enabling/disabling cpu cores at runtime. In addition cgroups can be used to limit and unlimit cpu usage.num_cpus
considers a cgroup limit to 1 or less cpu worth of time as there being only a single core even if it can migrate to a different cpu.
bjorn3 submitted PR review.
yuyang-ok updated PR #5078 from risc-fencei
to main
.
yuyang-ok updated PR #5078 from risc-fencei
to main
.
yuyang-ok updated PR #5078 from risc-fencei
to main
.
yuyang-ok submitted PR review.
yuyang-ok created PR review comment:
@bjorn3 I have rollback to features implementation since not safe,safety come first.
yuyang-ok edited PR review comment.
yuyang-ok edited PR review comment.
cfallin submitted PR review.
yuyang-ok updated PR #5078 from risc-fencei
to main
.
yuyang-ok closed without merge PR #5078.
Last updated: Dec 23 2024 at 13:07 UTC