cfallin requested elliottt for a review on PR #4811.
cfallin opened PR #4811 from ra2-semantics-cleanup
to main
:
This PR removes all uses of "modify" operands on instructions in the x64
backend, and also removes all uses of "pinned vregs", or vregs that are
explicitly tied to particular physical registers. In place of both of
these mechanisms, which are legacies of the old regalloc design and
supported via compatibility code, the backend now uses operand
constraints. This is more flexible as it allows the regalloc to see the
liveranges and constraints without "reverse-engineering" move instructions.Eventually, after removing all such uses (including in other backends
and by the ABI code), we can remove the compatibility code in regalloc2,
significantly simplifying its liverange-construction frontend and
thus allowing for higher confidence in correctness as well as possibly a
bit more compilation speed.Curiously, there are a few extra move instructions now; they are likely
poor splitting decisions and I can try to chase these down later.<!--
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jameysharp submitted PR review.
jameysharp submitted PR review.
jameysharp created PR review comment:
Can the TODO comment be deleted now?
cfallin updated PR #4811 from ra2-semantics-cleanup
to main
.
cfallin updated PR #4811 from ra2-semantics-cleanup
to main
.
cfallin created PR review comment:
Yep, forgot that; fixed now. Thanks!
cfallin submitted PR review.
elliottt submitted PR review.
elliottt created PR review comment:
:tada:
elliottt created PR review comment:
Yay!
elliottt created PR review comment:
Are these extra moves expected?
elliottt submitted PR review.
elliottt created PR review comment:
I like this a lot more!
elliottt created PR review comment:
It seems like the big change here is being explicit about zeroing the temp register in the emit code for
BrTableSeq
?
cfallin submitted PR review.
cfallin created PR review comment:
It looks like it's the result of a slight overapproximation of the liverange of the rdx input and rdx output: the input is supposed to be live up to the early-point and output live starting at the late-point, but for I think fuzzbug-related reasons that I don't fully recall, I had to make fixed defs live starting at the early point. The conflict is resolved by putting the input in r11 here but doing a last-minute move. I can dig into it further in regalloc2 but it will take some deep thought; not a super-easy fix. In any case the operands express a more flexible problem so we should be able to solve it locally (within regalloc) now...
cfallin submitted PR review.
cfallin created PR review comment:
Yep, the disassembly diff is a little tricky to see (too much delta for git to line up the lines) but basically the initialization of the zeroed register changed.
elliottt submitted PR review.
cfallin merged PR #4811.
Last updated: Nov 22 2024 at 17:03 UTC