fitzgen opened PR #3653 from bitselect-isle
to main
:
This is causing a test failure, as we are generating some unnecessary
movdqa
s now. Haven't had time to look into why this is happening, but I figured I would put this WIP PR up for posterity, along with info on the failing test and unnecessary moves.CLIF:
function %bitselect_i16x8() -> i16x8 { block0: v0 = vconst.i16x8 [0 0 0 0 0 0 0 0] v1 = vconst.i16x8 [0 0 0 0 0 0 0 0] v2 = vconst.i16x8 [0 0 0 0 0 0 0 0] v3 = bitselect v0, v1, v2 return v3 }
Before:
VCode_ShowWithRRU {{ Entry block: 0 Block 0: (original IR block: block0) (instruction range: 0 .. 11) Inst 0: pushq %rbp Inst 1: movq %rsp, %rbp Inst 2: load_const VCodeConstant(0), %xmm0 Inst 3: load_const VCodeConstant(0), %xmm1 Inst 4: load_const VCodeConstant(0), %xmm2 Inst 5: pand %xmm0, %xmm1 Inst 6: pandn %xmm2, %xmm0 Inst 7: por %xmm1, %xmm0 Inst 8: movq %rbp, %rsp Inst 9: popq %rbp Inst 10: ret }}
After:
VCode_ShowWithRRU {{ Entry block: 0 Block 0: (original IR block: block0) (instruction range: 0 .. 13) Inst 0: pushq %rbp Inst 1: movq %rsp, %rbp Inst 2: load_const VCodeConstant(0), %xmm0 Inst 3: load_const VCodeConstant(0), %xmm3 Inst 4: load_const VCodeConstant(0), %xmm1 Inst 5: movdqa %xmm0, %xmm2 Inst 6: pand %xmm3, %xmm2 Inst 7: pandn %xmm1, %xmm0 Inst 8: por %xmm0, %xmm2 Inst 9: movdqa %xmm2, %xmm0 Inst 10: movq %rbp, %rsp Inst 11: popq %rbp Inst 12: ret }}
fitzgen updated PR #3653 from bitselect-isle
to main
.
fitzgen updated PR #3653 from bitselect-isle
to main
.
fitzgen updated PR #3653 from bitselect-isle
to main
.
fitzgen has marked PR #3653 as ready for review.
fitzgen requested cfallin for a review on PR #3653.
fitzgen updated PR #3653 from bitselect-isle
to main
.
cfallin submitted PR review.
fitzgen updated PR #3653 from bitselect-isle
to main
.
fitzgen updated PR #3653 from bitselect-isle
to main
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fitzgen merged PR #3653.
Last updated: Dec 23 2024 at 13:07 UTC