dheaton-arm opened PR #3362 from implement-unarrow
to main
:
Implemented the following Opcodes for the Cranelift interpreter:
Unarrow
to combine two SIMD vectors into a new vector with twice
the lanes but half the width, with signed inputs which are clamped to
0x00
.
Uunarrow
to perform the same operation asUnarrow
but treating
inputs as unsigned.
Snarrow
to perform the same operation asUnarrow
but treating
both inputs and outputs as signed, and saturating accordingly.Note that all 3 instructions saturate at the type boundaries.
Copyright (c) 2021, Arm Limited
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cfallin submitted PR review.
cfallin created PR review comment:
Could you turn this into an iterator chain?
cfallin created PR review comment:
The
u128::MAX as i128
will overflow, which I guess is fine because I think this is just using thei128
as a container for the 128 bits, immediately passed into aValue::int
call. But given that, could you useu128
instead? IMHO the unsigned types are a bit more idiomatic for "just a bit pattern"-type values.
cfallin submitted PR review.
dheaton-arm submitted PR review.
dheaton-arm created PR review comment:
Sure; I'd gone for
i128
becauseValue::int
acceptsi128
rather thanu128
.
dheaton-arm updated PR #3362 from implement-unarrow
to main
.
dheaton-arm requested cfallin for a review on PR #3362.
cfallin created PR review comment:
Ah, OK, possibly that could be changed too, but it's not terribly important in this case so I won't hold up the PR for this :-)
cfallin submitted PR review.
cfallin submitted PR review.
cfallin merged PR #3362.
Last updated: Dec 23 2024 at 12:05 UTC