Wasmtime GitHub notifications bot (Apr 09 2021 at 15:03): Wasmtime GitHub notifications bot (Apr 09 2021 at 15:03):akirilov-arm requested cfallin for a review on PR #2823.
Wasmtime GitHub notifications bot (Apr 09 2021 at 15:03):akirilov-arm opened PR #2823 from callee_saves to main:
SIMD & FP registers are now saved and restored in pairs, similarly to general-purpose registers. Also, the fix for issue #2254 has enabled us to save and to restore only the bottom 64 bits of the registers (in case of non-Baldrdash ABIs), which is the requirement from the Procedure Call Standard for the Arm 64-bit Architecture.
As for the callee-saved general-purpose registers, if a procedure needs to save and restore an odd number of them, it no longer uses store and load pair instructions for the last register.
Wasmtime GitHub notifications bot (Apr 12 2021 at 18:35):cfallin submitted PR Review.
Wasmtime GitHub notifications bot (Apr 12 2021 at 18:35):cfallin submitted PR Review.
Wasmtime GitHub notifications bot (Apr 12 2021 at 18:35):cfallin created PR Review Comment:
A comment here to explain the strategies for both cases would make it a bit clearer, I think -- something like "The Baldrdash ABI saves whole (16-byte) clobbered vector registers, so there is no need to worry about 16-byte stack alignment. The SystemV (AAPCS) ABI saves half (8-byte) clobbered vector registers, so we round up if odd."?
Wasmtime GitHub notifications bot (Apr 13 2021 at 10:24):akirilov-arm updated PR #2823 from callee_saves to main.
Wasmtime GitHub notifications bot (Apr 13 2021 at 19:24):akirilov-arm updated PR #2823 from callee_saves to main.
Wasmtime GitHub notifications bot (Apr 13 2021 at 22:35):cfallin merged PR #2823.
Last updated: Dec 23 2024 at 12:05 UTC