jlb6740 opened PR #2440 from remaining_simd_conversions
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jlb6740 updated PR #2440 from remaining_simd_conversions
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jlb6740 updated PR #2440 from remaining_simd_conversions
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jlb6740 updated PR #2440 from remaining_simd_conversions
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jlb6740 updated PR #2440 from remaining_simd_conversions
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jlb6740 updated PR #2440 from remaining_simd_conversions
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jlb6740 updated PR #2440 from remaining_simd_conversions
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jlb6740 updated PR #2440 from remaining_simd_conversions
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jlb6740 has marked PR #2440 as ready for review.
jlb6740 requested bnjbvr for a review on PR #2440.
jlb6740 requested abrown for a review on PR #2440.
jlb6740 requested abrown and bnjbvr for a review on PR #2440.
jlb6740 requested cfallin, abrown and bnjbvr for a review on PR #2440.
cfallin submitted PR Review.
cfallin submitted PR Review.
cfallin created PR Review Comment:
This explanation is somewhat hard to follow; I think it would help to write out the expressions for each intermediate result. Perhaps also a table showing values for each of the four cases: negative, 0..INT_MAX, INT_MAX+1..UINT_MAX, above UINT_MAX.
cfallin created PR Review Comment:
I just noticed that here and above for
FcvtToSintSat
we assumeI32X4
. Is it the case that no other vector lane width will be used with this opcode? If so, can we assert on the input type (e.g.,assert_eq!(types::F32X4, ctx.input_ty(insn, 0)
)?
jlb6740 submitted PR Review.
jlb6740 created PR Review Comment:
Cool .. good suggestion. I'll make it easier to follow and highlight some specific cases.
jlb6740 submitted PR Review.
jlb6740 created PR Review Comment:
Good point. I'll point some assertions in.
jlb6740 updated PR #2440 from remaining_simd_conversions
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jlb6740 requested cfallin, abrown and bnjbvr for a review on PR #2440.
jlb6740 updated PR #2440 from remaining_simd_conversions
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jlb6740 updated PR #2440 from remaining_simd_conversions
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jlb6740 updated PR #2440 from remaining_simd_conversions
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cfallin submitted PR Review.
cfallin merged PR #2440.
Last updated: Dec 23 2024 at 12:05 UTC