abrown opened PR #2230 from lane to main:
This change adds x64 implementations for
extract_lane,replace_lane,shuffle, andswizzleas well as some saturating addition (necessary forswizzle). I cannot yet enable thesimd_lane.wasttest because it also uses other instructions likesplat,all_true, andany_truebut I did verify that the assertions insimd_lane.wastthat do not use these instructions pass.
bjorn3 submitted PR Review.
bjorn3 created PR Review Comment:
The frontend could have incorrectly passed for example 2 as lane. Maybe add a
debug_assert!thatlane < src_ty.lane_count()?
abrown submitted PR Review.
abrown created PR Review Comment:
These assertions were only valid for
CMPP*; with the addition ofPINSR*andPEXTR*the reg classes can come from I64 in either slot (perhaps we could keep theimmassertion withimm < 16).
cfallin submitted PR Review.
cfallin submitted PR Review.
cfallin created PR Review Comment:
Little style preference mostly, but maybe do a
let swapped = match *op { ... };and thenlet (dst, src) = if swapped { ... } else { ... };? This keeps the code duplication down in case we add more logic around theemit_...()call later.
cfallin created PR Review Comment:
I'd prefer an
assert!()here to ensure we avoid those opcodes, then avoid the extra nesting level of the if/else.
cfallin created PR Review Comment:
Doc comment and/or better name for this field perhaps? All the others are self-explanatory but I'm not sure what just
wmeans without context...
cfallin created PR Review Comment:
Also, on preview below, the raw bool params to the encoding functions are somewhat bothersome; can we make this an enum instead for more self-documenting goodness?
cfallin created PR Review Comment:
comment clarification request: somewhat subtle, but let's note that the CLIF instruction spec also specifies this behavior. In theory we might have chosen a simpler behavior at the CLIF level and done the Wasm-required magic in the translation; the swizzle op in CLIF just happens to be aligned with Wasm. (It probably doesn't matter much and is unlikely to change, but precision doesn't hurt...).
bnjbvr submitted PR Review.
bnjbvr submitted PR Review.
bnjbvr submitted PR Review.
bnjbvr created PR Review Comment:
Even better, for static goodness: use a different Vcode instruction for these two opcodes, so that the error becomes a compile time error.
bnjbvr created PR Review Comment:
While this may map the intel manual more closely, it's unusual and quite disturbing to see an input named
dst0here, and it could lead to mental mapping errors (e.g. this can be written to without any issue). Can you name thisin_vecor something like this?
bnjbvr created PR Review Comment:
Also, the tradition has to name this
is64to indicate a 64-bits operation or something along those lines.
abrown submitted PR Review.
abrown created PR Review Comment:
I went with the
assert!here; it's a bit burdensome to create newInstvariants and creating new ones just adds to the chaos of deciding which variant to pick during lowering.
abrown submitted PR Review.
abrown created PR Review Comment:
Added additional documentation here. But note that we shouldn't translate the semantics at the Wasm-to-CLIF level because that would disadvantage ARM since the semantics of their instruction matches the Wasm SIMD semantics. (If you look at issues in the Wasm SIMD repository I've brought up several times how the Wasm SIMD semantics are skewed towards matching ARM semantics).
abrown updated PR #2230 from lane to main:
This change adds x64 implementations for
extract_lane,replace_lane,shuffle, andswizzleas well as some saturating addition (necessary forswizzle). I cannot yet enable thesimd_lane.wasttest because it also uses other instructions likesplat,all_true, andany_truebut I did verify that the assertions insimd_lane.wastthat do not use these instructions pass.
abrown merged PR #2230.
Last updated: Dec 13 2025 at 21:03 UTC