Stream: git-wasmtime

Topic: wasmtime / PR #2103 cranelift: arm32 codegen


view this post on Zulip Wasmtime GitHub notifications bot (Aug 06 2020 at 09:50):

jmkrauz opened PR #2103 from arm32-codegen to main:

This commit adds arm32 Thumb2 code generation for some IR insts.
I have used machinst backend and followed Aarch64 implementation as an example.

Floating-point instructions are not supported, because regalloc
does not seem to allow to represent overlapping register classes,
which are needed by VFP/Neon.

Another lacking feature is support for I64 and I128 types.

An abi implementation is not complete, however it makes it possible
to run simple clif tests.

It may be a first step towards #1173.

This PR contains instruction emission test and clif tests for IR insts.

I don't know well who could review this.

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view this post on Zulip Wasmtime GitHub notifications bot (Aug 06 2020 at 10:01):

bjorn3 submitted PR Review.

view this post on Zulip Wasmtime GitHub notifications bot (Aug 06 2020 at 10:01):

bjorn3 created PR Review Comment:

Maybe use x86 or riscv instead?

view this post on Zulip Wasmtime GitHub notifications bot (Aug 06 2020 at 11:11):

jmkrauz submitted PR Review.

view this post on Zulip Wasmtime GitHub notifications bot (Aug 06 2020 at 11:11):

jmkrauz created PR Review Comment:

I believe some of the tests here or in regalloc/pressure.rs use the fact that S, D and Q registers overlap. I am not sure if we can achieve something similar with x86 or risc-v registers.

view this post on Zulip Wasmtime GitHub notifications bot (Aug 06 2020 at 16:18):

cfallin requested cfallin for a review on PR #2103.

view this post on Zulip Wasmtime GitHub notifications bot (Aug 26 2020 at 11:13):

jmkrauz updated PR #2103 from arm32-codegen to main:

This commit adds arm32 Thumb2 code generation for some IR insts.
I have used machinst backend and followed Aarch64 implementation as an example.

Floating-point instructions are not supported, because regalloc
does not seem to allow to represent overlapping register classes,
which are needed by VFP/Neon.

Another lacking feature is support for I64 and I128 types.

An abi implementation is not complete, however it makes it possible
to run simple clif tests.

It may be a first step towards #1173.

This PR contains instruction emission test and clif tests for IR insts.

I don't know well who could review this.

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Please ensure that the following steps are all taken care of before submitting
the PR.

Please ensure all communication adheres to the code of conduct.
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view this post on Zulip Wasmtime GitHub notifications bot (Sep 16 2020 at 10:14):

jmkrauz updated PR #2103 from arm32-codegen to main:

This commit adds arm32 Thumb2 code generation for some IR insts.
I have used machinst backend and followed Aarch64 implementation as an example.

Floating-point instructions are not supported, because regalloc
does not seem to allow to represent overlapping register classes,
which are needed by VFP/Neon.

Another lacking feature is support for I64 and I128 types.

An abi implementation is not complete, however it makes it possible
to run simple clif tests.

It may be a first step towards #1173.

This PR contains instruction emission test and clif tests for IR insts.

I don't know well who could review this.

<!--
Please ensure that the following steps are all taken care of before submitting
the PR.

Please ensure all communication adheres to the code of conduct.
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view this post on Zulip Wasmtime GitHub notifications bot (Sep 22 2020 at 10:50):

jmkrauz updated PR #2103 from arm32-codegen to main:

This commit adds arm32 Thumb2 code generation for some IR insts.
I have used machinst backend and followed Aarch64 implementation as an example.

Floating-point instructions are not supported, because regalloc
does not seem to allow to represent overlapping register classes,
which are needed by VFP/Neon.

Another lacking feature is support for I64 and I128 types.

An abi implementation is not complete, however it makes it possible
to run simple clif tests.

It may be a first step towards #1173.

This PR contains instruction emission test and clif tests for IR insts.

I don't know well who could review this.

<!--
Please ensure that the following steps are all taken care of before submitting
the PR.

Please ensure all communication adheres to the code of conduct.
-->

view this post on Zulip Wasmtime GitHub notifications bot (Sep 22 2020 at 10:53):

jmkrauz updated PR #2103 from arm32-codegen to main:

This commit adds arm32 Thumb2 code generation for some IR insts.
I have used machinst backend and followed Aarch64 implementation as an example.

Floating-point instructions are not supported, because regalloc
does not seem to allow to represent overlapping register classes,
which are needed by VFP/Neon.

Another lacking feature is support for I64 and I128 types.

An abi implementation is not complete, however it makes it possible
to run simple clif tests.

It may be a first step towards #1173.

This PR contains instruction emission test and clif tests for IR insts.

I don't know well who could review this.

<!--
Please ensure that the following steps are all taken care of before submitting
the PR.

Please ensure all communication adheres to the code of conduct.
-->

view this post on Zulip Wasmtime GitHub notifications bot (Sep 22 2020 at 16:07):

cfallin merged PR #2103.


Last updated: Dec 23 2024 at 12:05 UTC