Wasmtime GitHub notifications bot (Jul 17 2020 at 21:55): Wasmtime GitHub notifications bot (Jul 17 2020 at 21:55):cfallin opened PR #2042 from aarch64-fix-regshift-mask to main:
We had previously fixed a bug in which constant shift amounts should be
masked to modulo the number of bits in the operand (#1999); however, we
did not fix the analogous case for shifts incorporated into the second
register argument of ALU instructions that support integrated shifts.
This failure to mask resulted in illegal instructions being generated,
e.g. in https://bugzilla.mozilla.org/show_bug.cgi?id=1653502. This PR
fixes the issue by masking the amount, as the shift semantics require.<!--
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Wasmtime GitHub notifications bot (Jul 17 2020 at 21:55):cfallin requested bnjbvr and julian-seward1 for a review on PR #2042.
Wasmtime GitHub notifications bot (Jul 17 2020 at 21:55):cfallin requested bnjbvr and julian-seward1 for a review on PR #2042.
Wasmtime GitHub notifications bot (Jul 17 2020 at 21:55):cfallin updated PR #2042 from aarch64-fix-regshift-mask to main:
We had previously fixed a bug in which constant shift amounts should be
masked to modulo the number of bits in the operand (#1999); however, we
did not fix the analogous case for shifts incorporated into the second
register argument of ALU instructions that support integrated shifts.
This failure to mask resulted in illegal instructions being generated,
e.g. in https://bugzilla.mozilla.org/show_bug.cgi?id=1653502. This PR
fixes the issue by masking the amount, as the shift semantics require.<!--
Please ensure that the following steps are all taken care of before submitting
the PR.
[ ] This has been discussed in issue #..., or if not, please tell us why
here.[ ] A short description of what this does, why it is needed; if the
description becomes long, the matter should probably be discussed in an issue
first.[ ] This PR contains test cases, if meaningful.
- [ ] A reviewer from the core maintainer team has been assigned for this PR.
If you don't know who could review this, please indicate so. The list of
suggested reviewers on the right can help you.Please ensure all communication adheres to the code of conduct.
-->
Wasmtime GitHub notifications bot (Jul 17 2020 at 21:55):cfallin edited PR #2042 from aarch64-fix-regshift-mask to main:
We had previously fixed a bug in which constant shift amounts should be
masked to modulo the number of bits in the operand; however, we
did not fix the analogous case for shifts incorporated into the second
register argument of ALU instructions that support integrated shifts.
This failure to mask resulted in illegal instructions being generated,
e.g. in https://bugzilla.mozilla.org/show_bug.cgi?id=1653502. This PR
fixes the issue by masking the amount, as the shift semantics require.<!--
Please ensure that the following steps are all taken care of before submitting
the PR.
[ ] This has been discussed in issue #..., or if not, please tell us why
here.[ ] A short description of what this does, why it is needed; if the
description becomes long, the matter should probably be discussed in an issue
first.[ ] This PR contains test cases, if meaningful.
- [ ] A reviewer from the core maintainer team has been assigned for this PR.
If you don't know who could review this, please indicate so. The list of
suggested reviewers on the right can help you.Please ensure all communication adheres to the code of conduct.
-->
Wasmtime GitHub notifications bot (Jul 18 2020 at 06:46):julian-seward1 submitted PR Review.
Wasmtime GitHub notifications bot (Jul 19 2020 at 02:33):cfallin merged PR #2042.
Last updated: Dec 23 2024 at 12:05 UTC