Stream: git-wasmtime

Topic: wasmtime / PR #1865 AArch64: make use of reg-reg-extend a...

Wasmtime GitHub notifications bot (Jun 11 2020 at 19:30):

cfallin opened PR #1865 from aarch64-amode-reg-reg-extend to master:

When a load/store instruction needs an address of the form v0 + uextend(v1) or v0 + sextend(v1) (or the commuted forms thereof), we
currently generate a separate zero/sign-extend operation and then use a
plain [rA, rB] addressing mode. This patch extends lower_address()
to look at both addends of an address if it has two addends and a zero
offset, recognize extension operations, and incorporate them directly
into a [rA, rB, UXTW] or [rA, rB, SXTW] form. This should improve
our performence on WebAssembly workloads, at least, because we often see
a 64-bit linear memory base indexed by a 32-bit (Wasm) pointer value.

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Wasmtime GitHub notifications bot (Jun 11 2020 at 19:30):

cfallin requested julian-seward1 for a review on PR #1865.

Wasmtime GitHub notifications bot (Jun 12 2020 at 12:36):

julian-seward1 submitted PR Review.

Wasmtime GitHub notifications bot (Jun 12 2020 at 12:36):

julian-seward1 submitted PR Review.

Wasmtime GitHub notifications bot (Jun 12 2020 at 12:36):

julian-seward1 created PR Review Comment:

These 4 clauses computing parts are a bit duplication-ful. If the logic gets extended at some point to deal with 16- or 8-bit indices, it'll be even worse. Hence: is there some way to reduce the level duplication, without making it harder to follow?

Wasmtime GitHub notifications bot (Jun 12 2020 at 16:57):

cfallin updated PR #1865 from aarch64-amode-reg-reg-extend to master:

When a load/store instruction needs an address of the form v0 + uextend(v1) or v0 + sextend(v1) (or the commuted forms thereof), we
currently generate a separate zero/sign-extend operation and then use a
plain [rA, rB] addressing mode. This patch extends lower_address()
to look at both addends of an address if it has two addends and a zero
offset, recognize extension operations, and incorporate them directly
into a [rA, rB, UXTW] or [rA, rB, SXTW] form. This should improve
our performence on WebAssembly workloads, at least, because we often see
a 64-bit linear memory base indexed by a 32-bit (Wasm) pointer value.

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Wasmtime GitHub notifications bot (Jun 12 2020 at 16:58):

cfallin submitted PR Review.

Wasmtime GitHub notifications bot (Jun 12 2020 at 16:58):

cfallin created PR Review Comment:

Sure, factored out (i) the signed/unsigned duality, with a new helper maybe_input_insn_multi; and (ii) the two commutative cases, with a for-loop. Thanks!

Wasmtime GitHub notifications bot (Jun 12 2020 at 17:41):

cfallin updated PR #1865 from aarch64-amode-reg-reg-extend to master:

When a load/store instruction needs an address of the form v0 + uextend(v1) or v0 + sextend(v1) (or the commuted forms thereof), we
currently generate a separate zero/sign-extend operation and then use a
plain [rA, rB] addressing mode. This patch extends lower_address()
to look at both addends of an address if it has two addends and a zero
offset, recognize extension operations, and incorporate them directly
into a [rA, rB, UXTW] or [rA, rB, SXTW] form. This should improve
our performence on WebAssembly workloads, at least, because we often see
a 64-bit linear memory base indexed by a 32-bit (Wasm) pointer value.

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  first.

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Wasmtime GitHub notifications bot (Jun 12 2020 at 18:58):

cfallin merged PR #1865.

Last updated: Nov 22 2024 at 16:03 UTC