jlb6740 opened PR #1862 from vcode-add-store
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bjorn3 submitted PR Review.
bjorn3 submitted PR Review.
bjorn3 created PR Review Comment:
ty.is_float()
jlb6740 updated PR #1862 from vcode-add-store
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jlb6740 submitted PR Review.
jlb6740 created PR Review Comment:
Hi thanks. This was copied over from the Aarch64 for prep for some lowering that is not included in this patch. I will use your suggestion when needed.
jlb6740 edited PR Review Comment.
jlb6740 edited PR Review Comment.
jlb6740 updated PR #1862 from vcode-add-store
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jlb6740 updated PR #1862 from vcode-add-store
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jlb6740 updated PR #1862 from vcode-add-store
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jlb6740 updated PR #1862 from vcode-add-store
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bnjbvr submitted PR Review.
bnjbvr created PR Review Comment:
Should this comment be removed?
bnjbvr created PR Review Comment:
Out of curiosity, is
movd
better thanmovsd
in this case?
bnjbvr submitted PR Review.
bnjbvr created PR Review Comment:
nit: TODO here
alexcrichton edited PR #1862 from vcode-add-store
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jlb6740 submitted PR Review.
jlb6740 created PR Review Comment:
I was first implementing for movd (set in lower.rs) because this was a 32 bit move, else I'd prefer movsd over movq since movsd is intended for fp.
jlb6740 edited PR Review Comment.
jlb6740 submitted PR Review.
jlb6740 created PR Review Comment:
Looks out of place. Will remove.
jlb6740 updated PR #1862 from vcode-add-store
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jlb6740 updated PR #1862 from vcode-add-store
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jlb6740 updated PR #1862 from vcode-add-store
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jlb6740 updated PR #1862 from vcode-add-store
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jlb6740 requested bnjbvr for a review on PR #1862.
bnjbvr submitted PR Review.
bnjbvr submitted PR Review.
bnjbvr created PR Review Comment:
nit: can you keep it in the sections of vcode insts labelled with a "FP instructions" header, please? I tried to order the vcode instructions in logical groups, and it would be nice if we tried to enforce it.
(also nit: code comments are allowed to use 99 chars per line, as in the rest of the code base, so the wrapping around can be reverted too)
bnjbvr created PR Review Comment:
Right regarding 32 vs 64 bits; then my question is, is movd better than movss? movss can be encoded with F3 0F 11, so there's no difference in size; and we do use movss for reg to reg moves, and if I'm understanding correctly for f64 we'll use movsd for both RR and RM. I am not asking to change, but trying to understand; the only argument in favor of movss might be consistency with f64 here.
bnjbvr created PR Review Comment:
Can you add one test that uses one of the high registers requiring the REX prefix, please?
bnjbvr submitted PR Review.
bnjbvr created PR Review Comment:
Actually, when looking at the output of llvm and gcc, both use movss in this case. Also Intel's optimization guide seems to suggest there might be an extra overhead in using movd for FP registers? (3.5.2.3 Bypass between Execution Domains)
So could we change it to use movss instead, please? (and ditto for loads)
jlb6740 updated PR #1862 from vcode-add-store
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jlb6740 submitted PR Review.
jlb6740 created PR Review Comment:
Right ... I've done this with a new test for Movss. Thanks for pushing on the movss :+1:, not sure what I was overlooking there.
jlb6740 merged PR #1862.
Last updated: Dec 23 2024 at 13:07 UTC