ColonelToad opened PR #14942 from ColonelToad:fix/14691-riscv64-swizzle-splat-zext to bytecodealliance:main:
Fixes #14691.
vrgather.vxuses the full scalar register as the vector index, but the upper bits of an i8/i16/i32 value are not guaranteed to be zero. Zero-extend the splat index before lowering so out-of-range upper bits cannot change the result.Added RISC-V ISA expectations and a runtime regression test using a dirty upper byte.
Tests:
- cargo run -p cranelift-tools -- test cranelift/filetests/filetests/isa/riscv64/simd-swizzle.clif
- cargo run -p cranelift-tools -- test cranelift/filetests/filetests/runtests/simd-swizzle.clif
- cargo fmt --all -- --check
The RISC-V runtime portion is covered by the QEMU CI job.
ColonelToad removed the review request for wasmtime-compiler-reviewers from PR #14942.
ColonelToad requested fitzgen for a review on PR #14942.
ColonelToad requested wasmtime-compiler-reviewers for a review on PR #14942.
github-actions[bot] added the label cranelift on PR #14942.
:thumbs_up: fitzgen submitted PR review:
Thanks!
fitzgen added PR #14942 Cranelift: zero-extend RISC-V swizzle splat index to the merge queue.
fitzgen removed PR #14942 Cranelift: zero-extend RISC-V swizzle splat index from the merge queue.
:check: fitzgen merged PR #14942.
Last updated: Oct 31 2026 at 23:03 UTC