Stream: git-wasmtime

Topic: wasmtime / PR #14930 x64: add APX NDD lowering for simple...

view this post on Zulip Wasmtime GitHub notifications bot (Oct 22 2026 at 00:16):

jlb6740 opened PR #14930 from jlb6740:apx-patch-lower-simple-binary-ops to bytecodealliance:main:

First of a series splitting #14696 into one PR per instruction class. Adds the
APX NDD (new data destination) forms of sub, and, or and xor for 64-bit
register-register ops, following the pattern #13916 established for add: an
RVM encoding promoted into EVEX map 4 with ND = 1, plus a lowering rule
guarded on use_apx. The separate destination means the register allocator no
longer needs a move to preserve a live input. has_apx is off by default, so
nothing changes unless it's enabled. More NDD patches to follow.

view this post on Zulip Wasmtime GitHub notifications bot (Oct 22 2026 at 00:16):

jlb6740 requested fitzgen for a review on PR #14930.

view this post on Zulip Wasmtime GitHub notifications bot (Oct 22 2026 at 00:16):

jlb6740 requested wasmtime-compiler-reviewers for a review on PR #14930.

view this post on Zulip Wasmtime GitHub notifications bot (Oct 22 2026 at 00:16):

jlb6740 removed the review request for wasmtime-compiler-reviewers from PR #14930.

view this post on Zulip Wasmtime GitHub notifications bot (Oct 22 2026 at 00:24):

jlb6740 updated PR #14930.

view this post on Zulip Wasmtime GitHub notifications bot (Oct 22 2026 at 02:53):

github-actions[bot] added the label cranelift:area:x64 on PR #14930.

view this post on Zulip Wasmtime GitHub notifications bot (Oct 22 2026 at 02:53):

github-actions[bot] added the label cranelift on PR #14930.

view this post on Zulip Wasmtime GitHub notifications bot (Oct 22 2026 at 17:32):

jlb6740 commented on PR #14930:

Note that this patch, and none of the patches to come based on #14969, are gated on the regalloc work https://github.com/bytecodealliance/regalloc2/pull/267 and can go in before.

view this post on Zulip Wasmtime GitHub notifications bot (Oct 22 2026 at 19:50):

:thumbs_up: fitzgen submitted PR review:

It would be interesting to check in instruction encoding whether the first operand and destination are (1) actually different registers or (2) in the new register set, and if neither is true then we should be able to use an old (more compact) encoding, correct? This would require a bit more machinery than currently exists, as I believe that we go immediately from MInst to assembler instruction encoding automatically, but seems like something that we should have a tracking issue for and would probably want to have before enabling APX by default on supported hardware.

view this post on Zulip Wasmtime GitHub notifications bot (Oct 22 2026 at 19:50):

fitzgen added PR #14930 x64: add APX NDD lowering for simple integer binary ops to the merge queue.

view this post on Zulip Wasmtime GitHub notifications bot (Oct 22 2026 at 20:31):

:check: fitzgen merged PR #14930.

view this post on Zulip Wasmtime GitHub notifications bot (Oct 22 2026 at 20:31):

fitzgen removed PR #14930 x64: add APX NDD lowering for simple integer binary ops from the merge queue.

Last updated: Oct 31 2026 at 23:03 UTC