Wasmtime GitHub notifications bot (Oct 13 2026 at 03:27): Wasmtime GitHub notifications bot (Oct 13 2026 at 03:27):jlb6740 opened PR #14696 from jlb6740:apx-ndd-instructions to bytecodealliance:main:
Adds Intel APX NDD support to the x64 backend, one instruction class per commit. has_apx is off by default, so nothing changes unless it's enabled. Happy to break this into several PRs if that's easier to review.
NDD gives the legacy two-operand integer instructions a separate destination, so the copy that preserves a live input goes away. movq %rdi, %rax + addq %rdx, %rax becomes addq %rdx, %rdi, %rax.
That's add, sub, and, or, xor, neg, not, imul, cmov (all 16 conditions), adc, sbb, shl, shr, sar, rol, ror and shld, 32- and 64-bit, with register, memory and immediate sources. 94 encodings. I can't benchmark any of it without hardware, so all I have is instruction counts from the filetests: select goes 3 to 2, imul 3 to 2, i128 add and sub 4 to 2, shift by an immediate 2 to 1, shld 2 to 1.
Left out on purpose: shifts by a register amount, since BMI2's shlx/shrx/sarx already do better (any register rather than just cl, and no flag write), and rotates by an immediate, which rorx covers the same way. The complementary halves are in, because BMI2 can't encode them: shifts by an immediate, and rotates by cl. 8- and 16-bit ops are still widened to 32-bit. No NF forms, a big independent chunk of APX. cfcmov, push2 and pop2 are new instructions rather than promotions. inc, dec, rcl, rcr, adcx, adox and shrd aren't in cranelift-assembler-x64 at all, so there was nothing to promote.
Every commit adds precise-output filetests and all 1332 pass. Encodings are checked against XED, the only oracle in tree that decodes APX. Capstone can't do map 4, so fuzz::roundtrip skips all of this. One commit adds a deterministic test over every APX form comparing bytes and printed text, with a floor so it fails if the enumeration stops finding them.
With no APX hardware I ran it under Intel SDE too: 32 functions, 52 assertions, picked so a reversed operand order or flipped carry gives a wrong answer and not just a different encoding. All pass. Natively the same binary takes SIGILL, which is how I know the instructions really were emitted. Those tests aren't in the PR because test run with has_apx silently doesn't run: is_isa_compatible checks against cranelift-native's host flags, which have no APX detection (apxf is unstable, rust-lang/rust#139284), so it's skipped and reported as passing. I confirmed that by asserting something I knew was wrong and watching it pass. Probably worth its own issue.
Two notes. The adc/sbb commit is wider than its subject: those rules hang off the raw add/sub constructors, the path i128 and the overflow-checked forms take, so x64_add and x64_sub change generally. And watch for opcodes that move in map 4: shld's imm8 form is 0x24, not 0f a4, and shrd, adcx and adox shift too, while the cl forms, imul and cmov keep theirs.
Wasmtime GitHub notifications bot (Oct 13 2026 at 05:52):github-actions[bot] added the label cranelift:area:x64 on PR #14696.
Wasmtime GitHub notifications bot (Oct 13 2026 at 05:52):github-actions[bot] added the label cranelift on PR #14696.
Last updated: Oct 31 2026 at 23:03 UTC