avanhatt opened PR #14608 from avanhatt:veri-require-illtyped to bytecodealliance:main:
#14526 exposes an issue where an
optISLE rule could build an Clif term with invalid type widths (in that case,irreduceto a wider width than the current width). This would cause the midend to output invalid clif that would fail the validator (or crash the backend).The verifier did not catch this for a few different reasons:
- The
irreduce(and related) specs need the width requirement expressed as a precondition (require) when used on the RHS of a rule.- Our type inference should not use Clif type constraints when a term is used on the RHS. Supporting this also motivates allowing a
modelto specify a fixed list of types, e.g,Valueis for now 8, 16, 32, or 64 bits in the verifier.For the most clear error messages, this PR also explicitly calls out the "ill typed width" as part of the counterexample.
Draft for now so I can check it errors in CI when #14526 is reverted.
Note this is related to also catching #14566 in the verifier step, but will not yet fix it because we do not explicitly model
lanesin the type's verification model.
avanhatt edited PR #14608:
Note: primarily a
cranelift/isle/veri/specchange, with a small change to the ISLE parser for new spec form.#14526 exposes an issue where an
optISLE rule could build an Clif term with invalid type widths (in that case,irreduceto a wider width than the current width). This would cause the midend to output invalid clif that would fail the validator (or crash the backend).The verifier did not catch this for a few different reasons:
- The
irreduce(and related) specs need the width requirement expressed as a precondition (require) when used on the RHS of a rule.- Our type inference should not use Clif type constraints when a term is used on the RHS. Supporting this also motivates allowing a
modelto specify a fixed list of types, e.g,Valueis for now 8, 16, 32, or 64 bits in the verifier.For the most clear error messages, this PR also explicitly calls out the "ill typed width" as part of the counterexample.
Draft for now so I can check it errors in CI when #14526 is reverted.
Note this is related to also catching #14566 in the verifier step, but will not yet fix it because we do not explicitly model
lanesin the type's verification model.
github-actions[bot] added the label cranelift on PR #14608.
github-actions[bot] added the label isle on PR #14608.
github-actions[bot] commented on PR #14608:
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avanhatt updated PR #14608.
avanhatt commented on PR #14608:
Reverting
a01376fto test for CI failure
avanhatt commented on PR #14608:
CI fails as expected on the old rules. Lightly edited output:
=== veri: cranelift/isle/veri/configs/opt.args === === VERIFICATION FAILURES (6) === FAILURE #1305 cranelift/codegen/src/opts/shifts.isle line 83 (instantiation 333) .veriisle/expansions/01305/333/failure.out #1305 cranelift/codegen/src/opts/shifts.isle line 83 instantiation=333 ill-typed term reachable: cranelift/codegen/src/spec/inst_specs.isle line 492: e177: cannot sign extend to smaller width model: // ... FAILURE #1305 cranelift/codegen/src/opts/shifts.isle line 83 (instantiation 334) .veriisle/expansions/01305/334/failure.out #1305 cranelift/codegen/src/opts/shifts.isle line 83 instantiation=334 ill-typed term reachable: cranelift/codegen/src/spec/inst_specs.isle line 492: e177: cannot sign extend to smaller width model: // ... FAILURE #1305 cranelift/codegen/src/opts/shifts.isle line 83 (instantiation 704) .veriisle/expansions/01305/704/failure.out #1305 cranelift/codegen/src/opts/shifts.isle line 83 instantiation=704 ill-typed term reachable: cranelift/codegen/src/spec/inst_specs.isle line 492: e177: cannot sign extend to smaller width model: // ... FAILURE #1309 cranelift/codegen/src/opts/shifts.isle line 87 (instantiation 333) .veriisle/expansions/01309/333/failure.out #1309 cranelift/codegen/src/opts/shifts.isle line 87 instantiation=333 ill-typed term reachable: cranelift/codegen/src/spec/inst_specs.isle line 486: e177: cannot zero extend to smaller width model: // ... FAILURE #1309 cranelift/codegen/src/opts/shifts.isle line 87 (instantiation 334) .veriisle/expansions/01309/334/failure.out // ... FAILURE #1309 cranelift/codegen/src/opts/shifts.isle line 87 (instantiation 704) .veriisle/expansions/01309/704/failure.out #1309 cranelift/codegen/src/opts/shifts.isle line 87 instantiation=704 ill-typed term reachable: cranelift/codegen/src/spec/inst_specs.isle line 486: e177: cannot zero extend to smaller width model: // ...
avanhatt updated PR #14608.
avanhatt edited PR #14608:
Note: primarily a
cranelift/isle/veri/specchange, with a small change to the ISLE parser for new spec form.#14526 exposes an issue where an
optISLE rule could build an Clif term with invalid type widths (in that case,ireduceto a wider width than the current width). This would cause the midend to output invalid clif that would fail the validator (or crash the backend).The verifier did not catch this for a few different reasons:
- The
ireduce(and related) specs need the width requirement expressed as a precondition (require) when used on the RHS of a rule.- Our type inference should not use Clif type constraints when a term is used on the RHS. Supporting this also motivates allowing a
modelto specify a fixed list of types, e.g,Valueis for now 8, 16, 32, or 64 bits in the verifier.For the most clear error messages, this PR also explicitly calls out the "ill typed width" as part of the counterexample.
Draft for now so I can check it errors in CI when #14526 is reverted.
Note this is related to also catching #14566 in the verifier step, but will not yet fix it because we do not explicitly model
lanesin the type's verification model.
avanhatt has marked PR #14608 as ready for review.
avanhatt requested alexcrichton for a review on PR #14608.
avanhatt requested wasmtime-compiler-reviewers for a review on PR #14608.
alexcrichton unassigned alexcrichton from PR #14608 ISLE: veri: error on opt RHS building ill-typed clif terms.
alexcrichton requested cfallin for a review on PR #14608.
alexcrichton commented on PR #14608:
Redirecting to @cfallin as he's more familiar with this than I, but it may also be a moment as I think his queue is a bit large at this time
cfallin commented on PR #14608:
Working through reading/triaging my backlog now but I should be able to get to this soon!
:thumbs_up: cfallin submitted PR review:
Seems reasonable to me -- thanks!
cfallin added PR #14608 ISLE: veri: error on opt RHS building ill-typed clif terms to the merge queue.
:check: cfallin merged PR #14608.
cfallin removed PR #14608 ISLE: veri: error on opt RHS building ill-typed clif terms from the merge queue.
Last updated: Oct 11 2026 at 04:10 UTC