Stream: git-wasmtime

Topic: wasmtime / PR #14545 riscv64: allow f16 vector bit operat...


view this post on Zulip Wasmtime GitHub notifications bot (Oct 05 2026 at 16:27):

dotcom07 opened PR #14545 from dotcom07:fix/riscv64-f16-bit-ops to bytecodealliance:main:

Fixes #12195.

Several RISC-V lowering rules require Zvfh for f16 vectors even when they only use the bit representation. With only the base V extension, this causes compilation failures, including panics when lowering f16x8 bitcasts and loads/stores.

The f16x8 to i128 bitcast in #12195 is one such case.

Since Cranelift has no dedicated type for raw bits, this checks support using an integer vector type with the same lane width and lane count, while preserving the original type. This applies to loads/stores, constants, bitcasts, select, and bitwise AND/OR/XOR/NOT, which can use base V instructions without requiring FP16 arithmetic support.

Adds precise-output filetests for these paths and runs the existing f16 vector constant test with has_zvfh disabled. The RISC-V filetests pass. Copy and bitcast results were also checked under QEMU 9.2.0 with and without Zvfh. The original function from #12195 also returns the expected result under QEMU with Zvfh disabled.

view this post on Zulip Wasmtime GitHub notifications bot (Oct 05 2026 at 16:27):

dotcom07 requested cfallin for a review on PR #14545.

view this post on Zulip Wasmtime GitHub notifications bot (Oct 05 2026 at 16:27):

dotcom07 requested wasmtime-compiler-reviewers for a review on PR #14545.

view this post on Zulip Wasmtime GitHub notifications bot (Oct 05 2026 at 16:40):

dotcom07 updated PR #14545.

view this post on Zulip Wasmtime GitHub notifications bot (Oct 05 2026 at 17:48):

github-actions[bot] added the label cranelift on PR #14545.

view this post on Zulip Wasmtime GitHub notifications bot (Oct 05 2026 at 17:48):

github-actions[bot] added the label isle on PR #14545.

view this post on Zulip Wasmtime GitHub notifications bot (Oct 05 2026 at 18:54):

github-actions[bot] commented on PR #14545:

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cc @avanhatt, @cfallin, @fitzgen, @mmcloughlin

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view this post on Zulip Wasmtime GitHub notifications bot (Oct 08 2026 at 16:55):

fitzgen commented on PR #14545:

FYI: maintainers are a bit swamped at the moment so reviews might be a little delayed, thanks for your patience!

view this post on Zulip Wasmtime GitHub notifications bot (Oct 09 2026 at 18:58):

:thumbs_up: cfallin submitted PR review:

Thanks!

view this post on Zulip Wasmtime GitHub notifications bot (Oct 09 2026 at 18:58):

cfallin added PR #14545 riscv64: allow f16 vector bit operations without Zvfh to the merge queue.

view this post on Zulip Wasmtime GitHub notifications bot (Oct 09 2026 at 19:20):

:check: cfallin merged PR #14545.

view this post on Zulip Wasmtime GitHub notifications bot (Oct 09 2026 at 19:20):

cfallin removed PR #14545 riscv64: allow f16 vector bit operations without Zvfh from the merge queue.


Last updated: Oct 11 2026 at 04:10 UTC