Wasmtime GitHub notifications bot (Oct 04 2026 at 14:57): Wasmtime GitHub notifications bot (Oct 04 2026 at 14:57):dotcom07 opened PR #14524 from dotcom07:fix/riscv64-inline-memory-copy to bytecodealliance:main:
Fixes #13959.
Small constant-length copies can generate
i8x16loads and stores even when the target does not support them. On RISC-V without vector support, this causes a compiler panic, including when WebAssembly SIMD is disabled.This checks whether the target supports the vector type before using it in the shared inline-copy helper, falling back to scalar loads and stores otherwise. The RISC-V check uses the configured vector register size and shares the element-type checks with lowering.
Adds a regression test that cross-compiles a 16-byte
memory.copyfor RISC-V with bothhas_vand WebAssembly SIMD disabled.
Wasmtime GitHub notifications bot (Oct 04 2026 at 14:57):dotcom07 requested alexcrichton for a review on PR #14524.
Wasmtime GitHub notifications bot (Oct 04 2026 at 14:57):dotcom07 requested wasmtime-compiler-reviewers for a review on PR #14524.
Wasmtime GitHub notifications bot (Oct 04 2026 at 14:57):dotcom07 requested wasmtime-core-reviewers for a review on PR #14524.
Wasmtime GitHub notifications bot (Oct 04 2026 at 18:14):github-actions[bot] added the label cranelift on PR #14524.
Wasmtime GitHub notifications bot (Oct 04 2026 at 18:14):github-actions[bot] added the label isle on PR #14524.
Wasmtime GitHub notifications bot (Oct 04 2026 at 18:15):github-actions[bot] commented on PR #14524:
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Wasmtime GitHub notifications bot (Oct 04 2026 at 22:58)::memo: alexcrichton submitted PR review.
Wasmtime GitHub notifications bot (Oct 04 2026 at 22:58)::speech_balloon: alexcrichton created PR review comment:
I'm a bit surprised by this implementation -- shouldn't
has_vbe somewhere here as well?
Wasmtime GitHub notifications bot (Oct 05 2026 at 01:58)::memo: dotcom07 submitted PR review.
Wasmtime GitHub notifications bot (Oct 05 2026 at 01:58)::speech_balloon: dotcom07 created PR review comment:
I extracted this helper from the existing element-type checks in
ty_supported().
In #6266, vector lowering was changed to use the register-size check instead of an explicithas_vcheck. As noted in [this discussion], V implies Zvl128b, but not the other way around.Adding a mandatory
has_vcheck to this shared helper would also change existing lowering behavior, rejecting vector types previously accepted with Zvl enabled and V disabled.
Wasmtime GitHub notifications bot (Oct 05 2026 at 02:07)::memo: dotcom07 submitted PR review.
Wasmtime GitHub notifications bot (Oct 05 2026 at 02:07)::speech_balloon: dotcom07 created PR review comment:
One concrete example is a processor implementing Zve32x with Zvl128b: it can support i8x16 loads and stores without implementing the full V extension.
However, the backend does not currently model Zve extensions explicitly, so the register-size check alone does not capture all element-width and instruction restrictions. I'd be interested in exploring explicit Zve support as a separate follow-up.
Wasmtime GitHub notifications bot (Oct 05 2026 at 14:51)::thumbs_up: alexcrichton submitted PR review.
Wasmtime GitHub notifications bot (Oct 05 2026 at 14:52):alexcrichton added PR #14524 cranelift: avoid unsupported vector types in inline copies to the merge queue.
Wasmtime GitHub notifications bot (Oct 05 2026 at 15:29)::check: alexcrichton merged PR #14524.
Wasmtime GitHub notifications bot (Oct 05 2026 at 15:29):alexcrichton removed PR #14524 cranelift: avoid unsupported vector types in inline copies from the merge queue.
Last updated: Oct 11 2026 at 04:10 UTC