Stream: git-wasmtime

Topic: wasmtime / PR #14475 cranelift: Add 128-bit atomics suppo...

Wasmtime GitHub notifications bot (Oct 05 2026 at 13:22):

Gelbpunkt edited PR #14475.

Wasmtime GitHub notifications bot (Oct 05 2026 at 13:22):

Gelbpunkt edited PR #14475:

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This adds support for 128-bit atomics in the atomic_rmw rule, which for 128-bit parameters is now lowered to atomic_rmw_128_loop.

atomic_rmw_128_loop is modeled closely after atomic_rmw_loop, but needs a few extra registers to account for the data taking up two 64-bit GPRs. The generated assembly matches LLVM's.

Wasmtime GitHub notifications bot (Oct 05 2026 at 16:03):

Gelbpunkt updated PR #14475.

Wasmtime GitHub notifications bot (Oct 05 2026 at 16:05):

Gelbpunkt updated PR #14475.

Wasmtime GitHub notifications bot (Oct 05 2026 at 21:57):

Gelbpunkt updated PR #14475.

Wasmtime GitHub notifications bot (Oct 05 2026 at 22:02):

Gelbpunkt updated PR #14475.

Wasmtime GitHub notifications bot (Oct 06 2026 at 08:34):

Gelbpunkt updated PR #14475.

Wasmtime GitHub notifications bot (Oct 06 2026 at 14:47):

Gelbpunkt updated PR #14475.

Wasmtime GitHub notifications bot (Oct 06 2026 at 15:30):

Gelbpunkt updated PR #14475.

Wasmtime GitHub notifications bot (Oct 06 2026 at 16:36):

Gelbpunkt edited PR #14475:

This adds support for 128-bit atomics in the atomic_rmw rule, which for 128-bit parameters is now lowered to atomic_rmw_128_loop.

atomic_rmw_128_loop is modeled closely after atomic_rmw_loop, but needs a few extra registers to account for the data taking up two 64-bit GPRs. The generated assembly matches LLVM's.

A similar thing is done for atomic_cas_128_loop, since we want to be able to support 128-bit atomic compare-and-swap without LSE as well.

Also added are special cased implementations of atomic_load and atomic_store.

See the following Godbolt example for all the assembly generated by LLVM for these cases, which we now match: https://rust.godbolt.org/z/YG6j1z38q

bjorn3 tried this with cg_clif, and it works!

Wasmtime GitHub notifications bot (Oct 06 2026 at 16:37):

Gelbpunkt updated PR #14475.

Wasmtime GitHub notifications bot (Oct 06 2026 at 16:37):

Gelbpunkt has marked PR #14475 as ready for review.

Wasmtime GitHub notifications bot (Oct 06 2026 at 16:37):

Gelbpunkt requested wasmtime-compiler-reviewers for a review on PR #14475.

Wasmtime GitHub notifications bot (Oct 06 2026 at 16:37):

Gelbpunkt requested alexcrichton for a review on PR #14475.

Wasmtime GitHub notifications bot (Oct 06 2026 at 16:37):

Gelbpunkt edited PR #14475:

This adds support for 128-bit atomics in the atomic_rmw rule, which for 128-bit parameters is now lowered to atomic_rmw_128_loop.

atomic_rmw_128_loop is modeled closely after atomic_rmw_loop, but needs a few extra registers to account for the data taking up two 64-bit GPRs. The generated assembly matches LLVM's.

A similar thing is done for atomic_cas_128_loop, since we want to be able to support 128-bit atomic compare-and-swap without LSE as well.

Also added are special cased implementations of atomic_load and atomic_store.

See the following Godbolt example for all the assembly generated by LLVM for these cases, which we now match: https://rust.godbolt.org/z/YG6j1z38q

bjorn3 tried this with cg_clif, and it works!

Closes #10835

Wasmtime GitHub notifications bot (Oct 06 2026 at 16:41):

Gelbpunkt updated PR #14475.

Wasmtime GitHub notifications bot (Oct 06 2026 at 16:45):

Gelbpunkt updated PR #14475.

Wasmtime GitHub notifications bot (Oct 07 2026 at 09:50):

Gelbpunkt edited PR #14475:

This adds support for 128-bit atomics in the atomic_rmw rule, which for 128-bit parameters is now lowered to atomic_rmw_128_loop.

atomic_rmw_128_loop is modeled closely after atomic_rmw_loop, but needs a few extra registers to account for the data taking up two 64-bit GPRs. The generated assembly matches LLVM's.

A similar thing is done for atomic_cas_128_loop, since we want to be able to support 128-bit atomic compare-and-swap without LSE as well.

Also added are special cased implementations of atomic_load and atomic_store.

See the following Godbolt example for all the assembly generated by LLVM for these cases, which we now match: https://rust.godbolt.org/z/YG6j1z38q

bjorn3 tried this with cg_clif, and it works! In rust-lang/rust we currently keep a patch around for cg_clif to remove 128-bit atomic support, which is very painful to maintain, see https://github.com/rust-lang/rust/issues/153488. Out of x86_64, aarch64, riscv64 and s390x, the Rust targets that have 128-bit atomic support enabled are x86_64 on Darwin and Windows, aarch64 and s390x. Out of those, Cranelift currently lacks support for them on aarch64 and s390x.

Closes #10835

Wasmtime GitHub notifications bot (Oct 07 2026 at 15:40):

alexcrichton commented on PR #14475:

cc @theotherjimmy if you wouldn't mind reviewing this it'd be much appreciated!

Wasmtime GitHub notifications bot (Oct 07 2026 at 16:22):

:repeat: theotherjimmy submitted PR review:

Minor nits. Aside from some unused labels, this looks good.

Wasmtime GitHub notifications bot (Oct 07 2026 at 16:22):

:speech_balloon: theotherjimmy created PR review comment:

Unless I'm mistaken, this should work too:

cmp x27, x26
b.ne swap
cmp x21, x23
b.ne swap

With the bonus that it's shorter.

This is also the only place I saw cinc and csinc used, so that could be moved out of this PR too.

Note: this is not required, only nice to have.

Wasmtime GitHub notifications bot (Oct 07 2026 at 16:22):

:speech_balloon: theotherjimmy created PR review comment:

Out label appears to be unused. Can this be removed?

Wasmtime GitHub notifications bot (Oct 07 2026 at 16:22):

:speech_balloon: theotherjimmy created PR review comment:

This out label also seems unused.

Wasmtime GitHub notifications bot (Oct 07 2026 at 17:38):

:memo: Gelbpunkt submitted PR review.

Wasmtime GitHub notifications bot (Oct 07 2026 at 17:38):

:speech_balloon: Gelbpunkt created PR review comment:

Indeed, that should also work, but would deviate from LLVM. I presume LLVM tries to avoid branches as much as possible, but I'll use your suggestion and remove cinc/csinc, I think I prefer a smaller diff here

Wasmtime GitHub notifications bot (Oct 07 2026 at 18:09):

Gelbpunkt updated PR #14475.

Wasmtime GitHub notifications bot (Oct 07 2026 at 18:10):

:memo: Gelbpunkt submitted PR review.

Wasmtime GitHub notifications bot (Oct 07 2026 at 18:10):

:speech_balloon: Gelbpunkt created PR review comment:

(Since we don't want to swap when they're not equal, we branch to the keep case and therefore I switched the swap and keep cases around, but it works as intended now without cinc/csinc)

Wasmtime GitHub notifications bot (Oct 07 2026 at 18:10):

:memo: Gelbpunkt submitted PR review.

Wasmtime GitHub notifications bot (Oct 07 2026 at 18:10):

:speech_balloon: Gelbpunkt created PR review comment:

Done

Wasmtime GitHub notifications bot (Oct 07 2026 at 18:10):

:memo: Gelbpunkt submitted PR review.

Wasmtime GitHub notifications bot (Oct 07 2026 at 18:10):

:speech_balloon: Gelbpunkt created PR review comment:

Thanks, removed!

Wasmtime GitHub notifications bot (Oct 07 2026 at 18:15):

Gelbpunkt updated PR #14475.

Wasmtime GitHub notifications bot (Oct 07 2026 at 18:26):

:memo: theotherjimmy submitted PR review.

Wasmtime GitHub notifications bot (Oct 07 2026 at 18:26):

:speech_balloon: theotherjimmy created PR review comment:

Ah, good point. My bad.

Wasmtime GitHub notifications bot (Oct 07 2026 at 18:30):

:thumbs_up: theotherjimmy submitted PR review:

Looks good now.

Wasmtime GitHub notifications bot (Oct 07 2026 at 18:37):

:thumbs_up: alexcrichton submitted PR review:

(carrying over @theotherjimmy's approval)

Wasmtime GitHub notifications bot (Oct 07 2026 at 18:37):

alexcrichton added PR #14475 cranelift: Add 128-bit atomics support for AArch64 to the merge queue.

Wasmtime GitHub notifications bot (Oct 07 2026 at 18:46):

Gelbpunkt commented on PR #14475:

Hm, inst_size_test for aarch64 is failing on i686, I presume I could just #[cfg(target_pointer_width = "64")] it like on x64?

Wasmtime GitHub notifications bot (Oct 07 2026 at 19:02):

github-merge-queue[bot] removed PR #14475 cranelift: Add 128-bit atomics support for AArch64 from the merge queue.

Wasmtime GitHub notifications bot (Oct 07 2026 at 19:08):

Gelbpunkt updated PR #14475.

Wasmtime GitHub notifications bot (Oct 07 2026 at 21:48):

:thumbs_up: alexcrichton submitted PR review.

Wasmtime GitHub notifications bot (Oct 07 2026 at 21:48):

alexcrichton added PR #14475 cranelift: Add 128-bit atomics support for AArch64 to the merge queue.

Wasmtime GitHub notifications bot (Oct 07 2026 at 22:10):

github-merge-queue[bot] removed PR #14475 cranelift: Add 128-bit atomics support for AArch64 from the merge queue.

Wasmtime GitHub notifications bot (Oct 07 2026 at 22:34):

alexcrichton commented on PR #14475:

ah just an unused import on 32-bit now

Wasmtime GitHub notifications bot (Oct 08 2026 at 08:59):

Gelbpunkt updated PR #14475.

Wasmtime GitHub notifications bot (Oct 08 2026 at 09:00):

Gelbpunkt commented on PR #14475:

Right, that should be resolved now

Wasmtime GitHub notifications bot (Oct 08 2026 at 18:21):

:thumbs_up: theotherjimmy submitted PR review.

Wasmtime GitHub notifications bot (Oct 08 2026 at 20:22):

alexcrichton added PR #14475 cranelift: Add 128-bit atomics support for AArch64 to the merge queue.

Wasmtime GitHub notifications bot (Oct 08 2026 at 20:46):

:check: alexcrichton merged PR #14475.

Wasmtime GitHub notifications bot (Oct 08 2026 at 20:46):

alexcrichton removed PR #14475 cranelift: Add 128-bit atomics support for AArch64 from the merge queue.

Wasmtime GitHub notifications bot (Oct 08 2026 at 20:48):

Gelbpunkt commented on PR #14475:

Thanks for the review and quick merge! Hope I'll get around to s390x next week

Last updated: Oct 11 2026 at 04:10 UTC