dsecurity49 opened PR #14285 from dsecurity49:fix-aarch64-vhigh-bits-float-vectors to bytecodealliance:main:
Resolves missing ISLE rules from #12197 on AArch64, x86_64, and RISC-V.
AArch64:
- vhigh_bits: Switched vhigh_bits rules from $I* to multi_lane to support float vector types (f32x4, f64x2, f16x8), matching x64 and s390x.
- band + bnot: Added lowering rules for band(bnot) on scalar floats (f32, f64) to emit a single bic instruction instead of separate mvn + and.
x86_64:
- bitcast_gpr_to_xmm: Added 8-bit byte rule to fix compiler panic in scalar_to_vector.i8x16 / vany_true.i8x16 (using PINSRB on SSE4.1, and MOVZBL + PINSRW on baseline SSE2).
RISC-V:
- select_spectre_guard: Added lowering rule for vector types (ty_supported_vec) using vand.vx, vandn.vx, and vor.vv.
Includes precise-output filetests for all three architectures and enables aarch64 in runtests/simd-vhighbits-float.clif.
dsecurity49 requested cfallin for a review on PR #14285.
dsecurity49 requested wasmtime-compiler-reviewers for a review on PR #14285.
github-actions[bot] added the label cranelift on PR #14285.
github-actions[bot] added the label cranelift:area:aarch64 on PR #14285.
github-actions[bot] added the label cranelift:area:x64 on PR #14285.
:thumbs_up: cfallin submitted PR review:
Thanks!
cfallin added PR #14285 cranelift: fix missing ISLE lowering rules from #12197 on AArch64, x86_64, and RISC-V to the merge queue.
:check: cfallin merged PR #14285.
cfallin removed PR #14285 cranelift: fix missing ISLE lowering rules from #12197 on AArch64, x86_64, and RISC-V from the merge queue.
Last updated: Sep 20 2026 at 18:08 UTC