Wasmtime GitHub notifications bot (Jul 21 2026 at 01:43): Wasmtime GitHub notifications bot (Jul 21 2026 at 01:43):jlb6740 opened PR #13916 from jlb6740:apx-add-ndd to bytecodealliance:main:
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Wasmtime GitHub notifications bot (Jul 21 2026 at 03:52):github-actions[bot] added the label cranelift on PR #13916.
Wasmtime GitHub notifications bot (Jul 21 2026 at 03:52):github-actions[bot] added the label cranelift:area:x64 on PR #13916.
Wasmtime GitHub notifications bot (Jul 21 2026 at 03:52):github-actions[bot] added the label cranelift:meta on PR #13916.
Wasmtime GitHub notifications bot (Jul 21 2026 at 03:52):github-actions[bot] added the label isle on PR #13916.
Wasmtime GitHub notifications bot (Jul 21 2026 at 03:52):github-actions[bot] commented on PR #13916:
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Wasmtime GitHub notifications bot (Aug 21 2026 at 23:12):jlb6740 updated PR #13916.
Wasmtime GitHub notifications bot (Aug 21 2026 at 23:34):jlb6740 updated PR #13916.
Wasmtime GitHub notifications bot (Aug 22 2026 at 00:53):jlb6740 updated PR #13916.
Wasmtime GitHub notifications bot (Aug 22 2026 at 00:59):jlb6740 updated PR #13916.
Wasmtime GitHub notifications bot (Aug 22 2026 at 01:00):jlb6740 updated PR #13916.
Wasmtime GitHub notifications bot (Aug 22 2026 at 01:15):jlb6740 edited PR #13916:
Adds the APX NDD (new data destination) form of 64-bit
add, as an initial
end-to-end slice through the stack: DSL entry, extended-EVEX (map 4) encoding,
an ISLE lowering rule gated onhas_apx, and a filetest.This is deliberately one instruction rather than a batch to make sure of the generic
mechanisms definining APX, not necessarilyaddqitself:
Operand order is derived from the EVEX
NDbit, since withND = 1the
destination lives invvvvand prints last in AT&T order. Keying off the bit
rather than the operand shape means future NDD instructions get this for free.
disp8scaling is disabled forApxClass::LegacyGpr. Map-4 instructions are
promoted legacy instructions and keep plain byte displacements rather than
EVEX compressed displacement.Two things:
APX is test-only right now. Nothing enables
has_apxautomatically, because
is_x86_feature_detected!("apxf")is still unstable (rust-lang/rust#139284).
Detection can follow once that lands.The NDD rule sits below the load-sinking rules, so the memory-operand form
isn't selected yet. It's covered by an assembler unit test instead.Still a draft: it's stacked on #14136, so that commit currently shows up in the
diff here. I'll rebase and mark this ready once #14136 merges.
Wasmtime GitHub notifications bot (Aug 22 2026 at 03:56):github-actions[bot] added the label cranelift:area:machinst on PR #13916.
Wasmtime GitHub notifications bot (Aug 25 2026 at 00:57):jlb6740 has marked PR #13916 as ready for review.
Wasmtime GitHub notifications bot (Aug 25 2026 at 00:57):jlb6740 requested cfallin for a review on PR #13916.
Wasmtime GitHub notifications bot (Aug 25 2026 at 00:57):jlb6740 requested wasmtime-compiler-reviewers for a review on PR #13916.
Wasmtime GitHub notifications bot (Aug 25 2026 at 00:58):jlb6740 converted PR #13916 Apx add ndd to a draft.
Wasmtime GitHub notifications bot (Aug 25 2026 at 17:47):jlb6740 updated PR #13916.
Wasmtime GitHub notifications bot (Aug 25 2026 at 17:48):jlb6740 has marked PR #13916 as ready for review.
Wasmtime GitHub notifications bot (Aug 26 2026 at 16:53):jlb6740 edited PR #13916:
Adds the APX NDD (new data destination) form of 64-bit
add, as an initial
end-to-end slice through the stack: DSL entry, extended-EVEX (map 4) encoding,
an ISLE lowering rule gated onhas_apx, and a filetest.This is deliberately one instruction rather than a batch to make sure of the generic
mechanisms definining APX, not necessarilyaddqitself:
Operand order is derived from the EVEX
NDbit, since withND = 1the
destination lives invvvvand prints last in AT&T order. Keying off the bit
rather than the operand shape means future NDD instructions get this for free.
disp8scaling is disabled forApxClass::LegacyGpr. Map-4 instructions are
promoted legacy instructions and keep plain byte displacements rather than
EVEX compressed displacement.Two things:
APX is test-only right now. Nothing enables
has_apxautomatically, because
is_x86_feature_detected!("apxf")is still unstable (rust-lang/rust#139284).
Detection can follow once that lands.The NDD rule sits below the load-sinking rules, so the memory-operand form
isn't selected yet. It's covered by an assembler unit test instead.~~Still a draft: it's stacked on #14136, so that commit currently shows up in the
diff here. I'll rebase and mark this ready once #14136 merges.~~
Wasmtime GitHub notifications bot (Aug 28 2026 at 17:47)::thumbs_up: cfallin submitted PR review:
Thanks @jlb6740 for seeing this through -- looks fine as far as I understand things (I by no means claim to be an expert in x86-64 instruction encoding, but I'll trust the XED-based fuzzing).
One trivial request: could you change the title of this PR to something more descriptive than "apx add ndd"? I'm happy to merge once that's done. Thanks!
Last updated: Aug 30 2026 at 09:07 UTC