Stream: git-wasmtime

Topic: wasmtime / PR #13766 cranelift(aarch64): share base+index...


view this post on Zulip Wasmtime GitHub notifications bot (Jun 30 2026 at 08:04):

darmie opened PR #13766 from darmie:aarch64-amode-shared-base-cse to bytecodealliance:main:

When several loads share base + (extended index) and differ only by a
uimm12-scaled offset (e.g. fields read through a computed index), AArch64 amode
selection emitted a separate add base, #offset per load, defeating CSE of the
shared base + index.

This folds the offset into the load's immediate and keeps base + index as one
value, so a single add base, index, uxtw is materialized and reused. A zero
offset keeps the single-instruction RegExtended form, so it is
neutral-or-better: a cluster of N such loads drops N address-adds to 1, a lone
load is unchanged.

Tested: new aarch64 precise-output filetest + a stack round-trip runtest
(aarch64/x86_64/s390x); the full aarch64 filetest and runtest suites pass.

view this post on Zulip Wasmtime GitHub notifications bot (Jun 30 2026 at 08:04):

darmie requested alexcrichton for a review on PR #13766.

view this post on Zulip Wasmtime GitHub notifications bot (Jun 30 2026 at 08:04):

darmie requested wasmtime-compiler-reviewers for a review on PR #13766.

view this post on Zulip Wasmtime GitHub notifications bot (Jun 30 2026 at 08:25):

darmie requested wasmtime-core-reviewers for a review on PR #13766.

view this post on Zulip Wasmtime GitHub notifications bot (Jun 30 2026 at 08:25):

darmie updated PR #13766.

view this post on Zulip Wasmtime GitHub notifications bot (Jun 30 2026 at 11:36):

github-actions[bot] added the label cranelift on PR #13766.

view this post on Zulip Wasmtime GitHub notifications bot (Jun 30 2026 at 11:36):

github-actions[bot] added the label cranelift:area:aarch64 on PR #13766.

view this post on Zulip Wasmtime GitHub notifications bot (Jun 30 2026 at 17:40):

alexcrichton commented on PR #13766:

Thanks for this! I'm wary of the duplication being added here though, and amode rules are some of the most sensitive in Cranelift so we ideally want as little duplication as possible. For example the offset=0 rules are duplicates of above rules, and even using AMode.UnsignedOffset is a duplicate of prior rules as well. Would it be possible to shuffle rules around and add if-let clauses perhaps to tweak existing rules? For example rules could use if-let or some sort of extraction matcher to ensure that offset is 0. Either that or the rule using AMode.UnsignedOffset could be given higher priority.

view this post on Zulip Wasmtime GitHub notifications bot (Jul 01 2026 at 06:47):

darmie updated PR #13766.

view this post on Zulip Wasmtime GitHub notifications bot (Jul 01 2026 at 06:49):

darmie commented on PR #13766:

For example the offset=0 rules are duplicates of above rules, and even using AMode.UnsignedOffset is a duplicate of prior rules as well. Would it be possible to shuffle rules around and add if-let clauses perhaps to tweak existing rules? For example rules could use if-let or some sort of extraction matcher to ensure that offset is 0. Either that or the rule using AMode.UnsignedOffset could be given higher priority.

I have removed the duplication. Also added uimm12_scaled_nonzero_from_i64 (+ its verifier spec) so rules 8/9's UnsignedOffset only matches non-zero offsets and takes higher priority than 4/5; a zero offset falls through to the existing RegExtended rules naturally.

view this post on Zulip Wasmtime GitHub notifications bot (Jul 01 2026 at 10:02):

github-actions[bot] added the label isle on PR #13766.

view this post on Zulip Wasmtime GitHub notifications bot (Jul 01 2026 at 10:02):

github-actions[bot] commented on PR #13766:

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view this post on Zulip Wasmtime GitHub notifications bot (Jul 01 2026 at 14:56):

alexcrichton commented on PR #13766:

This helps remove some duplication, yeah, but this is still effectively a duplication of rule (2), however, and it's also a duplication of 3/4/5 in terms of matching pattern. My thinking is that what you want can be achieved by raising the priority of rule 2 because the premise here is that the static offset should have the highest priority for getting folded into the instruction itself while leaving all other computations in a CSE-able form.

view this post on Zulip Wasmtime GitHub notifications bot (Jul 24 2026 at 08:17):

darmie updated PR #13766.

view this post on Zulip Wasmtime GitHub notifications bot (Jul 24 2026 at 08:17):

darmie commented on PR #13766:

This helps remove some duplication, yeah, but this is still effectively a duplication of rule (2), however, and it's also a duplication of 3/4/5 in terms of matching pattern. My thinking is that what you want can be achieved by raising the priority of rule 2 because the premise here is that the static offset should have the highest priority for getting folded into the instruction itself while leaving all other computations in a CSE-able form.

It's done! I have replaced the four rules with a single generic highest-priority UnsignedOffset rule (non-zero uimm12), so it's rule 2's action raised in priority with no pattern duplication. Zero offsets fall through to the reg-folding rules. It also now folds plain-iadd/scaled cases, dropping an instruction in one amodes.clif function.

view this post on Zulip Wasmtime GitHub notifications bot (Jul 24 2026 at 08:28):

darmie updated PR #13766.

view this post on Zulip Wasmtime GitHub notifications bot (Jul 24 2026 at 23:54):

:thumbs_up: alexcrichton submitted PR review.

view this post on Zulip Wasmtime GitHub notifications bot (Jul 24 2026 at 23:54):

alexcrichton added PR #13766 cranelift(aarch64): share base+index across offset loads via uimm12 amode to the merge queue.

view this post on Zulip Wasmtime GitHub notifications bot (Jul 25 2026 at 00:19):

:check: alexcrichton merged PR #13766.

view this post on Zulip Wasmtime GitHub notifications bot (Jul 25 2026 at 00:19):

alexcrichton removed PR #13766 cranelift(aarch64): share base+index across offset loads via uimm12 amode from the merge queue.


Last updated: Jul 29 2026 at 05:03 UTC