darmie opened PR #13717 from darmie:aarch64-addv-hsum to bytecodealliance:main:
A complete
i32x4horizontal-add reduction has no CLIF opcode, so it is
expressed as twoiadd_pairwisees (which GVN shares) followed by a lane-0
extractlane. Currently that lowers to:addp v.4s, v.4s, v.4s addp v.4s, v.4s, v.4s umov w0, v.s[0]NEON
addvreduces the whole vector in a single instruction, so this contracts
the tree to:addv s0, v.4s umov w0, v.s[0]— one fewer instruction and, more importantly, no serial
addpdependency chain.The mid-end has no egraph rules touching
iadd_pairwise, so the structured
reduction reaches isel intact, which keeps the match reliable (a plainiadd
tree would be reassociated).Follow-up
The cleaner long-term fix is a dedicated horizontal-reduce CLIF op (e.g.
vreduce_iadd) that completes thevall_true/vany_true/vhigh_bits
vector→scalar family and lowers toaddvon aarch64 with portable fallbacks
elsewhere. Happy to do that as a follow-up if you'd prefer the IR-level
primitive; this is a minimal aarch64-only implementation for now.Tests
filetests/isa/aarch64/simd-addv-reduce.clif— precise-output, assertsaddv; umov.filetests/runtests/simd-addv-reduce.clif—interpret+runsemantics on aarch64/x86_64/s390x.- The existing
isa/aarch64andruntestssuites pass unchanged.
darmie requested cfallin for a review on PR #13717.
darmie requested wasmtime-compiler-reviewers for a review on PR #13717.
:thumbs_up: cfallin submitted PR review:
Thanks -- this looks good!
FWIW, we've talked about the tradeoff of putting more domain-specific opcodes into CLIF vs. using simpler ops and pattern-matching, as we do here; in general the direction has been to keep CLIF simpler ("RISC-like") now that we have a fairly robust pattern-matching language in the backend. We can of course always reconsider that if something specific is really difficult but for now this seems fine.
cfallin added PR #13717 cranelift(aarch64): fold an i32x4 horizontal add into a single addv to the merge queue.
:check: cfallin merged PR #13717.
cfallin removed PR #13717 cranelift(aarch64): fold an i32x4 horizontal add into a single addv from the merge queue.
Last updated: Jul 29 2026 at 05:03 UTC