Stream: git-wasmtime

Topic: wasmtime / PR #12218 s390x: Emit 20bit immedate variants ...

Wasmtime GitHub notifications bot (Dec 24 2025 at 15:30):

theotherjimmy opened PR #12218 from theotherjimmy:s390x-bxd20 to bytecodealliance:main:

Previously, cranelift did not emit memory operations using 20 bit immedates for reg + reg memory modes on s390x. This patch enables that in a type safe manner by exporting a few extractors for 20 bit immediates and changing the argument to the MemArg constructor for reg + reg addressing mode to accept that 20 bit offset instead of the u8 offset.

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Wasmtime GitHub notifications bot (Dec 24 2025 at 15:30):

theotherjimmy requested abrown for a review on PR #12218.

Wasmtime GitHub notifications bot (Dec 24 2025 at 15:30):

theotherjimmy requested wasmtime-compiler-reviewers for a review on PR #12218.

Wasmtime GitHub notifications bot (Dec 24 2025 at 15:32):

theotherjimmy updated PR #12218.

Wasmtime GitHub notifications bot (Dec 24 2025 at 15:52):

theotherjimmy updated PR #12218.

Wasmtime GitHub notifications bot (Dec 24 2025 at 17:45):

github-actions[bot] commented on PR #12218:

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cc @cfallin, @fitzgen

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Wasmtime GitHub notifications bot (Dec 27 2025 at 04:05):

cfallin commented on PR #12218:

cc @uweigand -- would you mind taking a look?

Wasmtime GitHub notifications bot (Jan 07 2026 at 16:33):

uweigand commented on PR #12218:

Hi @theotherjimmy this makes sense in principle, but I have a couple of comments:

• The bias naming was intended to reflect small offset generated by the back-end to access part of a value (e.g. when accessing a 16-byte value as two 8-byte values, the second value needs to have the address biased by 8); it was not intended to act as a generic displacement. If we want that, we should probably rename the function to reg_plus_reg_plus_off or something.
• With your code, we're now greedily generating reg+reg+simm20 always, and retroactively fix things if the instruction doesn't have that addressing mode. That is probably the right thing to do in general, but in many cases we already know that the addressing mode isn't available (e.g. vector instructions always only have uimm12 displacements). We'll likely get better code if we leave the addition separately from the beginning in those cases.
  

Wasmtime GitHub notifications bot (Jan 07 2026 at 18:14):

theotherjimmy commented on PR #12218:

Thanks for the review @uweigand

I think I'll rework this to write a new extractor with your suggested name, and migrate to that new extractor where we know the instructions support the extended offset. That should resolve your concerns.

Last updated: Jan 09 2026 at 13:15 UTC