alexcrichton opened PR #11128 from alexcrichton:x64-bt to bytecodealliance:main:
This commit builds on the previous refactorings to leverage the
btinstruction on x64 which moves a specific bit into the CF bit of EFLAGS which can be useful for comparisons/branches/selects/etc.<!--
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alexcrichton requested wasmtime-compiler-reviewers for a review on PR #11128.
alexcrichton requested wasmtime-core-reviewers for a review on PR #11128.
alexcrichton requested fitzgen for a review on PR #11128.
fitzgen submitted PR review.
fitzgen created PR review comment:
Do we expect this to use a
btinstruction? If not, then why not?
fitzgen created PR review comment:
Slightly easier to understand, for me at least, like this:
if val.count_ones() == 1 { Some(u8::try_from(val.trailing_zeros()).unwrap()) } else { None }
fitzgen created PR review comment:
Same here?
alexcrichton updated PR #11128.
github-actions[bot] commented on PR #11128:
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alexcrichton submitted PR review.
alexcrichton created PR review comment:
It's intentional yeah, and corresponds to this lowering rule. My rationale is "LLVM is probably smarter than I" and I'm assuming LLVM did things like micro-op tests or something to figure out that
testhas a lower latency thanbtor something like that. No idea if that's actually the case though, just mirroring them.
cfallin submitted PR review.
cfallin created PR review comment:
According to Agner Fog's tables, taking Skylake as a random reasonable baseline µarch,
testhas one cycle latency and a throughput of 4/cycle (four ALU ports can execute it) whilebthas one cycle latency and a throughput of 2/cycle (two ALU ports can execute it). So probably reasonable to prefertesttobtwhere possible.
alexcrichton submitted PR review.
alexcrichton created PR review comment:
Nice that sounds like an excellent reference to put as documentation in the lowering rules so I'll do that.
alexcrichton updated PR #11128.
fitzgen submitted PR review:
Thanks!
fitzgen merged PR #11128.
Last updated: Dec 06 2025 at 06:05 UTC