abrown opened PR #11115 from abrown:asm-xmm-rmir-vex to bytecodealliance:main:
This migration of AVX instructions to use the new assembler is intended to be a large but quite mechanical conversion of all instructions that fit within the
Inst::XmmRmiRVexvariant. Unfortunately, three unimplemented SSE instructions (vpmaddwd,vpmaddubsw,vpshufb) prevent us from fully removingInst::XmmRmiRVexand its ISLE helper,xmm_rmir_vex; we can remove those later once the SSE versions are implemented.Beyond small format-related changes in Cranelift to accept the new VEX shapes, the largest change comes in Winch: because of how
AvxOpcodewas passed around previously, I was forced to create new constructors and refactor various bits. I resisted the temptation to go too far, but I could not resist making some of these constructors more consistent, e.g., using common suffixes (rrr,rri) and moving like instructions closer to each other.
abrown requested alexcrichton for a review on PR #11115.
abrown requested wasmtime-compiler-reviewers for a review on PR #11115.
abrown requested wasmtime-core-reviewers for a review on PR #11115.
abrown updated PR #11115.
alexcrichton created PR review comment:
This looks peculiar! This indicates that we might be placing an unnecessary byte which isn't required? Or that the old encoding for these instructions was 1-byte smaller than the encoding from the assembler?
(or maybe a rebase conflict as one of the PRs I landed recently removed some bytes and this might be adding them back in without having rebased on that? unsure)
alexcrichton created PR review comment:
To confirm, changing opcodes here is intentional?
alexcrichton created PR review comment:
This (and a few below) regressed away from
v*
alexcrichton submitted PR review.
alexcrichton created PR review comment:
Should this (and various others around here) be using
*_or_avx?
alexcrichton created PR review comment:
Accidental regression from
vpsrlqtopsrlqI think
abrown created PR review comment:
It's a "generate all 1s" situation so I just changed it to the lowest lane version, but I'll change it back.
abrown submitted PR review.
abrown updated PR #11115.
abrown updated PR #11115.
abrown submitted PR review.
abrown created PR review comment:
(referenced above)
abrown submitted PR review.
abrown created PR review comment:
Ok, looking at this again, I think we should just accept this (like you were pointing out when we talked). This is coming because this PR switched the order of the operands as it lowered the instruction and I think this operand swap makes more sense. Take a look at the constructor I tagged below: we pass
src1andsrc2in the order one would expect. I'm just going to leave this.
abrown updated PR #11115.
abrown merged PR #11115.
Last updated: Dec 06 2025 at 06:05 UTC