Stream: git-wasmtime

Topic: wasmtime / PR #10975 x64: Migrate some blend-related inst...

Wasmtime GitHub notifications bot (Jun 07 2025 at 01:43):

alexcrichton opened PR #10975 from alexcrichton:x64-blends to bytecodealliance:main:

This commit migrates the pblendvb, blendvps, blendvpd, and AVX versions of each to the new assembler. This required a few minor features in the assembler:

• The fixed physical xmm0 register is now a Location
• The "/is4" encoding format for VEX instructions is supported
• The Fixed type now supports both xmm and gpr registers (minor update to its to_string method).

In the end this enables deleting XmmRmRBlend and XmmRmRBlendVex. (yay!)

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Wasmtime GitHub notifications bot (Jun 07 2025 at 01:43):

alexcrichton requested cfallin for a review on PR #10975.

Wasmtime GitHub notifications bot (Jun 07 2025 at 01:43):

alexcrichton requested wasmtime-compiler-reviewers for a review on PR #10975.

Wasmtime GitHub notifications bot (Jun 07 2025 at 01:45):

alexcrichton submitted PR review.

Wasmtime GitHub notifications bot (Jun 07 2025 at 01:45):

alexcrichton created PR review comment:

I'll note that there's no actual register allocation changes here, this is just an artifact of how the instruction used to be printed. The xmm0 argument was omitted by default and the src/destination, which are required to be the same register, were printed twice.

Wasmtime GitHub notifications bot (Jun 07 2025 at 02:13):

alexcrichton updated PR #10975.

Wasmtime GitHub notifications bot (Jun 07 2025 at 02:13):

alexcrichton updated PR #10975.

Wasmtime GitHub notifications bot (Jun 09 2025 at 17:32):

abrown submitted PR review.

Wasmtime GitHub notifications bot (Jun 09 2025 at 17:32):

abrown created PR review comment:

        inst("pblendvb", fmt("RM", [rw(xmm1), r(align(xmm_m128)), r(implicit(xmm0))]), rex([0x66, 0x0F, 0x38, 0x10]).r(), _64b | compat | sse41),

Don't we want this to be implicit?

Wasmtime GitHub notifications bot (Jun 09 2025 at 17:39):

alexcrichton submitted PR review.

Wasmtime GitHub notifications bot (Jun 09 2025 at 17:39):

alexcrichton created PR review comment:

I originally thought so yeah but apparently Capstone disassembles this with %xmm0 show it shows up in the instruction listing. It looks like even Intel-style disassembly shows xmm0 as well, so for whatever reason while it's implicit on instructions like div it's not implicit here...

Wasmtime GitHub notifications bot (Jun 09 2025 at 18:06):

abrown submitted PR review.

Wasmtime GitHub notifications bot (Jun 09 2025 at 18:28):

abrown merged PR #10975.

Last updated: Dec 06 2025 at 06:05 UTC