jlb6740 opened PR #10856 from jlb6740:add-rounding-to-new-assembler to bytecodealliance:main:
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jlb6740 requested cfallin for a review on PR #10856.
jlb6740 requested wasmtime-compiler-reviewers for a review on PR #10856.
jlb6740 commented on PR #10856:
Will add vround variants in a follow-up to this patch.
jlb6740 commented on PR #10856:
Only touches the assembler part.
jlb6740 deleted a comment on PR #10856:
Only touches the assembler part.
jlb6740 edited a comment on PR #10856:
Will add vround variants in a follow-up to this patch. Also, this only touches the assembler and does not connect isle.
jlb6740 updated PR #10856.
jlb6740 edited a comment on PR #10856:
This only touches the assembler and does not connect isle.
jlb6740 updated PR #10856.
jlb6740 updated PR #10856.
jlb6740 updated PR #10856.
jlb6740 updated PR #10856.
abrown submitted PR review.
alexcrichton submitted PR review.
alexcrichton created PR review comment:
Should these be
align(xmm_m128)?(should we maybe have a check in the DSL that non-avx
xmm_m128arguments are required to bealign?)
jlb6740 submitted PR review.
jlb6740 created PR review comment:
I read this comment multiple times trying to interpret:
"NB: the non-AVX variant of this instruction does not require that the operand
;; is aligned, but the instruction variant used here requires it to be aligned."Perhaps I should have asked. So the non-AVX variant here does require alignment?
jlb6740 edited PR review comment.
alexcrichton created PR review comment:
Ah yeah I believe that comment is referring to
rounds{s,d}, as opposed toroundp{s,d}. I'm under the impression that the f32/f64 versions do not require aligned memory but the 128-bit versions require aligned memory. The comment in ISLE I believe can be deleted with the new instructions since it's correctly modeled.This reminds me as well, should
rounds{s,d}below usexmm_m{32,64}instead ofxmm_m128? We don't have anything actually checking that right now but with PCC in the future (or some other integration) it might matter to annotate that with the appropriate bit-width.
alexcrichton submitted PR review.
jlb6740 updated PR #10856.
jlb6740 edited PR review comment.
jlb6740 edited PR review comment.
abrown merged PR #10856.
jlb6740 submitted PR review.
jlb6740 created PR review comment:
@alexcrichton Yes you are right on the rounds{s,d}. I am not sure how this would come in to play but let me update this to the correct annotation and also maybe remove that comment.
jlb6740 edited PR review comment.
alexcrichton created PR review comment:
Oh sorry fully reading your comment I can also clarify more:
The documentation there referred to the ISLE-specific abstraction of
XmmUnaryRmRImmwhich internally storesXmmMemAligned. Theroundssandroundsdinstructions usedXmmUnaryRmRImmbut this was technically not a correct way to model these instructions. Theroundssandroundsdinstructions do not actually require alignment. The problem, and where the comment comes from, is that the way this happens in ISLE is that first aValueis converted toXmmMemas the load is "sinkable". Next it goes to thex64_roundhelper which takesXmmMem. Next, without AVX, it would go toXmmUnaryRmRImm, but this required converting theXmmMemtoXmmMemAligned. That, for all WebAssembly loads/stores, would automatically do an unaligned load and then use a register operand. The problem with this is that the automatic load inserted would load 128-bits, not the appropriate number of bits for the f32/f64.So basically that long comment was an artifact of a precisely how ISLE is set up today. None of it is applicable under the new assembler, and I think that the
roundpsandroundpdinstructions needalign(xmm_m128)butroundssandroundsdcan usexmm_m32andxmm_m64since they don't require alignment.Also FWIW I see a new commit here but I don't believe it landed because it was pushed after this was already in the merge queue, so mind filing a follow-up commit with that?
alexcrichton submitted PR review.
Last updated: Dec 06 2025 at 07:03 UTC