rahulchaphalkar opened PR #10855 from rahulchaphalkar:div-instructions to bytecodealliance:main:
Converts div instructions to new assembler. Remove old div impl from codegen for SSE variants, not Vex variants.
rahulchaphalkar requested abrown for a review on PR #10855.
rahulchaphalkar requested wasmtime-compiler-reviewers for a review on PR #10855.
alexcrichton created PR review comment:
I think these should be
align(xmm_m128)?
alexcrichton submitted PR review.
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rahulchaphalkar updated PR #10855.
rahulchaphalkar submitted PR review.
rahulchaphalkar created PR review comment:
Done
rahulchaphalkar commented on PR #10855:
Seem to be unrelated connection errors in CI like -
Err:16 http://archive.ubuntu.com/ubuntu xenial/main amd64 libmpc3 amd64 1.0.3-1 #6 823.0 Could not connect to archive.ubuntu.com:80 (91.189.91.81), connection timed out [IP: 91.189.91.81 80]
rahulchaphalkar edited a comment on PR #10855:
Seem to be unrelated connection errors in CI like -
Err:16 http://archive.ubuntu.com/ubuntu xenial/main amd64 libmpc3 amd64 1.0.3-1 #6 823.0 Could not connect to archive.ubuntu.com:80 (91.189.91.81), connection timed out [IP: 91.189.91.81 80]Edit - They went away, now passes all tests
rahulchaphalkar commented on PR #10855:
@alexcrichton is this good to go?
alexcrichton submitted PR review:
Oh oops, my bad!
abrown submitted PR review:
This is good to go; can you update the few locations I pointed out before I merge?
abrown created PR review comment:
Just looking at the manual and, though this all will boil down to the same thing, I think we should be more pedantic and write:
inst("vdivss", fmt("B", [rw(xmm1), r(xmm2), r(xmm_m32)]), vex(LIG)._f3()._0f().wig().op(0x5E).r(), _64b | compat | avx), inst("vdivsd", fmt("B", [rw(xmm1), r(xmm2), r(xmm_m64)]), vex(LIG)._f2()._0f().wig().op(0x5E).r(), _64b | compat | avx),(And this probably means other VEX instructions should get checked but we don't have to do that in this PR).
abrown created PR review comment:
inst("vdivps", fmt("B", [rw(xmm1), r(xmm2), r(xmm_m128)]), vex(L128)._0f().wig().op(0x5E).r(), _64b | compat | avx), inst("vdivpd", fmt("B", [rw(xmm1), r(xmm2), r(xmm_m128)]), vex(L128)._66().wig()._0f().op(0x5E).r(), _64b | compat | avx),
abrown created PR review comment:
A nit to add the rule priority and, in these very short cases, fit it on a single line:
(rule 0 (x64_divsd src1 src2) x64_divsd_a src1 src2))
abrown created PR review comment:
More nits:
use crate::dsl::{Feature::*, Inst, Location::*, VexLength::*}; use crate::dsl::{align, fmt, implicit, inst, r, rex, rw, vex};
abrown submitted PR review:
This looks almost good to go; can you update the few locations I pointed out before I merge?
abrown commented on PR #10855:
Oops, looks like @alexcrichton and I raced; we can fix these nits later!
alexcrichton merged PR #10855.
Last updated: Dec 06 2025 at 07:03 UTC