abrown opened PR #10832 from abrown:asm-opcode-mod to bytecodealliance:main:
The x86 ISA includes a special format that, for certain instructions, writes the low three bits of the destination register into the low three bits of the opcode. This is specified with
+rb,+rw,+rd, and+roin the reference manual. This change adds a way to model this when defining instructions, e.g.,rex(...).rb().<!--
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abrown requested cfallin for a review on PR #10832.
abrown requested wasmtime-compiler-reviewers for a review on PR #10832.
abrown requested alexcrichton for a review on PR #10832.
cfallin submitted PR review:
LGTM, thanks!
cfallin created PR review comment:
Would it make sense to make this field an enum with
None,Rb,Rw,Rd,Roas options and a.bits()method? Not too important either way but that might make this a little more self-documenting/nicer.
abrown submitted PR review.
abrown created PR review comment:
:+1: I have another branch with that... abandoned because it was more lines. But, yeah, let me revive that since you mentioned it! I'll just add it to this PR and move the documentation around.
abrown updated PR #10832.
abrown has enabled auto merge for PR #10832.
abrown updated PR #10832.
abrown merged PR #10832.
Last updated: Dec 06 2025 at 07:03 UTC