Wasmtime GitHub notifications bot (May 14 2025 at 13:14): Wasmtime GitHub notifications bot (May 14 2025 at 13:14):uweigand opened PR #10774 from uweigand:s390x-ldbl to bytecodealliance:main:
This adds all missing operations to fully support f128 at the same level as f64 and f32 on s390x. The implementation is mostly a straightfoward extension of existing support, using the same vector instruction set. The exception is conversion between integer and f128, where we have to use the older floating-point instructions that use FPR register pairs to hold a f128 value. As regalloc does not support pairs, those registers are hard-coded, just as is done for the few instructions that require GPR register pairs.
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Wasmtime GitHub notifications bot (May 14 2025 at 13:14):uweigand requested cfallin for a review on PR #10774.
Wasmtime GitHub notifications bot (May 14 2025 at 13:14):uweigand requested wasmtime-compiler-reviewers for a review on PR #10774.
Wasmtime GitHub notifications bot (May 14 2025 at 14:46):github-actions[bot] commented on PR #10774:
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Wasmtime GitHub notifications bot (May 20 2025 at 16:13):cfallin submitted PR review:
Thanks for this implementation -- looks good!
Wasmtime GitHub notifications bot (May 20 2025 at 16:33):cfallin merged PR #10774.
Last updated: Dec 06 2025 at 07:03 UTC