MarinPostma edited PR #10109.
MarinPostma updated PR #10109.
MarinPostma updated PR #10109.
MarinPostma edited PR #10109:
implement
v128
simd logical operations:
v128.not
v128.and
v128.andnot
v128.or
v128.xor
alexcrichton commented on PR #10109:
Moving my review over to @saulecabrera who knows this better than I
alexcrichton requested saulecabrera for a review on PR #10109.
github-actions[bot] commented on PR #10109:
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MarinPostma updated PR #10109.
MarinPostma edited PR #10109:
implement
v128
simd logical operations:
v128.not
v128.and
v128.andnot
v128.or
v128.xor
v128.bitselect
MarinPostma edited PR #10109:
implement
v128
simd logical operations:
v128.not
v128.and
v128.andnot
v128.or
v128.xor
v128.bitselect
v128.any_true
MarinPostma updated PR #10109.
MarinPostma updated PR #10109.
MarinPostma edited PR #10109:
implement
v128
simd logical operations:
v128.not
v128.and
v128.andnot
v128.or
v128.xor
v128.bitselect
v128.any_true
v128.load8_lane
v128.load16_lane
v128.load32_lane
v128.load64_lane
MarinPostma updated PR #10109.
MarinPostma edited PR #10109:
implement
v128
simd logical operations:
v128.not
v128.and
v128.andnot
v128.or
v128.xor
v128.bitselect
v128.any_true
v128.load8_lane
v128.load16_lane
v128.load32_lane
v128.load64_lane
v128.store8_lane
v128.store16_lane
v128.store32_lane
v128.store64_lane
MarinPostma updated PR #10109.
saulecabrera submitted PR review.
saulecabrera created PR review comment:
Instead of introducing new load/stored methods, I'd suggest calling
wasm_load
andwasm_store
. This approach would probably require modifying the existingLoadKind
definition in case the current definition can't represent the semantics of lane loading/storing. That's the approach we've followed for other vector loads (e.g.,load_splat
)1 main reason:
- Wasm loads/stores are critical, from the sandboxing perspective, and we're trying to keep the implementation as tight as possible, reusing the existing methods makes auditing them and maintaining them much easier.
saulecabrera created PR review comment:
A small remark on naming: to be consistent with the rest of the naming in the MacroAssembler for type-specific instructions, perhaps we could consider prefixing all these methods with
v128_
? e.g.,v128_or
, similar to float operations, e.g.,float_abs
saulecabrera created PR review comment:
We need to check that the host/target supports AVX for all of these methods:
if !self.flags.has_avx() { bail!(CodeGenError::UnimplementedForNoAvx); }
MarinPostma updated PR #10109.
MarinPostma commented on PR #10109:
@saulecabrera it should be good now. I have take the opportunity to tighten store/loads even more regarding atomics operation. Having the
MemOpKind
as a separate arg meant that we could declare many opeartion as atomics, but that would have no effect.
MarinPostma edited a comment on PR #10109:
@saulecabrera it should be good now. I have taken the opportunity to tighten store/loads even more regarding atomics operation. Having the
MemOpKind
as a separate arg meant that we could declare many opeartion as atomics, but that would have no effect.
saulecabrera submitted PR review:
LGTM, thanks!
saulecabrera commented on PR #10109:
There's a conflict, once resolved, we can land this one.
MarinPostma updated PR #10109.
MarinPostma commented on PR #10109:
done
MarinPostma commented on PR #10109:
looks like a spurious failure? @saulecabrera
alexcrichton commented on PR #10109:
it's a bit hidden (alas) but I think that failure was non-spurious: https://github.com/bytecodealliance/wasmtime/actions/runs/13016537423/job/36307106911
saulecabrera commented on PR #10109:
Yeah, doesn't seem to be spurious. You need to update the spec tests here https://github.com/bytecodealliance/wasmtime/blob/main/crates/wast-util/src/lib.rs#L492 to include the ones that you enabled, so that it's marked as expected that these tests should fail on architectures that don't support AVX+. I believe this is mostly for for darwin x86_64, which runs via Rosetta and therefore there's no AVX support.
MarinPostma updated PR #10109.
MarinPostma commented on PR #10109:
I think I have fixed it, but I don't have a mac to try it right now. Thanks!
saulecabrera submitted PR review.
saulecabrera created PR review comment:
The failures that CI are related to the
vpinsr*
instruction, which are emitted here. We need to addself.ensure_has_avx()?
to get CI green.
saulecabrera edited PR review comment.
MarinPostma updated PR #10109.
MarinPostma submitted PR review.
MarinPostma created PR review comment:
I setup the action on my fork, all tests pass now. worry for the back and forth :sweat:
saulecabrera merged PR #10109.
Last updated: Feb 28 2025 at 03:10 UTC