wasmtime / Issue #2727 Cranelift: ishl.i128 with i128 shi... · git-wasmtime

Stream: git-wasmtime

Topic: wasmtime / Issue #2727 Cranelift: ishl.i128 with i128 shi...

Wasmtime GitHub notifications bot (Mar 15 2021 at 13:03):

Steps to Reproduce

Try to compile an ishl instruction with an i128 lhs and rhs using the x64 backend.

Expected Results

It compiles.

Actual Results

Panics with thread 'rustc' panicked at 'Multi-register value not expected', /home/bjorn/.cargo/git/checkouts/wasmtime-41807828cb3a7a7e/df6812b/cranelift/codegen/src/isa/x64/lower.rs:128:10

Versions and Environment

Cranelift version or commit: df6812b8559c35230d44c6d6f94a83b2b97b5de3

Operating system: N/A

Architecture: x86_64

This is similar to https://github.com/bytecodealliance/wasmtime/issues/2672 except that the lhs is also i128 in this case.

Wasmtime GitHub notifications bot (Mar 15 2021 at 13:03):

bjorn3 labeled Issue #2727:

Steps to Reproduce

Try to compile an ishl instruction with an i128 lhs and rhs using the x64 backend.

Expected Results

It compiles.

Actual Results

Panics with thread 'rustc' panicked at 'Multi-register value not expected', /home/bjorn/.cargo/git/checkouts/wasmtime-41807828cb3a7a7e/df6812b/cranelift/codegen/src/isa/x64/lower.rs:128:10

Versions and Environment

Cranelift version or commit: df6812b8559c35230d44c6d6f94a83b2b97b5de3

Operating system: N/A

Architecture: x86_64

This is similar to https://github.com/bytecodealliance/wasmtime/issues/2672 except that the lhs is also i128 in this case.

Wasmtime GitHub notifications bot (Mar 15 2021 at 13:03):

bjorn3 labeled Issue #2727:

Steps to Reproduce

Try to compile an ishl instruction with an i128 lhs and rhs using the x64 backend.

Expected Results

It compiles.

Actual Results

Panics with thread 'rustc' panicked at 'Multi-register value not expected', /home/bjorn/.cargo/git/checkouts/wasmtime-41807828cb3a7a7e/df6812b/cranelift/codegen/src/isa/x64/lower.rs:128:10

Versions and Environment

Cranelift version or commit: df6812b8559c35230d44c6d6f94a83b2b97b5de3

Operating system: N/A

Architecture: x86_64

This is similar to https://github.com/bytecodealliance/wasmtime/issues/2672 except that the lhs is also i128 in this case.

Wasmtime GitHub notifications bot (Mar 15 2021 at 16:08):

cfallin commented on Issue #2727:

Thanks for the report!

The fix here should be pretty easy -- we can just ignore the upper register since we mask the shift amount to 7 bits anyway. Happy to review a PR for this if you want to try, or I can get to it in a bit otherwise!

Wasmtime GitHub notifications bot (Mar 15 2021 at 16:18):

bjorn3 commented on Issue #2727:

It seems that the shift amount is also not properly masked for i128 lhs. I have something else I want to work on right now.

Wasmtime GitHub notifications bot (Mar 15 2021 at 17:01):

cfallin commented on Issue #2727:

It seems that the shift amount is also not properly masked for i128 lhs. I have something else I want to work on right now.

I don't think that's true, FWIW: see e.g. this test case. The masking is a bit subtle, as it happens in two parts -- the 64-bit shifts do their own implicit masking on x86, then the cmoves at the end are driven by the condition code from and amt, 64 (i.e. just bit 6, not higher bits).

Wasmtime GitHub notifications bot (May 10 2021 at 19:50):

cfallin closed Issue #2727:

Steps to Reproduce

Try to compile an ishl instruction with an i128 lhs and rhs using the x64 backend.

Expected Results

It compiles.

Actual Results

Panics with thread 'rustc' panicked at 'Multi-register value not expected', /home/bjorn/.cargo/git/checkouts/wasmtime-41807828cb3a7a7e/df6812b/cranelift/codegen/src/isa/x64/lower.rs:128:10

Versions and Environment

Cranelift version or commit: df6812b8559c35230d44c6d6f94a83b2b97b5de3

Operating system: N/A

Architecture: x86_64

This is similar to https://github.com/bytecodealliance/wasmtime/issues/2672 except that the lhs is also i128 in this case.

Last updated: Dec 23 2024 at 12:05 UTC