jlb6740 edited Issue #2272:
Last Update: 10/6/2020
Memory instruction |
opcode |
Status |
v128.load |
0x00 |
-- |
v128.load8x8_s |
0x01 |
-- |
v128.load8x8_u |
0x02 |
-- |
v128.load16x4_s |
0x03 |
-- |
v128.load16x4_u |
0x04 |
-- |
v128.load32x2_s |
0x05 |
-- |
v128.load32x2_u |
0x06 |
-- |
v128.load8_splat |
0x07 |
-- |
v128.load16_splat |
0x08 |
-- |
v128.load32_splat |
0x09 |
-- |
v128.load64_splat |
0x0a |
-- |
v128.store |
0x0b |
-- |
Basic operation |
opcode |
Status |
v128.const |
0x0c |
-- |
i8x16.shuffle |
0x0d |
-- |
i8x16.swizzle |
0x0e |
-- |
jlb6740 edited Issue #2272:
Status: Currently Not Valid (Initial Status WIP)
Last Update: 10/6/2020
Memory instruction |
opcode |
Status |
v128.load |
0x00 |
:+1: |
v128.load8x8_s |
0x01 |
-- |
v128.load8x8_u |
0x02 |
-- |
v128.load16x4_s |
0x03 |
-- |
v128.load16x4_u |
0x04 |
-- |
v128.load32x2_s |
0x05 |
-- |
v128.load32x2_u |
0x06 |
-- |
v128.load8_splat |
0x07 |
-- |
v128.load16_splat |
0x08 |
-- |
v128.load32_splat |
0x09 |
-- |
v128.load64_splat |
0x0a |
-- |
v128.store |
0x0b |
-- |
Basic operation |
opcode |
Status |
v128.const |
0x0c |
-- |
i8x16.shuffle |
0x0d |
-- |
i8x16.swizzle |
0x0e |
-- |
jlb6740 edited Issue #2272:
Status: Currently Not Valid (Initial Status WIP)
Last Update: 10/6/2020
Memory instruction |
opcode |
Status |
v128.load |
0x00 |
:+1: |
v128.load8x8_s |
0x01 |
-- |
v128.load8x8_u |
0x02 |
-- |
v128.load16x4_s |
0x03 |
-- |
v128.load16x4_u |
0x04 |
-- |
v128.load32x2_s |
0x05 |
-- |
v128.load32x2_u |
0x06 |
-- |
v128.load8_splat |
0x07 |
-- |
v128.load16_splat |
0x08 |
-- |
v128.load32_splat |
0x09 |
-- |
v128.load64_splat |
0x0a |
-- |
v128.store |
0x0b |
:+1: |
Basic operation |
opcode |
Status |
v128.const |
0x0c |
-- |
i8x16.shuffle |
0x0d |
-- |
i8x16.swizzle |
0x0e |
-- |
jlb6740 edited Issue #2272:
Status: Currently Not Valid (Initial Status WIP)
Last Update: 10/6/2020
Memory instruction |
opcode |
Status |
v128.load |
0x00 |
:+1: |
v128.load8x8_s |
0x01 |
:+1: |
v128.load8x8_u |
0x02 |
:+1: |
v128.load16x4_s |
0x03 |
:+1: |
v128.load16x4_u |
0x04 |
:+1: |
v128.load32x2_s |
0x05 |
:+1: |
v128.load32x2_u |
0x06 |
:+1: |
v128.load8_splat |
0x07 |
:+1: |
v128.load16_splat |
0x08 |
:+1: |
v128.load32_splat |
0x09 |
:+1: |
v128.load64_splat |
0x0a |
:+1: |
v128.store |
0x0b |
:+1: |
Basic operation |
opcode |
Status |
v128.const |
0x0c |
-- |
i8x16.shuffle |
0x0d |
-- |
i8x16.swizzle |
0x0e |
-- |
jlb6740 edited Issue #2272:
Status: Currently Not Valid (Initial Status WIP)
Last Update: 10/6/2020
https://gist.github.com/jlb6740/0a495404f6b3cc901e1b8e5ae8148020
Memory instruction |
opcode |
Status |
v128.load |
0x00 |
:+1: |
v128.load8x8_s |
0x01 |
:+1: |
v128.load8x8_u |
0x02 |
:+1: |
v128.load16x4_s |
0x03 |
:+1: |
v128.load16x4_u |
0x04 |
:+1: |
v128.load32x2_s |
0x05 |
:+1: |
v128.load32x2_u |
0x06 |
:+1: |
v128.load8_splat |
0x07 |
:+1: |
v128.load16_splat |
0x08 |
:+1: |
v128.load32_splat |
0x09 |
:+1: |
v128.load64_splat |
0x0a |
:+1: |
v128.store |
0x0b |
:+1: |
Basic operation |
opcode |
Status |
v128.const |
0x0c |
-- |
i8x16.shuffle |
0x0d |
-- |
i8x16.swizzle |
0x0e |
-- |
jlb6740 edited Issue #2272:
Status: Currently Not Valid (Initial Status WIP)
Last Update: 10/6/2020
https://gist.github.com/jlb6740/0a495404f6b3cc901e1b8e5ae8148020
Memory instruction |
opcode |
Status |
v128.load |
0x00 |
:+1: |
v128.load8x8_s |
0x01 |
:+1: |
v128.load8x8_u |
0x02 |
:+1: |
v128.load16x4_s |
0x03 |
:+1: |
v128.load16x4_u |
0x04 |
:+1: |
v128.load32x2_s |
0x05 |
:+1: |
v128.load32x2_u |
0x06 |
:+1: |
v128.load8_splat |
0x07 |
:+1: |
v128.load16_splat |
0x08 |
:+1: |
v128.load32_splat |
0x09 |
:+1: |
v128.load64_splat |
0x0a |
:+1: |
v128.store |
0x0b |
:+1: |
Basic operation |
opcode |
Status |
v128.const |
0x0c |
-- |
i8x16.shuffle |
0x0d |
-- |
i8x16.swizzle |
0x0e |
-- |
Splat operation |
opcode |
Status |
i8x16.splat |
0x0f |
-- |
i16x8.splat |
0x10 |
-- |
i32x4.splat |
0x11 |
-- |
i64x2.splat |
0x12 |
-- |
f32x4.splat |
0x13 |
-- |
f64x2.splat |
0x14 |
-- |
Lane operation |
opcode |
Status |
i8x16.extract_lane_s |
0x15 |
-- |
i8x16.extract_lane_u |
0x16 |
-- |
i8x16.replace_lane |
0x17 |
-- |
i16x8.extract_lane_s |
0x18 |
-- |
i16x8.extract_lane_u |
0x19 |
-- |
i16x8.replace_lane |
0x1a |
-- |
i32x4.extract_lane |
0x1b |
-- |
i32x4.replace_lane |
0x1c |
-- |
i64x2.extract_lane |
0x1d |
-- |
i64x2.replace_lane |
0x1e |
-- |
f32x4.extract_lane |
0x1f |
-- |
f32x4.replace_lane |
0x20 |
-- |
f64x2.extract_lane |
0x21 |
-- |
f64x2.replace_lane |
0x22 |
-- |
Integer Cmp |
opcode |
Status |
i8x16.eq |
0x23 |
-- |
i8x16.ne |
0x24 |
-- |
i8x16.lt_s |
0x25 |
-- |
i8x16.lt_u |
0x26 |
-- |
i8x16.gt_s |
0x27 |
-- |
i8x16.gt_u |
0x28 |
-- |
i8x16.le_s |
0x29 |
-- |
i8x16.le_u |
0x2a |
-- |
i8x16.ge_s |
0x2b |
-- |
i8x16.ge_u |
0x2c |
-- |
i16x8.eq |
0x2d |
-- |
i16x8.ne |
0x2e |
-- |
i16x8.lt_s |
0x2f |
-- |
i16x8.lt_u |
0x30 |
-- |
i16x8.gt_s |
0x31 |
-- |
i16x8.gt_u |
0x32 |
-- |
i16x8.le_s |
0x33 |
-- |
i16x8.le_u |
0x34 |
-- |
i16x8.ge_s |
0x35 |
-- |
i16x8.ge_u |
0x36 |
-- |
i32x4.eq |
0x37 |
-- |
i32x4.ne |
0x38 |
-- |
i32x4.lt_s |
0x39 |
-- |
i32x4.lt_u |
0x3a |
-- |
i32x4.gt_s |
0x3b |
-- |
i32x4.gt_u |
0x3c |
-- |
i32x4.le_s |
0x3d |
-- |
i32x4.le_u |
0x3e |
-- |
i32x4.ge_s |
0x3f |
-- |
i32x4.ge_u |
0x40 |
-- |
v128 Op |
opcode |
Status |
v128.not |
0x4d |
-- |
v128.and |
0x4e |
-- |
v128.andnot |
0x4f |
-- |
v128.or |
0x50 |
-- |
v128.xor |
0x51 |
-- |
v128.bitselect |
0x52 |
-- |
i8x16 Op |
opcode |
i16x8 Op |
opcode |
i32x4 Op |
opcode |
i64x2 Op |
opcode |
i8x16.abs |
0x60 |
i16x8.abs |
0x80 |
i32x4.abs |
0xa0 |
---- |
0xc0 |
i8x16.neg |
0x61 |
i16x8.neg |
0x81 |
i32x4.neg |
0xa1 |
i64x2.neg |
0xc1 |
i8x16.any_true |
0x62 |
i16x8.any_true |
0x82 |
i32x4.any_true |
0xa2 |
---- |
0xc2 |
i8x16.all_true |
0x63 |
i16x8.all_true |
0x83 |
i32x4.all_true |
0xa3 |
---- |
0xc3 |
i8x16.bitmask |
0x64 |
i16x8.bitmask |
0x84 |
i32x4.bitmask |
0xa4 |
---- |
0xc4 |
i8x16.narrow_i16x8_s |
0x65 |
i16x8.narrow_i32x4_s |
0x85 |
---- narrow ---- |
0xa5 |
---- |
0xc5 |
i8x16.narrow_i16x8_u |
0x66 |
i16x8.narrow_i32x4_u |
0x86 |
---- narrow ---- |
0xa6 |
---- |
0xc6 |
---- widen ---- |
0x67 |
i16x8.widen_low_i8x16_s |
0x87 |
i32x4.widen_low_i16x8_s |
0xa7 |
---- |
0xc7 |
---- widen ---- |
0x68 |
i16x8.widen_high_i8x16_s |
0x88 |
i32x4.widen_high_i16x8_s |
0xa8 |
---- |
0xc8 |
---- widen ---- |
0x69 |
i16x8.widen_low_i8x16_u |
0x89 |
i32x4.widen_low_i16x8_u |
0xa9 |
---- |
0xc9 |
---- widen ---- |
0x6a |
i16x8.widen_high_i8x16_u |
0x8a |
i32x4.widen_high_i16x8_u |
0xaa |
---- |
0xca |
i8x16.shl |
0x6b |
i16x8.shl |
0x8b |
i32x4.shl |
0xab |
i64x2.shl |
0xcb |
i8x16.shr_s |
0x6c |
i16x8.shr_s |
0x8c |
i32x4.shr_s |
0xac |
i64x2.shr_s |
0xcc |
i8x16.shr_u |
0x6d |
i16x8.shr_u |
0x8d |
i32x4.shr_u |
0xad |
i64x2.shr_u |
0xcd |
i8x16.add |
0x6e |
i16x8.add |
0x8e |
i32x4.add |
0xae |
i64x2.add |
0xce |
i8x16.add_sat_s |
0x6f |
i16x8.add_sat_s |
0x8f |
---- add_sat ---- |
0xaf |
---- |
0xcf |
i8x16.add_sat_u |
0x70 |
i16x8.add_sat_u |
0x90 |
---- add_sat ---- |
0xb0 |
---- |
0xd0 |
i8x16.sub |
0x71 |
i16x8.sub |
0x91 |
i32x4.sub |
0xb1 |
i64x2.sub |
0xd1 |
i8x16.sub_sat_s |
0x72 |
i16x8.sub_sat_s |
0x92 |
---- sub_sat ---- |
0xb2 |
---- |
0xd2 |
i8x16.sub_sat_u |
0x73 |
i16x8.sub_sat_u |
0x93 |
---- sub_sat ---- |
0xb3 |
---- |
0xd3 |
---- dot ---- |
0x74 |
---- dot ---- |
0x94 |
---- dot ---- |
0xb4 |
---- |
0xd4 |
---- mul ---- |
0x75 |
i16x8.mul |
0x95 |
i32x4.mul |
0xb5 |
i64x2.mul |
0xd5 |
i8x16.min_s |
0x76 |
i16x8.min_s |
0x96 |
i32x4.min_s |
0xb6 |
---- |
0xd6 |
i8x16.min_u |
0x77 |
i16x8.min_u |
0x97 |
i32x4.min_u |
0xb7 |
---- |
0xd7 |
i8x16.max_s |
0x78 |
i16x8.max_s |
0x98 |
i32x4.max_s |
0xb8 |
---- |
0xd8 |
i8x16.max_u |
0x79 |
i16x8.max_u |
0x99 |
i32x4.max_u |
0xb9 |
---- |
0xd9 |
---- avgr_s ---- |
0x7a |
---- avgr_s ---- |
0x9a |
---- avgr_s ---- |
0xba |
---- |
0xda |
i8x16.avgr_u |
0x7b |
i16x8.avgr_u |
0x9b |
---- avgr_u ---- |
0xbb |
---- |
0xdb |
f32x4 Op |
opcode |
f64x2 Op |
opcode |
f32x4.abs |
0xe0 |
f64x2.abs |
0xec |
f32x4.neg |
0xe1 |
f64x2.neg |
0xed |
---- round ---- |
0xe2 |
---- round ---- |
0xee |
f32x4.sqrt |
0xe3 |
f64x2.sqrt |
0xef |
f32x4.add |
0xe4 |
f64x2.add |
0xf0 |
f32x4.sub |
0xe5 |
f64x2.sub |
0xf1 |
f32x4.mul |
0xe6 |
f64x2.mul |
0xf2 |
f32x4.div |
0xe7 |
f64x2.div |
0xf3 |
f32x4.min |
0xe8 |
f64x2.min |
0xf4 |
f32x4.max |
0xe9 |
f64x2.max |
0xf5 |
f32x4.pmin |
0xea |
f64x2.pmin |
0xf6 |
f32x4.pmax |
0xeb |
f64x2.pmax |
0xf7 |
Conversion Op |
opcode |
-- |
i32x4.trunc_sat_f32x4_s |
0xf8 |
-- |
i32x4.trunc_sat_f32x4_u |
0xf9 |
-- |
f32x4.convert_i32x4_s |
0xfa |
-- |
f32x4.convert_i32x4_u |
0xfb |
-- |
jlb6740 edited Issue #2272:
Status: Currently Not Valid (Initial Status WIP)
Last Update: 10/8/2020
https://gist.github.com/jlb6740/0a495404f6b3cc901e1b8e5ae8148020
Memory instruction |
opcode |
Status |
v128.load |
0x00 |
:+1: |
v128.load8x8_s |
0x01 |
:+1: |
v128.load8x8_u |
0x02 |
:+1: |
v128.load16x4_s |
0x03 |
:+1: |
v128.load16x4_u |
0x04 |
:+1: |
v128.load32x2_s |
0x05 |
:+1: |
v128.load32x2_u |
0x06 |
:+1: |
v128.load8_splat |
0x07 |
:+1: |
v128.load16_splat |
0x08 |
:+1: |
v128.load32_splat |
0x09 |
:+1: |
v128.load64_splat |
0x0a |
:+1: |
v128.store |
0x0b |
:+1: |
Basic operation |
opcode |
Status |
v128.const |
0x0c |
-- |
i8x16.shuffle |
0x0d |
-- |
i8x16.swizzle |
0x0e |
-- |
Splat operation |
opcode |
Status |
i8x16.splat |
0x0f |
-- |
i16x8.splat |
0x10 |
-- |
i32x4.splat |
0x11 |
-- |
i64x2.splat |
0x12 |
-- |
f32x4.splat |
0x13 |
-- |
f64x2.splat |
0x14 |
-- |
Lane operation |
opcode |
Status |
i8x16.extract_lane_s |
0x15 |
-- |
i8x16.extract_lane_u |
0x16 |
-- |
i8x16.replace_lane |
0x17 |
-- |
i16x8.extract_lane_s |
0x18 |
-- |
i16x8.extract_lane_u |
0x19 |
-- |
i16x8.replace_lane |
0x1a |
-- |
i32x4.extract_lane |
0x1b |
-- |
i32x4.replace_lane |
0x1c |
-- |
i64x2.extract_lane |
0x1d |
-- |
i64x2.replace_lane |
0x1e |
-- |
f32x4.extract_lane |
0x1f |
-- |
f32x4.replace_lane |
0x20 |
-- |
f64x2.extract_lane |
0x21 |
-- |
f64x2.replace_lane |
0x22 |
-- |
Integer Cmp |
opcode |
Status |
i8x16.eq |
0x23 |
-- |
i8x16.ne |
0x24 |
-- |
i8x16.lt_s |
0x25 |
-- |
i8x16.lt_u |
0x26 |
-- |
i8x16.gt_s |
0x27 |
-- |
i8x16.gt_u |
0x28 |
-- |
i8x16.le_s |
0x29 |
-- |
i8x16.le_u |
0x2a |
-- |
i8x16.ge_s |
0x2b |
-- |
i8x16.ge_u |
0x2c |
-- |
i16x8.eq |
0x2d |
-- |
i16x8.ne |
0x2e |
-- |
i16x8.lt_s |
0x2f |
-- |
i16x8.lt_u |
0x30 |
-- |
i16x8.gt_s |
0x31 |
-- |
i16x8.gt_u |
0x32 |
-- |
i16x8.le_s |
0x33 |
-- |
i16x8.le_u |
0x34 |
-- |
i16x8.ge_s |
0x35 |
-- |
i16x8.ge_u |
0x36 |
-- |
i32x4.eq |
0x37 |
-- |
i32x4.ne |
0x38 |
-- |
i32x4.lt_s |
0x39 |
-- |
i32x4.lt_u |
0x3a |
-- |
i32x4.gt_s |
0x3b |
-- |
i32x4.gt_u |
0x3c |
-- |
i32x4.le_s |
0x3d |
-- |
i32x4.le_u |
0x3e |
-- |
i32x4.ge_s |
0x3f |
-- |
i32x4.ge_u |
0x40 |
-- |
v128 Op |
opcode |
Status |
v128.not |
0x4d |
-- |
v128.and |
0x4e |
-- |
v128.andnot |
0x4f |
-- |
v128.or |
0x50 |
-- |
v128.xor |
0x51 |
-- |
v128.bitselect |
0x52 |
-- |
i8x16 Op |
opcode |
i16x8 Op |
opcode |
i32x4 Op |
opcode |
i64x2 Op |
opcode |
i8x16.abs |
0x60 |
i16x8.abs |
0x80 |
i32x4.abs |
0xa0 |
---- |
0xc0 |
i8x16.neg |
0x61 |
i16x8.neg |
0x81 |
i32x4.neg |
0xa1 |
i64x2.neg |
0xc1 |
i8x16.any_true |
0x62 |
i16x8.any_true |
0x82 |
i32x4.any_true |
0xa2 |
---- |
0xc2 |
i8x16.all_true |
0x63 |
i16x8.all_true |
0x83 |
i32x4.all_true |
0xa3 |
---- |
0xc3 |
i8x16.bitmask |
0x64 |
i16x8.bitmask |
0x84 |
i32x4.bitmask |
0xa4 |
---- |
0xc4 |
i8x16.narrow_i16x8_s |
0x65 |
i16x8.narrow_i32x4_s |
0x85 |
---- narrow ---- |
0xa5 |
---- |
0xc5 |
i8x16.narrow_i16x8_u |
0x66 |
i16x8.narrow_i32x4_u |
0x86 |
---- narrow ---- |
0xa6 |
---- |
0xc6 |
---- widen ---- |
0x67 |
i16x8.widen_low_i8x16_s |
0x87 |
i32x4.widen_low_i16x8_s |
0xa7 |
---- |
0xc7 |
---- widen ---- |
0x68 |
i16x8.widen_high_i8x16_s |
0x88 |
i32x4.widen_high_i16x8_s |
0xa8 |
---- |
0xc8 |
---- widen ---- |
0x69 |
i16x8.widen_low_i8x16_u |
0x89 |
i32x4.widen_low_i16x8_u |
0xa9 |
---- |
0xc9 |
---- widen ---- |
0x6a |
i16x8.widen_high_i8x16_u |
0x8a |
i32x4.widen_high_i16x8_u |
0xaa |
---- |
0xca |
i8x16.shl |
0x6b |
i16x8.shl |
0x8b |
i32x4.shl |
0xab |
i64x2.shl |
0xcb |
i8x16.shr_s |
0x6c |
i16x8.shr_s |
0x8c |
i32x4.shr_s |
0xac |
i64x2.shr_s |
0xcc |
i8x16.shr_u |
0x6d |
i16x8.shr_u |
0x8d |
i32x4.shr_u |
0xad |
i64x2.shr_u |
0xcd |
i8x16.add |
0x6e |
i16x8.add |
0x8e |
i32x4.add |
0xae |
i64x2.add |
0xce |
i8x16.add_sat_s |
0x6f |
i16x8.add_sat_s |
0x8f |
---- add_sat ---- |
0xaf |
---- |
0xcf |
i8x16.add_sat_u |
0x70 |
i16x8.add_sat_u |
0x90 |
---- add_sat ---- |
0xb0 |
---- |
0xd0 |
i8x16.sub |
0x71 |
i16x8.sub |
0x91 |
i32x4.sub |
0xb1 |
i64x2.sub |
0xd1 |
i8x16.sub_sat_s |
0x72 |
i16x8.sub_sat_s |
0x92 |
---- sub_sat ---- |
0xb2 |
---- |
0xd2 |
i8x16.sub_sat_u |
0x73 |
i16x8.sub_sat_u |
0x93 |
---- sub_sat ---- |
0xb3 |
---- |
0xd3 |
---- dot ---- |
0x74 |
---- dot ---- |
0x94 |
---- dot ---- |
0xb4 |
---- |
0xd4 |
---- mul ---- |
0x75 |
i16x8.mul |
0x95 |
i32x4.mul |
0xb5 |
i64x2.mul |
0xd5 |
i8x16.min_s |
0x76 |
i16x8.min_s |
0x96 |
i32x4.min_s |
0xb6 |
---- |
0xd6 |
i8x16.min_u |
0x77 |
i16x8.min_u |
0x97 |
i32x4.min_u |
0xb7 |
---- |
0xd7 |
i8x16.max_s |
0x78 |
i16x8.max_s |
0x98 |
i32x4.max_s |
0xb8 |
---- |
0xd8 |
i8x16.max_u |
0x79 |
i16x8.max_u |
0x99 |
i32x4.max_u |
0xb9 |
---- |
0xd9 |
---- avgr_s ---- |
0x7a |
---- avgr_s ---- |
0x9a |
---- avgr_s ---- |
0xba |
---- |
0xda |
i8x16.avgr_u |
0x7b |
i16x8.avgr_u |
0x9b |
---- avgr_u ---- |
0xbb |
---- |
0xdb |
f32x4 Op |
opcode |
f64x2 Op |
opcode |
f32x4.abs |
0xe0 |
f64x2.abs |
0xec |
f32x4.neg |
0xe1 |
f64x2.neg |
0xed |
---- round ---- |
0xe2 |
---- round ---- |
0xee |
f32x4.sqrt |
0xe3 |
f64x2.sqrt |
0xef |
f32x4.add |
0xe4 |
f64x2.add |
0xf0 |
f32x4.sub |
0xe5 |
f64x2.sub |
0xf1 |
f32x4.mul |
0xe6 |
f64x2.mul |
0xf2 |
f32x4.div |
0xe7 |
f64x2.div |
0xf3 |
f32x4.min |
0xe8 |
f64x2.min |
0xf4 |
f32x4.max |
0xe9 |
f64x2.max |
0xf5 |
f32x4.pmin |
0xea |
f64x2.pmin |
0xf6 |
f32x4.pmax |
0xeb |
f64x2.pmax |
0xf7 |
Conversion Op |
opcode |
-- |
i32x4.trunc_sat_f32x4_s |
0xf8 |
-- |
i32x4.trunc_sat_f32x4_u |
0xf9 |
-- |
f32x4.convert_i32x4_s |
0xfa |
-- |
f32x4.convert_i32x4_u |
0xfb |
-- |
jlb6740 edited Issue #2272:
Status: Currently Not Valid (Initial Status WIP)
Last Update: 10/8/2020
https://gist.github.com/jlb6740/0a495404f6b3cc901e1b8e5ae8148020
Memory instruction |
opcode |
Status |
v128.load |
0x00 |
:+1: |
v128.load8x8_s |
0x01 |
:+1: |
v128.load8x8_u |
0x02 |
:+1: |
v128.load16x4_s |
0x03 |
:+1: |
v128.load16x4_u |
0x04 |
:+1: |
v128.load32x2_s |
0x05 |
:+1: |
v128.load32x2_u |
0x06 |
:+1: |
v128.load8_splat |
0x07 |
:+1: |
v128.load16_splat |
0x08 |
:+1: |
v128.load32_splat |
0x09 |
:+1: |
v128.load64_splat |
0x0a |
:+1: |
v128.store |
0x0b |
:+1: |
Basic operation |
opcode |
Status |
v128.const |
0x0c |
-- |
i8x16.shuffle |
0x0d |
-- |
i8x16.swizzle |
0x0e |
-- |
Splat operation |
opcode |
Status |
i8x16.splat |
0x0f |
-- |
i16x8.splat |
0x10 |
-- |
i32x4.splat |
0x11 |
-- |
i64x2.splat |
0x12 |
-- |
f32x4.splat |
0x13 |
-- |
f64x2.splat |
0x14 |
-- |
Lane operation |
opcode |
Status |
i8x16.extract_lane_s |
0x15 |
-- |
i8x16.extract_lane_u |
0x16 |
-- |
i8x16.replace_lane |
0x17 |
-- |
i16x8.extract_lane_s |
0x18 |
-- |
i16x8.extract_lane_u |
0x19 |
-- |
i16x8.replace_lane |
0x1a |
-- |
i32x4.extract_lane |
0x1b |
-- |
i32x4.replace_lane |
0x1c |
-- |
i64x2.extract_lane |
0x1d |
-- |
i64x2.replace_lane |
0x1e |
-- |
f32x4.extract_lane |
0x1f |
-- |
f32x4.replace_lane |
0x20 |
-- |
f64x2.extract_lane |
0x21 |
-- |
f64x2.replace_lane |
0x22 |
-- |
Integer Cmp |
opcode |
Status |
i8x16.eq |
0x23 |
-- |
i8x16.ne |
0x24 |
-- |
i8x16.lt_s |
0x25 |
-- |
i8x16.lt_u |
0x26 |
-- |
i8x16.gt_s |
0x27 |
-- |
i8x16.gt_u |
0x28 |
-- |
i8x16.le_s |
0x29 |
-- |
i8x16.le_u |
0x2a |
-- |
i8x16.ge_s |
0x2b |
-- |
i8x16.ge_u |
0x2c |
-- |
i16x8.eq |
0x2d |
-- |
i16x8.ne |
0x2e |
-- |
i16x8.lt_s |
0x2f |
-- |
i16x8.lt_u |
0x30 |
-- |
i16x8.gt_s |
0x31 |
-- |
i16x8.gt_u |
0x32 |
-- |
i16x8.le_s |
0x33 |
-- |
i16x8.le_u |
0x34 |
-- |
i16x8.ge_s |
0x35 |
-- |
i16x8.ge_u |
0x36 |
-- |
i32x4.eq |
0x37 |
-- |
i32x4.ne |
0x38 |
-- |
i32x4.lt_s |
0x39 |
-- |
i32x4.lt_u |
0x3a |
-- |
i32x4.gt_s |
0x3b |
-- |
i32x4.gt_u |
0x3c |
-- |
i32x4.le_s |
0x3d |
-- |
i32x4.le_u |
0x3e |
-- |
i32x4.ge_s |
0x3f |
-- |
i32x4.ge_u |
0x40 |
-- |
v128 Op |
opcode |
Status |
v128.not |
0x4d |
-- |
v128.and |
0x4e |
-- |
v128.andnot |
0x4f |
-- |
v128.or |
0x50 |
-- |
v128.xor |
0x51 |
-- |
v128.bitselect |
0x52 |
-- |
i8x16 Arith Op |
opcode |
-- |
i8x16.abs |
0x60 |
|
i8x16.neg |
0x61 |
|
i8x16.any_true |
0x62 |
|
i8x16.all_true |
0x63 |
|
i8x16.bitmask |
0x64 |
|
i8x16.narrow_i16x8_s |
0x65 |
|
i8x16.narrow_i16x8_u |
0x66 |
|
---- widen ---- |
0x67 |
|
---- widen ---- |
0x68 |
|
---- widen ---- |
0x69 |
|
---- widen ---- |
0x6a |
|
i8x16.shl |
0x6b |
|
i8x16.shr_s |
0x6c |
i16x8.shr_s |
i8x16.shr_u |
0x6d |
i16x8.shr_u |
i8x16.add |
0x6e |
i16x8.add |
i8x16.add_sat_s |
0x6f |
i16x8.add_sat_s |
i8x16.add_sat_u |
0x70 |
i16x8.add_sat_u |
i8x16.sub |
0x71 |
i16x8.sub |
i8x16.sub_sat_s |
0x72 |
i16x8.sub_sat_s |
i8x16.sub_sat_u |
0x73 |
i16x8.sub_sat_u |
---- dot ---- |
0x74 |
---- dot ---- |
---- mul ---- |
0x75 |
i16x8.mul |
i8x16.min_s |
0x76 |
i16x8.min_s |
i8x16.min_u |
0x77 |
i16x8.min_u |
i8x16.max_s |
0x78 |
i16x8.max_s |
i8x16.max_u |
0x79 |
i16x8.max_u |
---- avgr_s ---- |
0x7a |
---- avgr_s ---- |
i8x16.avgr_u |
0x7b |
i16x8.avgr_u |
i16x8 Arith Op |
opcode |
-- |
i16x8.abs |
0x80 |
|
i16x8.neg |
0x81 |
|
i16x8.any_true |
0x82 |
|
i16x8.all_true |
0x83 |
|
i16x8.bitmask |
0x84 |
|
i16x8.narrow_i32x4_s |
0x85 |
|
i16x8.narrow_i32x4_u |
0x86 |
|
i16x8.widen_low_i8x16_s |
0x87 |
|
i16x8.widen_high_i8x16_s |
0x88 |
|
i16x8.widen_low_i8x16_u |
0x89 |
|
i16x8.widen_high_i8x16_u |
0x8a |
|
i16x8.shl |
0x8b |
|
i32x4 Arith Op |
opcode |
-- |
i32x4.abs |
0xa0 |
|
i32x4.neg |
0xa1 |
|
i32x4.any_true |
0xa2 |
|
i32x4.all_true |
0xa3 |
|
i32x4.bitmask |
0xa4 |
|
---- narrow ---- |
0xa5 |
|
---- narrow ---- |
0xa6 |
|
i32x4.widen_low_i16x8_s |
0xa7 |
|
i32x4.widen_high_i16x8_s |
0xa8 |
|
i32x4.widen_low_i16x8_u |
0xa9 |
|
i32x4.widen_high_i16x8_u |
0xaa |
|
i32x4.shl |
0xab |
|
i64x2 Arith Op |
opcode |
-- |
---- |
0xc0 |
|
i64x2.neg |
0xc1 |
|
---- |
0xc2 |
|
---- |
0xc3 |
|
---- |
0xc4 |
|
---- |
0xc5 |
|
---- |
0xc6 |
|
---- |
0xc7 |
|
---- |
0xc8 |
|
---- |
0xc9 |
|
---- |
0xca |
|
i64x2.shl |
0xcb |
|
f32x4 Op |
opcode |
-- |
f32x4.abs |
0xe0 |
-- |
f32x4.neg |
0xe1 |
-- |
---- round ---- |
0xe2 |
-- |
f32x4.sqrt |
0xe3 |
-- |
f32x4.add |
0xe4 |
-- |
f32x4.sub |
0xe5 |
-- |
f32x4.mul |
0xe6 |
-- |
f32x4.div |
0xe7 |
-- |
f32x4.min |
0xe8 |
-- |
f32x4.max |
0xe9 |
-- |
f32x4.pmin |
0xea |
-- |
f32x4.pmax |
0xeb |
-- |
f64x2 Op |
opcode |
-- |
f64x2.abs |
0xec |
-- |
f64x2.neg |
0xed |
-- |
---- round ---- |
0xee |
-- |
f64x2.sqrt |
0xef |
-- |
f64x2.add |
0xf0 |
-- |
f64x2.sub |
0xf1 |
-- |
f64x2.mul |
0xf2 |
-- |
f64x2.div |
0xf3 |
-- |
f64x2.min |
0xf4 |
-- |
f64x2.max |
0xf5 |
-- |
f64x2.pmin |
0xf6 |
-- |
f64x2.pmax |
0xf7 |
-- |
Conversion Op |
opcode |
-- |
i32x4.trunc_sat_f32x4_s |
0xf8 |
-- |
i32x4.trunc_sat_f32x4_u |
0xf9 |
-- |
f32x4.convert_i32x4_s |
0xfa |
-- |
f32x4.convert_i32x4_u |
0xfb |
-- |
jlb6740 edited Issue #2272:
Status: Currently Not Valid (Initial Status WIP)
Last Update: 10/8/2020
https://gist.github.com/jlb6740/0a495404f6b3cc901e1b8e5ae8148020
Memory instruction |
opcode |
Status |
v128.load |
0x00 |
:+1: |
v128.load8x8_s |
0x01 |
:+1: |
v128.load8x8_u |
0x02 |
:+1: |
v128.load16x4_s |
0x03 |
:+1: |
v128.load16x4_u |
0x04 |
:+1: |
v128.load32x2_s |
0x05 |
:+1: |
v128.load32x2_u |
0x06 |
:+1: |
v128.load8_splat |
0x07 |
:+1: |
v128.load16_splat |
0x08 |
:+1: |
v128.load32_splat |
0x09 |
:+1: |
v128.load64_splat |
0x0a |
:+1: |
v128.store |
0x0b |
:+1: |
Basic operation |
opcode |
Status |
v128.const |
0x0c |
-- |
i8x16.shuffle |
0x0d |
-- |
i8x16.swizzle |
0x0e |
-- |
Splat operation |
opcode |
Status |
i8x16.splat |
0x0f |
-- |
i16x8.splat |
0x10 |
-- |
i32x4.splat |
0x11 |
-- |
i64x2.splat |
0x12 |
-- |
f32x4.splat |
0x13 |
-- |
f64x2.splat |
0x14 |
-- |
Lane operation |
opcode |
Status |
i8x16.extract_lane_s |
0x15 |
-- |
i8x16.extract_lane_u |
0x16 |
-- |
i8x16.replace_lane |
0x17 |
-- |
i16x8.extract_lane_s |
0x18 |
-- |
i16x8.extract_lane_u |
0x19 |
-- |
i16x8.replace_lane |
0x1a |
-- |
i32x4.extract_lane |
0x1b |
-- |
i32x4.replace_lane |
0x1c |
-- |
i64x2.extract_lane |
0x1d |
-- |
i64x2.replace_lane |
0x1e |
-- |
f32x4.extract_lane |
0x1f |
-- |
f32x4.replace_lane |
0x20 |
-- |
f64x2.extract_lane |
0x21 |
-- |
f64x2.replace_lane |
0x22 |
-- |
Integer Cmp |
opcode |
Status |
i8x16.eq |
0x23 |
-- |
i8x16.ne |
0x24 |
-- |
i8x16.lt_s |
0x25 |
-- |
i8x16.lt_u |
0x26 |
-- |
i8x16.gt_s |
0x27 |
-- |
i8x16.gt_u |
0x28 |
-- |
i8x16.le_s |
0x29 |
-- |
i8x16.le_u |
0x2a |
-- |
i8x16.ge_s |
0x2b |
-- |
i8x16.ge_u |
0x2c |
-- |
i16x8.eq |
0x2d |
-- |
i16x8.ne |
0x2e |
-- |
i16x8.lt_s |
0x2f |
-- |
i16x8.lt_u |
0x30 |
-- |
i16x8.gt_s |
0x31 |
-- |
i16x8.gt_u |
0x32 |
-- |
i16x8.le_s |
0x33 |
-- |
i16x8.le_u |
0x34 |
-- |
i16x8.ge_s |
0x35 |
-- |
i16x8.ge_u |
0x36 |
-- |
i32x4.eq |
0x37 |
-- |
i32x4.ne |
0x38 |
-- |
i32x4.lt_s |
0x39 |
-- |
i32x4.lt_u |
0x3a |
-- |
i32x4.gt_s |
0x3b |
-- |
i32x4.gt_u |
0x3c |
-- |
i32x4.le_s |
0x3d |
-- |
i32x4.le_u |
0x3e |
-- |
i32x4.ge_s |
0x3f |
-- |
i32x4.ge_u |
0x40 |
-- |
v128 Op |
opcode |
Status |
v128.not |
0x4d |
-- |
v128.and |
0x4e |
-- |
v128.andnot |
0x4f |
-- |
v128.or |
0x50 |
-- |
v128.xor |
0x51 |
-- |
v128.bitselect |
0x52 |
-- |
i8x16 Arith Op |
opcode |
-- |
i8x16.abs |
0x60 |
-- |
i8x16.neg |
0x61 |
-- |
i8x16.any_true |
0x62 |
-- |
i8x16.all_true |
0x63 |
-- |
i8x16.bitmask |
0x64 |
-- |
i8x16.narrow_i16x8_s |
0x65 |
-- |
i8x16.narrow_i16x8_u |
0x66 |
-- |
---- widen ---- |
0x67 |
-- |
---- widen ---- |
0x68 |
-- |
---- widen ---- |
0x69 |
-- |
---- widen ---- |
0x6a |
-- |
i8x16.shl |
0x6b |
-- |
i8x16.shr_s |
0x6c |
-- |
i8x16.shr_u |
0x6d |
-- |
i8x16.add |
0x6e |
-- |
i8x16.add_sat_s |
0x6f |
-- |
i8x16.add_sat_u |
0x70 |
-- |
i8x16.sub |
0x71 |
-- |
i8x16.sub_sat_s |
0x72 |
-- |
i8x16.sub_sat_u |
0x73 |
-- |
---- dot ---- |
0x74 |
-- |
---- mul ---- |
0x75 |
-- |
i8x16.min_s |
0x76 |
-- |
i8x16.min_u |
0x77 |
-- |
i8x16.max_s |
0x78 |
-- |
i8x16.max_u |
0x79 |
-- |
---- avgr_s ---- |
0x7a |
-- |
i8x16.avgr_u |
0x7b |
-- |
i16x8 Arith Op |
opcode |
-- |
i16x8.abs |
0x80 |
-- |
i16x8.neg |
0x81 |
-- |
i16x8.any_true |
0x82 |
-- |
i16x8.all_true |
0x83 |
-- |
i16x8.bitmask |
0x84 |
-- |
i16x8.narrow_i32x4_s |
0x85 |
-- |
i16x8.narrow_i32x4_u |
0x86 |
-- |
i16x8.widen_low_i8x16_s |
0x87 |
-- |
i16x8.widen_high_i8x16_s |
0x88 |
-- |
i16x8.widen_low_i8x16_u |
0x89 |
-- |
i16x8.widen_high_i8x16_u |
0x8a |
-- |
i16x8.shl |
0x8b |
-- |
i16x8.shr_s |
0x8c |
-- |
i16x8.shr_u |
0x8d |
-- |
i16x8.add |
0x8e |
-- |
i16x8.add_sat_s |
0x8f |
-- |
i16x8.add_sat_u |
0x90 |
-- |
i16x8.sub |
0x91 |
-- |
i16x8.sub_sat_s |
0x92 |
-- |
i16x8.sub_sat_u |
0x93 |
-- |
---- dot ---- |
0x94 |
-- |
i16x8.mul |
0x95 |
-- |
i16x8.min_s |
0x96 |
-- |
i16x8.min_u |
0x97 |
-- |
i16x8.max_s |
0x98 |
-- |
i16x8.max_u |
0x99 |
-- |
---- avgr_s ---- |
0x9a |
-- |
i16x8.avgr_u |
0x9b |
-- |
i32x4 Arith Op |
opcode |
Status |
i32x4.abs |
0xa0 |
-- |
i32x4.neg |
0xa1 |
-- |
i32x4.any_true |
0xa2 |
-- |
i32x4.all_true |
0xa3 |
-- |
i32x4.bitmask |
0xa4 |
-- |
---- narrow ---- |
0xa5 |
-- |
---- narrow ---- |
0xa6 |
-- |
i32x4.widen_low_i16x8_s |
0xa7 |
-- |
i32x4.widen_high_i16x8_s |
0xa8 |
-- |
i32x4.widen_low_i16x8_u |
0xa9 |
-- |
i32x4.widen_high_i16x8_u |
0xaa |
-- |
i32x4.shl |
0xab |
-- |
i32x4.shr_s |
0xac |
-- |
i32x4.shr_u |
0xad |
-- |
i32x4.add |
0xae |
-- |
---- add_sat ---- |
0xaf |
-- |
---- add_sat ---- |
0xb0 |
-- |
i32x4.sub |
0xb1 |
-- |
---- sub_sat ---- |
0xb2 |
-- |
---- sub_sat ---- |
0xb3 |
-- |
---- dot ---- |
0xb4 |
-- |
i32x4.mul |
0xb5 |
-- |
i32x4.min_s |
0xb6 |
-- |
i32x4.min_u |
0xb7 |
-- |
i32x4.max_s |
0xb8 |
-- |
i32x4.max_u |
0xb9 |
-- |
---- avgr_s ---- |
0xba |
-- |
---- avgr_u ---- |
0xbb |
-- |
i64x2 Arith Op |
opcode |
Status |
---- |
0xc0 |
-- |
i64x2.neg |
0xc1 |
-- |
---- |
0xc2 |
-- |
---- |
0xc3 |
-- |
---- |
0xc4 |
-- |
---- |
0xc5 |
-- |
---- |
0xc6 |
-- |
---- |
0xc7 |
-- |
---- |
0xc8 |
-- |
---- |
0xc9 |
-- |
---- |
0xca |
-- |
i64x2.shl |
0xcb |
-- |
i64x2.shr_s |
0xcc |
-- |
i64x2.shr_u |
0xcd |
-- |
i64x2.add |
0xce |
-- |
---- |
0xcf |
-- |
---- |
0xd0 |
-- |
i64x2.sub |
0xd1 |
-- |
---- |
0xd2 |
-- |
---- |
0xd3 |
-- |
---- |
0xd4 |
-- |
i64x2.mul |
0xd5 |
-- |
---- |
0xd6 |
-- |
---- |
0xd7 |
-- |
---- |
0xd8 |
-- |
---- |
0xd9 |
-- |
---- |
0xda |
-- |
---- |
0xdb |
-- |
f32x4 Op |
opcode |
Status |
f32x4.abs |
0xe0 |
-- |
f32x4.neg |
0xe1 |
-- |
---- round ---- |
0xe2 |
-- |
f32x4.sqrt |
0xe3 |
-- |
f32x4.add |
0xe4 |
-- |
f32x4.sub |
0xe5 |
-- |
f32x4.mul |
0xe6 |
-- |
f32x4.div |
0xe7 |
-- |
f32x4.min |
0xe8 |
-- |
f32x4.max |
0xe9 |
-- |
f32x4.pmin |
0xea |
-- |
f32x4.pmax |
0xeb |
-- |
f64x2 Op |
opcode |
Status |
f64x2.abs |
0xec |
-- |
f64x2.neg |
0xed |
-- |
---- round ---- |
0xee |
-- |
f64x2.sqrt |
0xef |
-- |
f64x2.add |
0xf0 |
-- |
f64x2.sub |
0xf1 |
-- |
f64x2.mul |
0xf2 |
-- |
f64x2.div |
0xf3 |
-- |
f64x2.min |
0xf4 |
-- |
f64x2.max |
0xf5 |
-- |
f64x2.pmin |
0xf6 |
-- |
f64x2.pmax |
0xf7 |
-- |
Conversion Op |
opcode |
Status |
i32x4.trunc_sat_f32x4_s |
0xf8 |
-- |
i32x4.trunc_sat_f32x4_u |
0xf9 |
-- |
f32x4.convert_i32x4_s |
0xfa |
-- |
f32x4.convert_i32x4_u |
0xfb |
-- |
jlb6740 edited Issue #2272:
Status: Currently Not Valid (Initial Status WIP)
Last Update: 10/8/2020
https://gist.github.com/jlb6740/0a495404f6b3cc901e1b8e5ae8148020
Memory instruction |
Opcode |
Status |
v128.load |
0x00 |
:+1: |
v128.load8x8_s |
0x01 |
:+1: |
v128.load8x8_u |
0x02 |
:+1: |
v128.load16x4_s |
0x03 |
:+1: |
v128.load16x4_u |
0x04 |
:+1: |
v128.load32x2_s |
0x05 |
:+1: |
v128.load32x2_u |
0x06 |
:+1: |
v128.load8_splat |
0x07 |
:+1: |
v128.load16_splat |
0x08 |
:+1: |
v128.load32_splat |
0x09 |
:+1: |
v128.load64_splat |
0x0a |
:+1: |
v128.store |
0x0b |
:+1: |
Basic operation |
Opcode |
Status |
v128.const |
0x0c |
-- |
i8x16.shuffle |
0x0d |
-- |
i8x16.swizzle |
0x0e |
-- |
Splat operation |
Opcode |
Status |
i8x16.splat |
0x0f |
-- |
i16x8.splat |
0x10 |
-- |
i32x4.splat |
0x11 |
-- |
i64x2.splat |
0x12 |
-- |
f32x4.splat |
0x13 |
-- |
f64x2.splat |
0x14 |
-- |
Lane operation |
Opcode |
Status |
i8x16.extract_lane_s |
0x15 |
-- |
i8x16.extract_lane_u |
0x16 |
-- |
i8x16.replace_lane |
0x17 |
-- |
i16x8.extract_lane_s |
0x18 |
-- |
i16x8.extract_lane_u |
0x19 |
-- |
i16x8.replace_lane |
0x1a |
-- |
i32x4.extract_lane |
0x1b |
-- |
i32x4.replace_lane |
0x1c |
-- |
i64x2.extract_lane |
0x1d |
-- |
i64x2.replace_lane |
0x1e |
-- |
f32x4.extract_lane |
0x1f |
-- |
f32x4.replace_lane |
0x20 |
-- |
f64x2.extract_lane |
0x21 |
-- |
f64x2.replace_lane |
0x22 |
-- |
Integer Cmp |
Opcode |
Status |
i8x16.eq |
0x23 |
-- |
i8x16.ne |
0x24 |
-- |
i8x16.lt_s |
0x25 |
-- |
i8x16.lt_u |
0x26 |
-- |
i8x16.gt_s |
0x27 |
-- |
i8x16.gt_u |
0x28 |
-- |
i8x16.le_s |
0x29 |
-- |
i8x16.le_u |
0x2a |
-- |
i8x16.ge_s |
0x2b |
-- |
i8x16.ge_u |
0x2c |
-- |
i16x8.eq |
0x2d |
-- |
i16x8.ne |
0x2e |
-- |
i16x8.lt_s |
0x2f |
-- |
i16x8.lt_u |
0x30 |
-- |
i16x8.gt_s |
0x31 |
-- |
i16x8.gt_u |
0x32 |
-- |
i16x8.le_s |
0x33 |
-- |
i16x8.le_u |
0x34 |
-- |
i16x8.ge_s |
0x35 |
-- |
i16x8.ge_u |
0x36 |
-- |
i32x4.eq |
0x37 |
-- |
i32x4.ne |
0x38 |
-- |
i32x4.lt_s |
0x39 |
-- |
i32x4.lt_u |
0x3a |
-- |
i32x4.gt_s |
0x3b |
-- |
i32x4.gt_u |
0x3c |
-- |
i32x4.le_s |
0x3d |
-- |
i32x4.le_u |
0x3e |
-- |
i32x4.ge_s |
0x3f |
-- |
i32x4.ge_u |
0x40 |
-- |
v128 Op |
Opcode |
Status |
v128.not |
0x4d |
-- |
v128.and |
0x4e |
-- |
v128.andnot |
0x4f |
-- |
v128.or |
0x50 |
-- |
v128.xor |
0x51 |
-- |
v128.bitselect |
0x52 |
-- |
i8x16 Arith Op |
Opcode |
-- |
i8x16.abs |
0x60 |
-- |
i8x16.neg |
0x61 |
-- |
i8x16.any_true |
0x62 |
-- |
i8x16.all_true |
0x63 |
-- |
i8x16.bitmask |
0x64 |
-- |
i8x16.narrow_i16x8_s |
0x65 |
-- |
i8x16.narrow_i16x8_u |
0x66 |
-- |
---- widen ---- |
0x67 |
-- |
---- widen ---- |
0x68 |
-- |
---- widen ---- |
0x69 |
-- |
---- widen ---- |
0x6a |
-- |
i8x16.shl |
0x6b |
-- |
i8x16.shr_s |
0x6c |
-- |
i8x16.shr_u |
0x6d |
-- |
i8x16.add |
0x6e |
-- |
i8x16.add_sat_s |
0x6f |
-- |
i8x16.add_sat_u |
0x70 |
-- |
i8x16.sub |
0x71 |
-- |
i8x16.sub_sat_s |
0x72 |
-- |
i8x16.sub_sat_u |
0x73 |
-- |
---- dot ---- |
0x74 |
-- |
---- mul ---- |
0x75 |
-- |
i8x16.min_s |
0x76 |
-- |
i8x16.min_u |
0x77 |
-- |
i8x16.max_s |
0x78 |
-- |
i8x16.max_u |
0x79 |
-- |
---- avgr_s ---- |
0x7a |
-- |
i8x16.avgr_u |
0x7b |
-- |
i16x8 Arith Op |
Opcode |
-- |
i16x8.abs |
0x80 |
-- |
i16x8.neg |
0x81 |
-- |
i16x8.any_true |
0x82 |
-- |
i16x8.all_true |
0x83 |
-- |
i16x8.bitmask |
0x84 |
-- |
i16x8.narrow_i32x4_s |
0x85 |
-- |
i16x8.narrow_i32x4_u |
0x86 |
-- |
i16x8.widen_low_i8x16_s |
0x87 |
-- |
i16x8.widen_high_i8x16_s |
0x88 |
-- |
i16x8.widen_low_i8x16_u |
0x89 |
-- |
i16x8.widen_high_i8x16_u |
0x8a |
-- |
i16x8.shl |
0x8b |
-- |
i16x8.shr_s |
0x8c |
-- |
i16x8.shr_u |
0x8d |
-- |
i16x8.add |
0x8e |
-- |
i16x8.add_sat_s |
0x8f |
-- |
i16x8.add_sat_u |
0x90 |
-- |
i16x8.sub |
0x91 |
-- |
i16x8.sub_sat_s |
0x92 |
-- |
i16x8.sub_sat_u |
0x93 |
-- |
---- dot ---- |
0x94 |
-- |
i16x8.mul |
0x95 |
-- |
i16x8.min_s |
0x96 |
-- |
i16x8.min_u |
0x97 |
-- |
i16x8.max_s |
0x98 |
-- |
i16x8.max_u |
0x99 |
-- |
---- avgr_s ---- |
0x9a |
-- |
i16x8.avgr_u |
0x9b |
-- |
i32x4 Arith Op |
Opcode |
Status |
i32x4.abs |
0xa0 |
-- |
i32x4.neg |
0xa1 |
-- |
i32x4.any_true |
0xa2 |
-- |
i32x4.all_true |
0xa3 |
-- |
i32x4.bitmask |
0xa4 |
-- |
---- narrow ---- |
0xa5 |
-- |
---- narrow ---- |
0xa6 |
-- |
i32x4.widen_low_i16x8_s |
0xa7 |
-- |
i32x4.widen_high_i16x8_s |
0xa8 |
-- |
i32x4.widen_low_i16x8_u |
0xa9 |
-- |
i32x4.widen_high_i16x8_u |
0xaa |
-- |
i32x4.shl |
0xab |
-- |
i32x4.shr_s |
0xac |
-- |
i32x4.shr_u |
0xad |
-- |
i32x4.add |
0xae |
-- |
---- add_sat ---- |
0xaf |
-- |
---- add_sat ---- |
0xb0 |
-- |
i32x4.sub |
0xb1 |
-- |
---- sub_sat ---- |
0xb2 |
-- |
---- sub_sat ---- |
0xb3 |
-- |
---- dot ---- |
0xb4 |
-- |
i32x4.mul |
0xb5 |
-- |
i32x4.min_s |
0xb6 |
-- |
i32x4.min_u |
0xb7 |
-- |
i32x4.max_s |
0xb8 |
-- |
i32x4.max_u |
0xb9 |
-- |
---- avgr_s ---- |
0xba |
-- |
---- avgr_u ---- |
0xbb |
-- |
i64x2 Arith Op |
Opcode |
Status |
---- |
0xc0 |
-- |
i64x2.neg |
0xc1 |
-- |
---- |
0xc2 |
-- |
---- |
0xc3 |
-- |
---- |
0xc4 |
-- |
---- |
0xc5 |
-- |
---- |
0xc6 |
-- |
---- |
0xc7 |
-- |
---- |
0xc8 |
-- |
---- |
0xc9 |
-- |
---- |
0xca |
-- |
i64x2.shl |
0xcb |
-- |
i64x2.shr_s |
0xcc |
-- |
i64x2.shr_u |
0xcd |
-- |
i64x2.add |
0xce |
-- |
---- |
0xcf |
-- |
---- |
0xd0 |
-- |
i64x2.sub |
0xd1 |
-- |
---- |
0xd2 |
-- |
---- |
0xd3 |
-- |
---- |
0xd4 |
-- |
i64x2.mul |
0xd5 |
-- |
---- |
0xd6 |
-- |
---- |
0xd7 |
-- |
---- |
0xd8 |
-- |
---- |
0xd9 |
-- |
---- |
0xda |
-- |
---- |
0xdb |
-- |
f32x4 Op |
Opcode |
Status |
f32x4.abs |
0xe0 |
-- |
f32x4.neg |
0xe1 |
-- |
---- round ---- |
0xe2 |
-- |
f32x4.sqrt |
0xe3 |
-- |
f32x4.add |
0xe4 |
-- |
f32x4.sub |
0xe5 |
-- |
f32x4.mul |
0xe6 |
-- |
f32x4.div |
0xe7 |
-- |
f32x4.min |
0xe8 |
-- |
f32x4.max |
0xe9 |
-- |
f32x4.pmin |
0xea |
-- |
f32x4.pmax |
0xeb |
-- |
f64x2 Op |
Opcode |
Status |
f64x2.abs |
0xec |
-- |
f64x2.neg |
0xed |
-- |
---- round ---- |
0xee |
-- |
f64x2.sqrt |
0xef |
-- |
f64x2.add |
0xf0 |
-- |
f64x2.sub |
0xf1 |
-- |
f64x2.mul |
0xf2 |
-- |
f64x2.div |
0xf3 |
-- |
f64x2.min |
0xf4 |
-- |
f64x2.max |
0xf5 |
-- |
f64x2.pmin |
0xf6 |
-- |
f64x2.pmax |
0xf7 |
-- |
Conversion Op |
Opcode |
Status |
i32x4.trunc_sat_f32x4_s |
0xf8 |
-- |
i32x4.trunc_sat_f32x4_u |
0xf9 |
-- |
f32x4.convert_i32x4_s |
0xfa |
-- |
f32x4.convert_i32x4_u |
0xfb |
-- |
jlb6740 edited Issue #2272:
Status: Currently Not Valid (Initial Status WIP)
Last Update: 10/8/2020
https://gist.github.com/jlb6740/0a495404f6b3cc901e1b8e5ae8148020
Loads |
Opcode |
Status |
v128.load |
0x00 |
:+1: |
v128.load8x8_s |
0x01 |
:+1: |
v128.load8x8_u |
0x02 |
:+1: |
v128.load16x4_s |
0x03 |
:+1: |
v128.load16x4_u |
0x04 |
:+1: |
v128.load32x2_s |
0x05 |
:+1: |
v128.load32x2_u |
0x06 |
:+1: |
v128.load8_splat |
0x07 |
:+1: |
v128.load16_splat |
0x08 |
:+1: |
v128.load32_splat |
0x09 |
:+1: |
v128.load64_splat |
0x0a |
:+1: |
Basic operation |
Opcode |
Status |
v128.const |
0x0c |
-- |
i8x16.shuffle |
0x0d |
-- |
i8x16.swizzle |
0x0e |
-- |
Splat operation |
Opcode |
Status |
i8x16.splat |
0x0f |
-- |
i16x8.splat |
0x10 |
-- |
i32x4.splat |
0x11 |
-- |
i64x2.splat |
0x12 |
-- |
f32x4.splat |
0x13 |
-- |
f64x2.splat |
0x14 |
-- |
Lane operation |
Opcode |
Status |
i8x16.extract_lane_s |
0x15 |
-- |
i8x16.extract_lane_u |
0x16 |
-- |
i8x16.replace_lane |
0x17 |
-- |
i16x8.extract_lane_s |
0x18 |
-- |
i16x8.extract_lane_u |
0x19 |
-- |
i16x8.replace_lane |
0x1a |
-- |
i32x4.extract_lane |
0x1b |
-- |
i32x4.replace_lane |
0x1c |
-- |
i64x2.extract_lane |
0x1d |
-- |
i64x2.replace_lane |
0x1e |
-- |
f32x4.extract_lane |
0x1f |
-- |
f32x4.replace_lane |
0x20 |
-- |
f64x2.extract_lane |
0x21 |
-- |
f64x2.replace_lane |
0x22 |
-- |
Integer Cmp |
Opcode |
Status |
i8x16.eq |
0x23 |
-- |
i8x16.ne |
0x24 |
-- |
i8x16.lt_s |
0x25 |
-- |
i8x16.lt_u |
0x26 |
-- |
i8x16.gt_s |
0x27 |
-- |
i8x16.gt_u |
0x28 |
-- |
i8x16.le_s |
0x29 |
-- |
i8x16.le_u |
0x2a |
-- |
i8x16.ge_s |
0x2b |
-- |
i8x16.ge_u |
0x2c |
-- |
i16x8.eq |
0x2d |
-- |
i16x8.ne |
0x2e |
-- |
i16x8.lt_s |
0x2f |
-- |
i16x8.lt_u |
0x30 |
-- |
i16x8.gt_s |
0x31 |
-- |
i16x8.gt_u |
0x32 |
-- |
i16x8.le_s |
0x33 |
-- |
i16x8.le_u |
0x34 |
-- |
i16x8.ge_s |
0x35 |
-- |
i16x8.ge_u |
0x36 |
-- |
i32x4.eq |
0x37 |
-- |
i32x4.ne |
0x38 |
-- |
i32x4.lt_s |
0x39 |
-- |
i32x4.lt_u |
0x3a |
-- |
i32x4.gt_s |
0x3b |
-- |
i32x4.gt_u |
0x3c |
-- |
i32x4.le_s |
0x3d |
-- |
i32x4.le_u |
0x3e |
-- |
i32x4.ge_s |
0x3f |
-- |
i32x4.ge_u |
0x40 |
-- |
v128 Op |
Opcode |
Status |
v128.not |
0x4d |
-- |
v128.and |
0x4e |
-- |
v128.andnot |
0x4f |
-- |
v128.or |
0x50 |
-- |
v128.xor |
0x51 |
-- |
v128.bitselect |
0x52 |
-- |
i8x16 Arith Op |
Opcode |
-- |
i8x16.abs |
0x60 |
-- |
i8x16.neg |
0x61 |
-- |
i8x16.any_true |
0x62 |
-- |
i8x16.all_true |
0x63 |
-- |
i8x16.bitmask |
0x64 |
-- |
i8x16.narrow_i16x8_s |
0x65 |
-- |
i8x16.narrow_i16x8_u |
0x66 |
-- |
---- widen ---- |
0x67 |
-- |
---- widen ---- |
0x68 |
-- |
---- widen ---- |
0x69 |
-- |
---- widen ---- |
0x6a |
-- |
i8x16.shl |
0x6b |
-- |
i8x16.shr_s |
0x6c |
-- |
i8x16.shr_u |
0x6d |
-- |
i8x16.add |
0x6e |
-- |
i8x16.add_sat_s |
0x6f |
-- |
i8x16.add_sat_u |
0x70 |
-- |
i8x16.sub |
0x71 |
-- |
i8x16.sub_sat_s |
0x72 |
-- |
i8x16.sub_sat_u |
0x73 |
-- |
---- dot ---- |
0x74 |
-- |
---- mul ---- |
0x75 |
-- |
i8x16.min_s |
0x76 |
-- |
i8x16.min_u |
0x77 |
-- |
i8x16.max_s |
0x78 |
-- |
i8x16.max_u |
0x79 |
-- |
---- avgr_s ---- |
0x7a |
-- |
i8x16.avgr_u |
0x7b |
-- |
i16x8 Arith Op |
Opcode |
Status |
i16x8.abs |
0x80 |
-- |
i16x8.neg |
0x81 |
-- |
i16x8.any_true |
0x82 |
-- |
i16x8.all_true |
0x83 |
-- |
i16x8.bitmask |
0x84 |
-- |
i16x8.narrow_i32x4_s |
0x85 |
-- |
i16x8.narrow_i32x4_u |
0x86 |
-- |
i16x8.widen_low_i8x16_s |
0x87 |
-- |
i16x8.widen_high_i8x16_s |
0x88 |
-- |
i16x8.widen_low_i8x16_u |
0x89 |
-- |
i16x8.widen_high_i8x16_u |
0x8a |
-- |
i16x8.shl |
0x8b |
-- |
i16x8.shr_s |
0x8c |
-- |
i16x8.shr_u |
0x8d |
-- |
i16x8.add |
0x8e |
-- |
i16x8.add_sat_s |
0x8f |
-- |
i16x8.add_sat_u |
0x90 |
-- |
i16x8.sub |
0x91 |
-- |
i16x8.sub_sat_s |
0x92 |
-- |
i16x8.sub_sat_u |
0x93 |
-- |
---- dot ---- |
0x94 |
-- |
i16x8.mul |
0x95 |
-- |
i16x8.min_s |
0x96 |
-- |
i16x8.min_u |
0x97 |
-- |
i16x8.max_s |
0x98 |
-- |
i16x8.max_u |
0x99 |
-- |
---- avgr_s ---- |
0x9a |
-- |
i16x8.avgr_u |
0x9b |
-- |
i32x4 Arith Op |
Opcode |
Status |
i32x4.abs |
0xa0 |
-- |
i32x4.neg |
0xa1 |
-- |
i32x4.any_true |
0xa2 |
-- |
i32x4.all_true |
0xa3 |
-- |
i32x4.bitmask |
0xa4 |
-- |
---- narrow ---- |
0xa5 |
-- |
---- narrow ---- |
0xa6 |
-- |
i32x4.widen_low_i16x8_s |
0xa7 |
-- |
i32x4.widen_high_i16x8_s |
0xa8 |
-- |
i32x4.widen_low_i16x8_u |
0xa9 |
-- |
i32x4.widen_high_i16x8_u |
0xaa |
-- |
i32x4.shl |
0xab |
-- |
i32x4.shr_s |
0xac |
-- |
i32x4.shr_u |
0xad |
-- |
i32x4.add |
0xae |
-- |
---- add_sat ---- |
0xaf |
-- |
---- add_sat ---- |
0xb0 |
-- |
i32x4.sub |
0xb1 |
-- |
---- sub_sat ---- |
0xb2 |
-- |
---- sub_sat ---- |
0xb3 |
-- |
---- dot ---- |
0xb4 |
-- |
i32x4.mul |
0xb5 |
-- |
i32x4.min_s |
0xb6 |
-- |
i32x4.min_u |
0xb7 |
-- |
i32x4.max_s |
0xb8 |
-- |
i32x4.max_u |
0xb9 |
-- |
---- avgr_s ---- |
0xba |
-- |
---- avgr_u ---- |
0xbb |
-- |
i64x2 Arith Op |
Opcode |
Status |
---- |
0xc0 |
-- |
i64x2.neg |
0xc1 |
-- |
---- |
0xc2 |
-- |
---- |
0xc3 |
-- |
---- |
0xc4 |
-- |
---- |
0xc5 |
-- |
---- |
0xc6 |
-- |
---- |
0xc7 |
-- |
---- |
0xc8 |
-- |
---- |
0xc9 |
-- |
---- |
0xca |
-- |
i64x2.shl |
0xcb |
-- |
i64x2.shr_s |
0xcc |
-- |
i64x2.shr_u |
0xcd |
-- |
i64x2.add |
0xce |
-- |
---- |
0xcf |
-- |
---- |
0xd0 |
-- |
i64x2.sub |
0xd1 |
-- |
---- |
0xd2 |
-- |
---- |
0xd3 |
-- |
---- |
0xd4 |
-- |
i64x2.mul |
0xd5 |
-- |
---- |
0xd6 |
-- |
---- |
0xd7 |
-- |
---- |
0xd8 |
-- |
---- |
0xd9 |
-- |
---- |
0xda |
-- |
---- |
0xdb |
-- |
f32x4 Op |
Opcode |
Status |
f32x4.abs |
0xe0 |
-- |
f32x4.neg |
0xe1 |
-- |
---- round ---- |
0xe2 |
-- |
f32x4.sqrt |
0xe3 |
-- |
f32x4.add |
0xe4 |
-- |
f32x4.sub |
0xe5 |
-- |
f32x4.mul |
0xe6 |
-- |
f32x4.div |
0xe7 |
-- |
f32x4.min |
0xe8 |
-- |
f32x4.max |
0xe9 |
-- |
f32x4.pmin |
0xea |
-- |
f32x4.pmax |
0xeb |
-- |
f64x2 Op |
Opcode |
Status |
f64x2.abs |
0xec |
-- |
f64x2.neg |
0xed |
-- |
---- round ---- |
0xee |
-- |
f64x2.sqrt |
0xef |
-- |
f64x2.add |
0xf0 |
-- |
f64x2.sub |
0xf1 |
-- |
f64x2.mul |
0xf2 |
-- |
f64x2.div |
0xf3 |
-- |
f64x2.min |
0xf4 |
-- |
f64x2.max |
0xf5 |
-- |
f64x2.pmin |
0xf6 |
-- |
f64x2.pmax |
0xf7 |
-- |
Conversion Op |
Opcode |
Status |
i32x4.trunc_sat_f32x4_s |
0xf8 |
-- |
i32x4.trunc_sat_f32x4_u |
0xf9 |
-- |
f32x4.convert_i32x4_s |
0xfa |
-- |
f32x4.convert_i32x4_u |
0xfb |
-- |
jlb6740 edited Issue #2272:
Status: Currently Not Valid (Initial Status WIP)
Last Update: 10/8/2020
https://gist.github.com/jlb6740/0a495404f6b3cc901e1b8e5ae8148020
Loads |
Opcode |
Status |
v128.load |
0x00 |
:+1: |
v128.load8x8_s |
0x01 |
:+1: |
v128.load8x8_u |
0x02 |
:+1: |
v128.load16x4_s |
0x03 |
:+1: |
v128.load16x4_u |
0x04 |
:+1: |
v128.load32x2_s |
0x05 |
:+1: |
v128.load32x2_u |
0x06 |
:+1: |
v128.load8_splat |
0x07 |
:+1: |
v128.load16_splat |
0x08 |
:+1: |
v128.load32_splat |
0x09 |
:+1: |
v128.load64_splat |
0x0a |
:+1: |
Basic operation |
Opcode |
Status |
v128.const |
0x0c |
:+1: |
i8x16.shuffle |
0x0d |
:+1: |
i8x16.swizzle |
0x0e |
:+1: |
Splat operation |
Opcode |
Status |
i8x16.splat |
0x0f |
-- |
i16x8.splat |
0x10 |
-- |
i32x4.splat |
0x11 |
-- |
i64x2.splat |
0x12 |
-- |
f32x4.splat |
0x13 |
-- |
f64x2.splat |
0x14 |
-- |
Lane operation |
Opcode |
Status |
i8x16.extract_lane_s |
0x15 |
-- |
i8x16.extract_lane_u |
0x16 |
-- |
i8x16.replace_lane |
0x17 |
-- |
i16x8.extract_lane_s |
0x18 |
-- |
i16x8.extract_lane_u |
0x19 |
-- |
i16x8.replace_lane |
0x1a |
-- |
i32x4.extract_lane |
0x1b |
-- |
i32x4.replace_lane |
0x1c |
-- |
i64x2.extract_lane |
0x1d |
-- |
i64x2.replace_lane |
0x1e |
-- |
f32x4.extract_lane |
0x1f |
-- |
f32x4.replace_lane |
0x20 |
-- |
f64x2.extract_lane |
0x21 |
-- |
f64x2.replace_lane |
0x22 |
-- |
Integer Cmp |
Opcode |
Status |
i8x16.eq |
0x23 |
-- |
i8x16.ne |
0x24 |
-- |
i8x16.lt_s |
0x25 |
-- |
i8x16.lt_u |
0x26 |
-- |
i8x16.gt_s |
0x27 |
-- |
i8x16.gt_u |
0x28 |
-- |
i8x16.le_s |
0x29 |
-- |
i8x16.le_u |
0x2a |
-- |
i8x16.ge_s |
0x2b |
-- |
i8x16.ge_u |
0x2c |
-- |
i16x8.eq |
0x2d |
-- |
i16x8.ne |
0x2e |
-- |
i16x8.lt_s |
0x2f |
-- |
i16x8.lt_u |
0x30 |
-- |
i16x8.gt_s |
0x31 |
-- |
i16x8.gt_u |
0x32 |
-- |
i16x8.le_s |
0x33 |
-- |
i16x8.le_u |
0x34 |
-- |
i16x8.ge_s |
0x35 |
-- |
i16x8.ge_u |
0x36 |
-- |
i32x4.eq |
0x37 |
-- |
i32x4.ne |
0x38 |
-- |
i32x4.lt_s |
0x39 |
-- |
i32x4.lt_u |
0x3a |
-- |
i32x4.gt_s |
0x3b |
-- |
i32x4.gt_u |
0x3c |
-- |
i32x4.le_s |
0x3d |
-- |
i32x4.le_u |
0x3e |
-- |
i32x4.ge_s |
0x3f |
-- |
i32x4.ge_u |
0x40 |
-- |
v128 Op |
Opcode |
Status |
v128.not |
0x4d |
-- |
v128.and |
0x4e |
-- |
v128.andnot |
0x4f |
-- |
v128.or |
0x50 |
-- |
v128.xor |
0x51 |
-- |
v128.bitselect |
0x52 |
-- |
i8x16 Arith Op |
Opcode |
-- |
i8x16.abs |
0x60 |
-- |
i8x16.neg |
0x61 |
-- |
i8x16.any_true |
0x62 |
-- |
i8x16.all_true |
0x63 |
-- |
i8x16.bitmask |
0x64 |
-- |
i8x16.narrow_i16x8_s |
0x65 |
-- |
i8x16.narrow_i16x8_u |
0x66 |
-- |
---- widen ---- |
0x67 |
-- |
---- widen ---- |
0x68 |
-- |
---- widen ---- |
0x69 |
-- |
---- widen ---- |
0x6a |
-- |
i8x16.shl |
0x6b |
-- |
i8x16.shr_s |
0x6c |
-- |
i8x16.shr_u |
0x6d |
-- |
i8x16.add |
0x6e |
-- |
i8x16.add_sat_s |
0x6f |
-- |
i8x16.add_sat_u |
0x70 |
-- |
i8x16.sub |
0x71 |
-- |
i8x16.sub_sat_s |
0x72 |
-- |
i8x16.sub_sat_u |
0x73 |
-- |
---- dot ---- |
0x74 |
-- |
---- mul ---- |
0x75 |
-- |
i8x16.min_s |
0x76 |
-- |
i8x16.min_u |
0x77 |
-- |
i8x16.max_s |
0x78 |
-- |
i8x16.max_u |
0x79 |
-- |
---- avgr_s ---- |
0x7a |
-- |
i8x16.avgr_u |
0x7b |
-- |
i16x8 Arith Op |
Opcode |
Status |
i16x8.abs |
0x80 |
-- |
i16x8.neg |
0x81 |
-- |
i16x8.any_true |
0x82 |
-- |
i16x8.all_true |
0x83 |
-- |
i16x8.bitmask |
0x84 |
-- |
i16x8.narrow_i32x4_s |
0x85 |
-- |
i16x8.narrow_i32x4_u |
0x86 |
-- |
i16x8.widen_low_i8x16_s |
0x87 |
-- |
i16x8.widen_high_i8x16_s |
0x88 |
-- |
i16x8.widen_low_i8x16_u |
0x89 |
-- |
i16x8.widen_high_i8x16_u |
0x8a |
-- |
i16x8.shl |
0x8b |
-- |
i16x8.shr_s |
0x8c |
-- |
i16x8.shr_u |
0x8d |
-- |
i16x8.add |
0x8e |
-- |
i16x8.add_sat_s |
0x8f |
-- |
i16x8.add_sat_u |
0x90 |
-- |
i16x8.sub |
0x91 |
-- |
i16x8.sub_sat_s |
0x92 |
-- |
i16x8.sub_sat_u |
0x93 |
-- |
---- dot ---- |
0x94 |
-- |
i16x8.mul |
0x95 |
-- |
i16x8.min_s |
0x96 |
-- |
i16x8.min_u |
0x97 |
-- |
i16x8.max_s |
0x98 |
-- |
i16x8.max_u |
0x99 |
-- |
---- avgr_s ---- |
0x9a |
-- |
i16x8.avgr_u |
0x9b |
-- |
i32x4 Arith Op |
Opcode |
Status |
i32x4.abs |
0xa0 |
-- |
i32x4.neg |
0xa1 |
-- |
i32x4.any_true |
0xa2 |
-- |
i32x4.all_true |
0xa3 |
-- |
i32x4.bitmask |
0xa4 |
-- |
---- narrow ---- |
0xa5 |
-- |
---- narrow ---- |
0xa6 |
-- |
i32x4.widen_low_i16x8_s |
0xa7 |
-- |
i32x4.widen_high_i16x8_s |
0xa8 |
-- |
i32x4.widen_low_i16x8_u |
0xa9 |
-- |
i32x4.widen_high_i16x8_u |
0xaa |
-- |
i32x4.shl |
0xab |
-- |
i32x4.shr_s |
0xac |
-- |
i32x4.shr_u |
0xad |
-- |
i32x4.add |
0xae |
-- |
---- add_sat ---- |
0xaf |
-- |
---- add_sat ---- |
0xb0 |
-- |
i32x4.sub |
0xb1 |
-- |
---- sub_sat ---- |
0xb2 |
-- |
---- sub_sat ---- |
0xb3 |
-- |
---- dot ---- |
0xb4 |
-- |
i32x4.mul |
0xb5 |
-- |
i32x4.min_s |
0xb6 |
-- |
i32x4.min_u |
0xb7 |
-- |
i32x4.max_s |
0xb8 |
-- |
i32x4.max_u |
0xb9 |
-- |
---- avgr_s ---- |
0xba |
-- |
---- avgr_u ---- |
0xbb |
-- |
i64x2 Arith Op |
Opcode |
Status |
---- |
0xc0 |
-- |
i64x2.neg |
0xc1 |
-- |
---- |
0xc2 |
-- |
---- |
0xc3 |
-- |
---- |
0xc4 |
-- |
---- |
0xc5 |
-- |
---- |
0xc6 |
-- |
---- |
0xc7 |
-- |
---- |
0xc8 |
-- |
---- |
0xc9 |
-- |
---- |
0xca |
-- |
i64x2.shl |
0xcb |
-- |
i64x2.shr_s |
0xcc |
-- |
i64x2.shr_u |
0xcd |
-- |
i64x2.add |
0xce |
-- |
---- |
0xcf |
-- |
---- |
0xd0 |
-- |
i64x2.sub |
0xd1 |
-- |
---- |
0xd2 |
-- |
---- |
0xd3 |
-- |
---- |
0xd4 |
-- |
i64x2.mul |
0xd5 |
-- |
---- |
0xd6 |
-- |
---- |
0xd7 |
-- |
---- |
0xd8 |
-- |
---- |
0xd9 |
-- |
---- |
0xda |
-- |
---- |
0xdb |
-- |
f32x4 Op |
Opcode |
Status |
f32x4.abs |
0xe0 |
-- |
f32x4.neg |
0xe1 |
-- |
---- round ---- |
0xe2 |
-- |
f32x4.sqrt |
0xe3 |
-- |
f32x4.add |
0xe4 |
-- |
f32x4.sub |
0xe5 |
-- |
f32x4.mul |
0xe6 |
-- |
f32x4.div |
0xe7 |
-- |
f32x4.min |
0xe8 |
-- |
f32x4.max |
0xe9 |
-- |
f32x4.pmin |
0xea |
-- |
f32x4.pmax |
0xeb |
-- |
f64x2 Op |
Opcode |
Status |
f64x2.abs |
0xec |
-- |
f64x2.neg |
0xed |
-- |
---- round ---- |
0xee |
-- |
f64x2.sqrt |
0xef |
-- |
f64x2.add |
0xf0 |
-- |
f64x2.sub |
0xf1 |
-- |
f64x2.mul |
0xf2 |
-- |
f64x2.div |
0xf3 |
-- |
f64x2.min |
0xf4 |
-- |
f64x2.max |
0xf5 |
-- |
f64x2.pmin |
0xf6 |
-- |
f64x2.pmax |
0xf7 |
-- |
Conversion Op |
Opcode |
Status |
i32x4.trunc_sat_f32x4_s |
0xf8 |
-- |
i32x4.trunc_sat_f32x4_u |
0xf9 |
-- |
f32x4.convert_i32x4_s |
0xfa |
-- |
f32x4.convert_i32x4_u |
0xfb |
-- |
jlb6740 edited Issue #2272:
Status: Currently Not Valid (Initial Status WIP)
Last Update: 10/8/2020
https://gist.github.com/jlb6740/0a495404f6b3cc901e1b8e5ae8148020
Loads |
Opcode |
Status |
v128.load |
0x00 |
:+1: |
v128.load8x8_s |
0x01 |
:+1: |
v128.load8x8_u |
0x02 |
:+1: |
v128.load16x4_s |
0x03 |
:+1: |
v128.load16x4_u |
0x04 |
:+1: |
v128.load32x2_s |
0x05 |
:+1: |
v128.load32x2_u |
0x06 |
:+1: |
v128.load8_splat |
0x07 |
:+1: |
v128.load16_splat |
0x08 |
:+1: |
v128.load32_splat |
0x09 |
:+1: |
v128.load64_splat |
0x0a |
:+1: |
Basic operation |
Opcode |
Status |
v128.const |
0x0c |
:+1: |
i8x16.shuffle |
0x0d |
:+1: |
i8x16.swizzle |
0x0e |
:+1: |
Splat operation |
Opcode |
Status |
i8x16.splat |
0x0f |
:+1: |
i16x8.splat |
0x10 |
:+1: |
i32x4.splat |
0x11 |
:+1: |
i64x2.splat |
0x12 |
:+1: |
f32x4.splat |
0x13 |
:+1: |
f64x2.splat |
0x14 |
:+1: |
Lane operation |
Opcode |
Status |
i8x16.extract_lane_s |
0x15 |
-- |
i8x16.extract_lane_u |
0x16 |
-- |
i8x16.replace_lane |
0x17 |
-- |
i16x8.extract_lane_s |
0x18 |
-- |
i16x8.extract_lane_u |
0x19 |
-- |
i16x8.replace_lane |
0x1a |
-- |
i32x4.extract_lane |
0x1b |
-- |
i32x4.replace_lane |
0x1c |
-- |
i64x2.extract_lane |
0x1d |
-- |
i64x2.replace_lane |
0x1e |
-- |
f32x4.extract_lane |
0x1f |
-- |
f32x4.replace_lane |
0x20 |
-- |
f64x2.extract_lane |
0x21 |
-- |
f64x2.replace_lane |
0x22 |
-- |
Integer Cmp |
Opcode |
Status |
i8x16.eq |
0x23 |
-- |
i8x16.ne |
0x24 |
-- |
i8x16.lt_s |
0x25 |
-- |
i8x16.lt_u |
0x26 |
-- |
i8x16.gt_s |
0x27 |
-- |
i8x16.gt_u |
0x28 |
-- |
i8x16.le_s |
0x29 |
-- |
i8x16.le_u |
0x2a |
-- |
i8x16.ge_s |
0x2b |
-- |
i8x16.ge_u |
0x2c |
-- |
i16x8.eq |
0x2d |
-- |
i16x8.ne |
0x2e |
-- |
i16x8.lt_s |
0x2f |
-- |
i16x8.lt_u |
0x30 |
-- |
i16x8.gt_s |
0x31 |
-- |
i16x8.gt_u |
0x32 |
-- |
i16x8.le_s |
0x33 |
-- |
i16x8.le_u |
0x34 |
-- |
i16x8.ge_s |
0x35 |
-- |
i16x8.ge_u |
0x36 |
-- |
i32x4.eq |
0x37 |
-- |
i32x4.ne |
0x38 |
-- |
i32x4.lt_s |
0x39 |
-- |
i32x4.lt_u |
0x3a |
-- |
i32x4.gt_s |
0x3b |
-- |
i32x4.gt_u |
0x3c |
-- |
i32x4.le_s |
0x3d |
-- |
i32x4.le_u |
0x3e |
-- |
i32x4.ge_s |
0x3f |
-- |
i32x4.ge_u |
0x40 |
-- |
v128 Op |
Opcode |
Status |
v128.not |
0x4d |
-- |
v128.and |
0x4e |
-- |
v128.andnot |
0x4f |
-- |
v128.or |
0x50 |
-- |
v128.xor |
0x51 |
-- |
v128.bitselect |
0x52 |
-- |
i8x16 Arith Op |
Opcode |
-- |
i8x16.abs |
0x60 |
-- |
i8x16.neg |
0x61 |
-- |
i8x16.any_true |
0x62 |
-- |
i8x16.all_true |
0x63 |
-- |
i8x16.bitmask |
0x64 |
-- |
i8x16.narrow_i16x8_s |
0x65 |
-- |
i8x16.narrow_i16x8_u |
0x66 |
-- |
---- widen ---- |
0x67 |
-- |
---- widen ---- |
0x68 |
-- |
---- widen ---- |
0x69 |
-- |
---- widen ---- |
0x6a |
-- |
i8x16.shl |
0x6b |
-- |
i8x16.shr_s |
0x6c |
-- |
i8x16.shr_u |
0x6d |
-- |
i8x16.add |
0x6e |
-- |
i8x16.add_sat_s |
0x6f |
-- |
i8x16.add_sat_u |
0x70 |
-- |
i8x16.sub |
0x71 |
-- |
i8x16.sub_sat_s |
0x72 |
-- |
i8x16.sub_sat_u |
0x73 |
-- |
---- dot ---- |
0x74 |
-- |
---- mul ---- |
0x75 |
-- |
i8x16.min_s |
0x76 |
-- |
i8x16.min_u |
0x77 |
-- |
i8x16.max_s |
0x78 |
-- |
i8x16.max_u |
0x79 |
-- |
---- avgr_s ---- |
0x7a |
-- |
i8x16.avgr_u |
0x7b |
-- |
i16x8 Arith Op |
Opcode |
Status |
i16x8.abs |
0x80 |
-- |
i16x8.neg |
0x81 |
-- |
i16x8.any_true |
0x82 |
-- |
i16x8.all_true |
0x83 |
-- |
i16x8.bitmask |
0x84 |
-- |
i16x8.narrow_i32x4_s |
0x85 |
-- |
i16x8.narrow_i32x4_u |
0x86 |
-- |
i16x8.widen_low_i8x16_s |
0x87 |
-- |
i16x8.widen_high_i8x16_s |
0x88 |
-- |
i16x8.widen_low_i8x16_u |
0x89 |
-- |
i16x8.widen_high_i8x16_u |
0x8a |
-- |
i16x8.shl |
0x8b |
-- |
i16x8.shr_s |
0x8c |
-- |
i16x8.shr_u |
0x8d |
-- |
i16x8.add |
0x8e |
-- |
i16x8.add_sat_s |
0x8f |
-- |
i16x8.add_sat_u |
0x90 |
-- |
i16x8.sub |
0x91 |
-- |
i16x8.sub_sat_s |
0x92 |
-- |
i16x8.sub_sat_u |
0x93 |
-- |
---- dot ---- |
0x94 |
-- |
i16x8.mul |
0x95 |
-- |
i16x8.min_s |
0x96 |
-- |
i16x8.min_u |
0x97 |
-- |
i16x8.max_s |
0x98 |
-- |
i16x8.max_u |
0x99 |
-- |
---- avgr_s ---- |
0x9a |
-- |
i16x8.avgr_u |
0x9b |
-- |
i32x4 Arith Op |
Opcode |
Status |
i32x4.abs |
0xa0 |
-- |
i32x4.neg |
0xa1 |
-- |
i32x4.any_true |
0xa2 |
-- |
i32x4.all_true |
0xa3 |
-- |
i32x4.bitmask |
0xa4 |
-- |
---- narrow ---- |
0xa5 |
-- |
---- narrow ---- |
0xa6 |
-- |
i32x4.widen_low_i16x8_s |
0xa7 |
-- |
i32x4.widen_high_i16x8_s |
0xa8 |
-- |
i32x4.widen_low_i16x8_u |
0xa9 |
-- |
i32x4.widen_high_i16x8_u |
0xaa |
-- |
i32x4.shl |
0xab |
-- |
i32x4.shr_s |
0xac |
-- |
i32x4.shr_u |
0xad |
-- |
i32x4.add |
0xae |
-- |
---- add_sat ---- |
0xaf |
-- |
---- add_sat ---- |
0xb0 |
-- |
i32x4.sub |
0xb1 |
-- |
---- sub_sat ---- |
0xb2 |
-- |
---- sub_sat ---- |
0xb3 |
-- |
---- dot ---- |
0xb4 |
-- |
i32x4.mul |
0xb5 |
-- |
i32x4.min_s |
0xb6 |
-- |
i32x4.min_u |
0xb7 |
-- |
i32x4.max_s |
0xb8 |
-- |
i32x4.max_u |
0xb9 |
-- |
---- avgr_s ---- |
0xba |
-- |
---- avgr_u ---- |
0xbb |
-- |
i64x2 Arith Op |
Opcode |
Status |
---- |
0xc0 |
-- |
i64x2.neg |
0xc1 |
-- |
---- |
0xc2 |
-- |
---- |
0xc3 |
-- |
---- |
0xc4 |
-- |
---- |
0xc5 |
-- |
---- |
0xc6 |
-- |
---- |
0xc7 |
-- |
---- |
0xc8 |
-- |
---- |
0xc9 |
-- |
---- |
0xca |
-- |
i64x2.shl |
0xcb |
-- |
i64x2.shr_s |
0xcc |
-- |
i64x2.shr_u |
0xcd |
-- |
i64x2.add |
0xce |
-- |
---- |
0xcf |
-- |
---- |
0xd0 |
-- |
i64x2.sub |
0xd1 |
-- |
---- |
0xd2 |
-- |
---- |
0xd3 |
-- |
---- |
0xd4 |
-- |
i64x2.mul |
0xd5 |
-- |
---- |
0xd6 |
-- |
---- |
0xd7 |
-- |
---- |
0xd8 |
-- |
---- |
0xd9 |
-- |
---- |
0xda |
-- |
---- |
0xdb |
-- |
f32x4 Op |
Opcode |
Status |
f32x4.abs |
0xe0 |
-- |
f32x4.neg |
0xe1 |
-- |
---- round ---- |
0xe2 |
-- |
f32x4.sqrt |
0xe3 |
-- |
f32x4.add |
0xe4 |
-- |
f32x4.sub |
0xe5 |
-- |
f32x4.mul |
0xe6 |
-- |
f32x4.div |
0xe7 |
-- |
f32x4.min |
0xe8 |
-- |
f32x4.max |
0xe9 |
-- |
f32x4.pmin |
0xea |
-- |
f32x4.pmax |
0xeb |
-- |
f64x2 Op |
Opcode |
Status |
f64x2.abs |
0xec |
-- |
f64x2.neg |
0xed |
-- |
---- round ---- |
0xee |
-- |
f64x2.sqrt |
0xef |
-- |
f64x2.add |
0xf0 |
-- |
f64x2.sub |
0xf1 |
-- |
f64x2.mul |
0xf2 |
-- |
f64x2.div |
0xf3 |
-- |
f64x2.min |
0xf4 |
-- |
f64x2.max |
0xf5 |
-- |
f64x2.pmin |
0xf6 |
-- |
f64x2.pmax |
0xf7 |
-- |
Conversion Op |
Opcode |
Status |
i32x4.trunc_sat_f32x4_s |
0xf8 |
-- |
i32x4.trunc_sat_f32x4_u |
0xf9 |
-- |
f32x4.convert_i32x4_s |
0xfa |
-- |
f32x4.convert_i32x4_u |
0xfb |
-- |
jlb6740 edited Issue #2272:
Status: Currently Not Valid (Initial Status WIP)
Last Update: 10/8/2020
https://gist.github.com/jlb6740/0a495404f6b3cc901e1b8e5ae8148020
Loads |
Opcode |
Status |
v128.load |
0x00 |
:+1: |
v128.load8x8_s |
0x01 |
:+1: |
v128.load8x8_u |
0x02 |
:+1: |
v128.load16x4_s |
0x03 |
:+1: |
v128.load16x4_u |
0x04 |
:+1: |
v128.load32x2_s |
0x05 |
:+1: |
v128.load32x2_u |
0x06 |
:+1: |
v128.load8_splat |
0x07 |
:+1: |
v128.load16_splat |
0x08 |
:+1: |
v128.load32_splat |
0x09 |
:+1: |
v128.load64_splat |
0x0a |
:+1: |
Basic operation |
Opcode |
Status |
v128.const |
0x0c |
:+1: |
i8x16.shuffle |
0x0d |
:+1: |
i8x16.swizzle |
0x0e |
:+1: |
Splat operation |
Opcode |
Status |
i8x16.splat |
0x0f |
:+1: |
i16x8.splat |
0x10 |
:+1: |
i32x4.splat |
0x11 |
:+1: |
i64x2.splat |
0x12 |
:+1: |
f32x4.splat |
0x13 |
:+1: |
f64x2.splat |
0x14 |
:+1: |
Lane operation |
Opcode |
Status |
i8x16.extract_lane_s |
0x15 |
:+1: |
i8x16.extract_lane_u |
0x16 |
:+1: |
i8x16.replace_lane |
0x17 |
:+1: |
i16x8.extract_lane_s |
0x18 |
:+1: |
i16x8.extract_lane_u |
0x19 |
:+1: |
i16x8.replace_lane |
0x1a |
:+1: |
i32x4.extract_lane |
0x1b |
:+1: |
i32x4.replace_lane |
0x1c |
:+1: |
i64x2.extract_lane |
0x1d |
:+1: |
i64x2.replace_lane |
0x1e |
:+1: |
f32x4.extract_lane |
0x1f |
:+1: |
f32x4.replace_lane |
0x20 |
:+1: |
f64x2.extract_lane |
0x21 |
:+1: |
f64x2.replace_lane |
0x22 |
:+1: |
Integer Cmp |
Opcode |
Status |
i8x16.eq |
0x23 |
-- |
i8x16.ne |
0x24 |
-- |
i8x16.lt_s |
0x25 |
-- |
i8x16.lt_u |
0x26 |
-- |
i8x16.gt_s |
0x27 |
-- |
i8x16.gt_u |
0x28 |
-- |
i8x16.le_s |
0x29 |
-- |
i8x16.le_u |
0x2a |
-- |
i8x16.ge_s |
0x2b |
-- |
i8x16.ge_u |
0x2c |
-- |
i16x8.eq |
0x2d |
-- |
i16x8.ne |
0x2e |
-- |
i16x8.lt_s |
0x2f |
-- |
i16x8.lt_u |
0x30 |
-- |
i16x8.gt_s |
0x31 |
-- |
i16x8.gt_u |
0x32 |
-- |
i16x8.le_s |
0x33 |
-- |
i16x8.le_u |
0x34 |
-- |
i16x8.ge_s |
0x35 |
-- |
i16x8.ge_u |
0x36 |
-- |
i32x4.eq |
0x37 |
-- |
i32x4.ne |
0x38 |
-- |
i32x4.lt_s |
0x39 |
-- |
i32x4.lt_u |
0x3a |
-- |
i32x4.gt_s |
0x3b |
-- |
i32x4.gt_u |
0x3c |
-- |
i32x4.le_s |
0x3d |
-- |
i32x4.le_u |
0x3e |
-- |
i32x4.ge_s |
0x3f |
-- |
i32x4.ge_u |
0x40 |
-- |
v128 Op |
Opcode |
Status |
v128.not |
0x4d |
-- |
v128.and |
0x4e |
-- |
v128.andnot |
0x4f |
-- |
v128.or |
0x50 |
-- |
v128.xor |
0x51 |
-- |
v128.bitselect |
0x52 |
-- |
i8x16 Arith Op |
Opcode |
-- |
i8x16.abs |
0x60 |
-- |
i8x16.neg |
0x61 |
-- |
i8x16.any_true |
0x62 |
-- |
i8x16.all_true |
0x63 |
-- |
i8x16.bitmask |
0x64 |
-- |
i8x16.narrow_i16x8_s |
0x65 |
-- |
i8x16.narrow_i16x8_u |
0x66 |
-- |
---- widen ---- |
0x67 |
-- |
---- widen ---- |
0x68 |
-- |
---- widen ---- |
0x69 |
-- |
---- widen ---- |
0x6a |
-- |
i8x16.shl |
0x6b |
-- |
i8x16.shr_s |
0x6c |
-- |
i8x16.shr_u |
0x6d |
-- |
i8x16.add |
0x6e |
-- |
i8x16.add_sat_s |
0x6f |
-- |
i8x16.add_sat_u |
0x70 |
-- |
i8x16.sub |
0x71 |
-- |
i8x16.sub_sat_s |
0x72 |
-- |
i8x16.sub_sat_u |
0x73 |
-- |
---- dot ---- |
0x74 |
-- |
---- mul ---- |
0x75 |
-- |
i8x16.min_s |
0x76 |
-- |
i8x16.min_u |
0x77 |
-- |
i8x16.max_s |
0x78 |
-- |
i8x16.max_u |
0x79 |
-- |
---- avgr_s ---- |
0x7a |
-- |
i8x16.avgr_u |
0x7b |
-- |
i16x8 Arith Op |
Opcode |
Status |
i16x8.abs |
0x80 |
-- |
i16x8.neg |
0x81 |
-- |
i16x8.any_true |
0x82 |
-- |
i16x8.all_true |
0x83 |
-- |
i16x8.bitmask |
0x84 |
-- |
i16x8.narrow_i32x4_s |
0x85 |
-- |
i16x8.narrow_i32x4_u |
0x86 |
-- |
i16x8.widen_low_i8x16_s |
0x87 |
-- |
i16x8.widen_high_i8x16_s |
0x88 |
-- |
i16x8.widen_low_i8x16_u |
0x89 |
-- |
i16x8.widen_high_i8x16_u |
0x8a |
-- |
i16x8.shl |
0x8b |
-- |
i16x8.shr_s |
0x8c |
-- |
i16x8.shr_u |
0x8d |
-- |
i16x8.add |
0x8e |
-- |
i16x8.add_sat_s |
0x8f |
-- |
i16x8.add_sat_u |
0x90 |
-- |
i16x8.sub |
0x91 |
-- |
i16x8.sub_sat_s |
0x92 |
-- |
i16x8.sub_sat_u |
0x93 |
-- |
---- dot ---- |
0x94 |
-- |
i16x8.mul |
0x95 |
-- |
i16x8.min_s |
0x96 |
-- |
i16x8.min_u |
0x97 |
-- |
i16x8.max_s |
0x98 |
-- |
i16x8.max_u |
0x99 |
-- |
---- avgr_s ---- |
0x9a |
-- |
i16x8.avgr_u |
0x9b |
-- |
i32x4 Arith Op |
Opcode |
Status |
i32x4.abs |
0xa0 |
-- |
i32x4.neg |
0xa1 |
-- |
i32x4.any_true |
0xa2 |
-- |
i32x4.all_true |
0xa3 |
-- |
i32x4.bitmask |
0xa4 |
-- |
---- narrow ---- |
0xa5 |
-- |
---- narrow ---- |
0xa6 |
-- |
i32x4.widen_low_i16x8_s |
0xa7 |
-- |
i32x4.widen_high_i16x8_s |
0xa8 |
-- |
i32x4.widen_low_i16x8_u |
0xa9 |
-- |
i32x4.widen_high_i16x8_u |
0xaa |
-- |
i32x4.shl |
0xab |
-- |
i32x4.shr_s |
0xac |
-- |
i32x4.shr_u |
0xad |
-- |
i32x4.add |
0xae |
-- |
---- add_sat ---- |
0xaf |
-- |
---- add_sat ---- |
0xb0 |
-- |
i32x4.sub |
0xb1 |
-- |
---- sub_sat ---- |
0xb2 |
-- |
---- sub_sat ---- |
0xb3 |
-- |
---- dot ---- |
0xb4 |
-- |
i32x4.mul |
0xb5 |
-- |
i32x4.min_s |
0xb6 |
-- |
i32x4.min_u |
0xb7 |
-- |
i32x4.max_s |
0xb8 |
-- |
i32x4.max_u |
0xb9 |
-- |
---- avgr_s ---- |
0xba |
-- |
---- avgr_u ---- |
0xbb |
-- |
i64x2 Arith Op |
Opcode |
Status |
---- |
0xc0 |
-- |
i64x2.neg |
0xc1 |
-- |
---- |
0xc2 |
-- |
---- |
0xc3 |
-- |
---- |
0xc4 |
-- |
---- |
0xc5 |
-- |
---- |
0xc6 |
-- |
---- |
0xc7 |
-- |
---- |
0xc8 |
-- |
---- |
0xc9 |
-- |
---- |
0xca |
-- |
i64x2.shl |
0xcb |
-- |
i64x2.shr_s |
0xcc |
-- |
i64x2.shr_u |
0xcd |
-- |
i64x2.add |
0xce |
-- |
---- |
0xcf |
-- |
---- |
0xd0 |
-- |
i64x2.sub |
0xd1 |
-- |
---- |
0xd2 |
-- |
---- |
0xd3 |
-- |
---- |
0xd4 |
-- |
i64x2.mul |
0xd5 |
-- |
---- |
0xd6 |
-- |
---- |
0xd7 |
-- |
---- |
0xd8 |
-- |
---- |
0xd9 |
-- |
---- |
0xda |
-- |
---- |
0xdb |
-- |
f32x4 Op |
Opcode |
Status |
f32x4.abs |
0xe0 |
-- |
f32x4.neg |
0xe1 |
-- |
---- round ---- |
0xe2 |
-- |
f32x4.sqrt |
0xe3 |
-- |
f32x4.add |
0xe4 |
-- |
f32x4.sub |
0xe5 |
-- |
f32x4.mul |
0xe6 |
-- |
f32x4.div |
0xe7 |
-- |
f32x4.min |
0xe8 |
-- |
f32x4.max |
0xe9 |
-- |
f32x4.pmin |
0xea |
-- |
f32x4.pmax |
0xeb |
-- |
f64x2 Op |
Opcode |
Status |
f64x2.abs |
0xec |
-- |
f64x2.neg |
0xed |
-- |
---- round ---- |
0xee |
-- |
f64x2.sqrt |
0xef |
-- |
f64x2.add |
0xf0 |
-- |
f64x2.sub |
0xf1 |
-- |
f64x2.mul |
0xf2 |
-- |
f64x2.div |
0xf3 |
-- |
f64x2.min |
0xf4 |
-- |
f64x2.max |
0xf5 |
-- |
f64x2.pmin |
0xf6 |
-- |
f64x2.pmax |
0xf7 |
-- |
Conversion Op |
Opcode |
Status |
i32x4.trunc_sat_f32x4_s |
0xf8 |
-- |
i32x4.trunc_sat_f32x4_u |
0xf9 |
-- |
f32x4.convert_i32x4_s |
0xfa |
-- |
f32x4.convert_i32x4_u |
0xfb |
-- |
jlb6740 edited Issue #2272:
Status: Currently Not Valid (Initial Status WIP)
Last Update: 10/8/2020
https://gist.github.com/jlb6740/0a495404f6b3cc901e1b8e5ae8148020
Loads |
Opcode |
Status |
v128.load |
0x00 |
:+1: |
v128.load8x8_s |
0x01 |
:+1: |
v128.load8x8_u |
0x02 |
:+1: |
v128.load16x4_s |
0x03 |
:+1: |
v128.load16x4_u |
0x04 |
:+1: |
v128.load32x2_s |
0x05 |
:+1: |
v128.load32x2_u |
0x06 |
:+1: |
v128.load8_splat |
0x07 |
:+1: |
v128.load16_splat |
0x08 |
:+1: |
v128.load32_splat |
0x09 |
:+1: |
v128.load64_splat |
0x0a |
:+1: |
Basic operation |
Opcode |
Status |
v128.const |
0x0c |
:+1: |
i8x16.shuffle |
0x0d |
:+1: |
i8x16.swizzle |
0x0e |
:+1: |
Splat operation |
Opcode |
Status |
i8x16.splat |
0x0f |
:+1: |
i16x8.splat |
0x10 |
:+1: |
i32x4.splat |
0x11 |
:+1: |
i64x2.splat |
0x12 |
:+1: |
f32x4.splat |
0x13 |
:+1: |
f64x2.splat |
0x14 |
:+1: |
Lane operation |
Opcode |
Status |
i8x16.extract_lane_s |
0x15 |
:+1: |
i8x16.extract_lane_u |
0x16 |
:+1: |
i8x16.replace_lane |
0x17 |
:+1: |
i16x8.extract_lane_s |
0x18 |
:+1: |
i16x8.extract_lane_u |
0x19 |
:+1: |
i16x8.replace_lane |
0x1a |
:+1: |
i32x4.extract_lane |
0x1b |
:+1: |
i32x4.replace_lane |
0x1c |
:+1: |
i64x2.extract_lane |
0x1d |
:+1: |
i64x2.replace_lane |
0x1e |
:+1: |
f32x4.extract_lane |
0x1f |
:+1: |
f32x4.replace_lane |
0x20 |
:+1: |
f64x2.extract_lane |
0x21 |
:+1: |
f64x2.replace_lane |
0x22 |
:+1: |
Integer Cmp |
Opcode |
Status |
i8x16.eq |
0x23 |
:+1: |
i8x16.ne |
0x24 |
:+1: |
i8x16.lt_s |
0x25 |
:+1: |
i8x16.lt_u |
0x26 |
:+1: |
i8x16.gt_s |
0x27 |
:+1: |
i8x16.gt_u |
0x28 |
:+1: |
i8x16.le_s |
0x29 |
:+1: |
i8x16.le_u |
0x2a |
:+1: |
i8x16.ge_s |
0x2b |
:+1: |
i8x16.ge_u |
0x2c |
:+1: |
i16x8.eq |
0x2d |
:+1: |
i16x8.ne |
0x2e |
:+1: |
i16x8.lt_s |
0x2f |
:+1: |
i16x8.lt_u |
0x30 |
:+1: |
i16x8.gt_s |
0x31 |
:+1: |
i16x8.gt_u |
0x32 |
:+1: |
i16x8.le_s |
0x33 |
:+1: |
i16x8.le_u |
0x34 |
:+1: |
i16x8.ge_s |
0x35 |
:+1: |
i16x8.ge_u |
0x36 |
:+1: |
i32x4.eq |
0x37 |
:+1: |
i32x4.ne |
0x38 |
:+1: |
i32x4.lt_s |
0x39 |
:+1: |
i32x4.lt_u |
0x3a |
:+1: |
i32x4.gt_s |
0x3b |
:+1: |
i32x4.gt_u |
0x3c |
:+1: |
i32x4.le_s |
0x3d |
:+1: |
i32x4.le_u |
0x3e |
:+1: |
i32x4.ge_s |
0x3f |
:+1: |
i32x4.ge_u |
0x40 |
:+1: |
v128 Op |
Opcode |
Status |
v128.not |
0x4d |
-- |
v128.and |
0x4e |
-- |
v128.andnot |
0x4f |
-- |
v128.or |
0x50 |
-- |
v128.xor |
0x51 |
-- |
v128.bitselect |
0x52 |
-- |
i8x16 Arith Op |
Opcode |
-- |
i8x16.abs |
0x60 |
-- |
i8x16.neg |
0x61 |
-- |
i8x16.any_true |
0x62 |
-- |
i8x16.all_true |
0x63 |
-- |
i8x16.bitmask |
0x64 |
-- |
i8x16.narrow_i16x8_s |
0x65 |
-- |
i8x16.narrow_i16x8_u |
0x66 |
-- |
---- widen ---- |
0x67 |
-- |
---- widen ---- |
0x68 |
-- |
---- widen ---- |
0x69 |
-- |
---- widen ---- |
0x6a |
-- |
i8x16.shl |
0x6b |
-- |
i8x16.shr_s |
0x6c |
-- |
i8x16.shr_u |
0x6d |
-- |
i8x16.add |
0x6e |
-- |
i8x16.add_sat_s |
0x6f |
-- |
i8x16.add_sat_u |
0x70 |
-- |
i8x16.sub |
0x71 |
-- |
i8x16.sub_sat_s |
0x72 |
-- |
i8x16.sub_sat_u |
0x73 |
-- |
---- dot ---- |
0x74 |
-- |
---- mul ---- |
0x75 |
-- |
i8x16.min_s |
0x76 |
-- |
i8x16.min_u |
0x77 |
-- |
i8x16.max_s |
0x78 |
-- |
i8x16.max_u |
0x79 |
-- |
---- avgr_s ---- |
0x7a |
-- |
i8x16.avgr_u |
0x7b |
-- |
i16x8 Arith Op |
Opcode |
Status |
i16x8.abs |
0x80 |
-- |
i16x8.neg |
0x81 |
-- |
i16x8.any_true |
0x82 |
-- |
i16x8.all_true |
0x83 |
-- |
i16x8.bitmask |
0x84 |
-- |
i16x8.narrow_i32x4_s |
0x85 |
-- |
i16x8.narrow_i32x4_u |
0x86 |
-- |
i16x8.widen_low_i8x16_s |
0x87 |
-- |
i16x8.widen_high_i8x16_s |
0x88 |
-- |
i16x8.widen_low_i8x16_u |
0x89 |
-- |
i16x8.widen_high_i8x16_u |
0x8a |
-- |
i16x8.shl |
0x8b |
-- |
i16x8.shr_s |
0x8c |
-- |
i16x8.shr_u |
0x8d |
-- |
i16x8.add |
0x8e |
-- |
i16x8.add_sat_s |
0x8f |
-- |
i16x8.add_sat_u |
0x90 |
-- |
i16x8.sub |
0x91 |
-- |
i16x8.sub_sat_s |
0x92 |
-- |
i16x8.sub_sat_u |
0x93 |
-- |
---- dot ---- |
0x94 |
-- |
i16x8.mul |
0x95 |
-- |
i16x8.min_s |
0x96 |
-- |
i16x8.min_u |
0x97 |
-- |
i16x8.max_s |
0x98 |
-- |
i16x8.max_u |
0x99 |
-- |
---- avgr_s ---- |
0x9a |
-- |
i16x8.avgr_u |
0x9b |
-- |
i32x4 Arith Op |
Opcode |
Status |
i32x4.abs |
0xa0 |
-- |
i32x4.neg |
0xa1 |
-- |
i32x4.any_true |
0xa2 |
-- |
i32x4.all_true |
0xa3 |
-- |
i32x4.bitmask |
0xa4 |
-- |
---- narrow ---- |
0xa5 |
-- |
---- narrow ---- |
0xa6 |
-- |
i32x4.widen_low_i16x8_s |
0xa7 |
-- |
i32x4.widen_high_i16x8_s |
0xa8 |
-- |
i32x4.widen_low_i16x8_u |
0xa9 |
-- |
i32x4.widen_high_i16x8_u |
0xaa |
-- |
i32x4.shl |
0xab |
-- |
i32x4.shr_s |
0xac |
-- |
i32x4.shr_u |
0xad |
-- |
i32x4.add |
0xae |
-- |
---- add_sat ---- |
0xaf |
-- |
---- add_sat ---- |
0xb0 |
-- |
i32x4.sub |
0xb1 |
-- |
---- sub_sat ---- |
0xb2 |
-- |
---- sub_sat ---- |
0xb3 |
-- |
---- dot ---- |
0xb4 |
-- |
i32x4.mul |
0xb5 |
-- |
i32x4.min_s |
0xb6 |
-- |
i32x4.min_u |
0xb7 |
-- |
i32x4.max_s |
0xb8 |
-- |
i32x4.max_u |
0xb9 |
-- |
---- avgr_s ---- |
0xba |
-- |
---- avgr_u ---- |
0xbb |
-- |
i64x2 Arith Op |
Opcode |
Status |
---- |
0xc0 |
-- |
i64x2.neg |
0xc1 |
-- |
---- |
0xc2 |
-- |
---- |
0xc3 |
-- |
---- |
0xc4 |
-- |
---- |
0xc5 |
-- |
---- |
0xc6 |
-- |
---- |
0xc7 |
-- |
---- |
0xc8 |
-- |
---- |
0xc9 |
-- |
---- |
0xca |
-- |
i64x2.shl |
0xcb |
-- |
i64x2.shr_s |
0xcc |
-- |
i64x2.shr_u |
0xcd |
-- |
i64x2.add |
0xce |
-- |
---- |
0xcf |
-- |
---- |
0xd0 |
-- |
i64x2.sub |
0xd1 |
-- |
---- |
0xd2 |
-- |
---- |
0xd3 |
-- |
---- |
0xd4 |
-- |
i64x2.mul |
0xd5 |
-- |
---- |
0xd6 |
-- |
---- |
0xd7 |
-- |
---- |
0xd8 |
-- |
---- |
0xd9 |
-- |
---- |
0xda |
-- |
---- |
0xdb |
-- |
f32x4 Op |
Opcode |
Status |
f32x4.abs |
0xe0 |
-- |
f32x4.neg |
0xe1 |
-- |
---- round ---- |
0xe2 |
-- |
f32x4.sqrt |
0xe3 |
-- |
f32x4.add |
0xe4 |
-- |
f32x4.sub |
0xe5 |
-- |
f32x4.mul |
0xe6 |
-- |
f32x4.div |
0xe7 |
-- |
f32x4.min |
0xe8 |
-- |
f32x4.max |
0xe9 |
-- |
f32x4.pmin |
0xea |
-- |
f32x4.pmax |
0xeb |
-- |
f64x2 Op |
Opcode |
Status |
f64x2.abs |
0xec |
-- |
f64x2.neg |
0xed |
-- |
---- round ---- |
0xee |
-- |
f64x2.sqrt |
0xef |
-- |
f64x2.add |
0xf0 |
-- |
f64x2.sub |
0xf1 |
-- |
f64x2.mul |
0xf2 |
-- |
f64x2.div |
0xf3 |
-- |
f64x2.min |
0xf4 |
-- |
f64x2.max |
0xf5 |
-- |
f64x2.pmin |
0xf6 |
-- |
f64x2.pmax |
0xf7 |
-- |
Conversion Op |
Opcode |
Status |
i32x4.trunc_sat_f32x4_s |
0xf8 |
-- |
i32x4.trunc_sat_f32x4_u |
0xf9 |
-- |
f32x4.convert_i32x4_s |
0xfa |
-- |
f32x4.convert_i32x4_u |
0xfb |
-- |
jlb6740 edited Issue #2272:
Status: Currently Not Valid (Initial Status WIP)
Last Update: 10/8/2020
https://gist.github.com/jlb6740/0a495404f6b3cc901e1b8e5ae8148020
Loads |
Opcode |
Status |
v128.load |
0x00 |
:+1: |
v128.load8x8_s |
0x01 |
:+1: |
v128.load8x8_u |
0x02 |
:+1: |
v128.load16x4_s |
0x03 |
:+1: |
v128.load16x4_u |
0x04 |
:+1: |
v128.load32x2_s |
0x05 |
:+1: |
v128.load32x2_u |
0x06 |
:+1: |
v128.load8_splat |
0x07 |
:+1: |
v128.load16_splat |
0x08 |
:+1: |
v128.load32_splat |
0x09 |
:+1: |
v128.load64_splat |
0x0a |
:+1: |
Basic operation |
Opcode |
Status |
v128.const |
0x0c |
:+1: |
i8x16.shuffle |
0x0d |
:+1: |
i8x16.swizzle |
0x0e |
:+1: |
Splat operation |
Opcode |
Status |
i8x16.splat |
0x0f |
:+1: |
i16x8.splat |
0x10 |
:+1: |
i32x4.splat |
0x11 |
:+1: |
i64x2.splat |
0x12 |
:+1: |
f32x4.splat |
0x13 |
:+1: |
f64x2.splat |
0x14 |
:+1: |
Lane operation |
Opcode |
Status |
i8x16.extract_lane_s |
0x15 |
:+1: |
i8x16.extract_lane_u |
0x16 |
:+1: |
i8x16.replace_lane |
0x17 |
:+1: |
i16x8.extract_lane_s |
0x18 |
:+1: |
i16x8.extract_lane_u |
0x19 |
:+1: |
i16x8.replace_lane |
0x1a |
:+1: |
i32x4.extract_lane |
0x1b |
:+1: |
i32x4.replace_lane |
0x1c |
:+1: |
i64x2.extract_lane |
0x1d |
:+1: |
i64x2.replace_lane |
0x1e |
:+1: |
f32x4.extract_lane |
0x1f |
:+1: |
f32x4.replace_lane |
0x20 |
:+1: |
f64x2.extract_lane |
0x21 |
:+1: |
f64x2.replace_lane |
0x22 |
:+1: |
Integer Cmp |
Opcode |
Status |
i8x16.eq |
0x23 |
:+1: |
i8x16.ne |
0x24 |
:+1: |
i8x16.lt_s |
0x25 |
:+1: |
i8x16.lt_u |
0x26 |
:+1: |
i8x16.gt_s |
0x27 |
:+1: |
i8x16.gt_u |
0x28 |
:+1: |
i8x16.le_s |
0x29 |
:+1: |
i8x16.le_u |
0x2a |
:+1: |
i8x16.ge_s |
0x2b |
:+1: |
i8x16.ge_u |
0x2c |
:+1: |
i16x8.eq |
0x2d |
:+1: |
i16x8.ne |
0x2e |
:+1: |
i16x8.lt_s |
0x2f |
:+1: |
i16x8.lt_u |
0x30 |
:+1: |
i16x8.gt_s |
0x31 |
:+1: |
i16x8.gt_u |
0x32 |
:+1: |
i16x8.le_s |
0x33 |
:+1: |
i16x8.le_u |
0x34 |
:+1: |
i16x8.ge_s |
0x35 |
:+1: |
i16x8.ge_u |
0x36 |
:+1: |
i32x4.eq |
0x37 |
:+1: |
i32x4.ne |
0x38 |
:+1: |
i32x4.lt_s |
0x39 |
:+1: |
i32x4.lt_u |
0x3a |
:+1: |
i32x4.gt_s |
0x3b |
:+1: |
i32x4.gt_u |
0x3c |
:+1: |
i32x4.le_s |
0x3d |
:+1: |
i32x4.le_u |
0x3e |
:+1: |
i32x4.ge_s |
0x3f |
:+1: |
i32x4.ge_u |
0x40 |
:+1: |
v128 Op |
Opcode |
Status |
v128.not |
0x4d |
-- |
v128.and |
0x4e |
-- |
v128.andnot |
0x4f |
-- |
v128.or |
0x50 |
-- |
v128.xor |
0x51 |
-- |
v128.bitselect |
0x52 |
-- |
i8x16 Arith Op |
Opcode |
-- |
i8x16.abs |
0x60 |
-- |
i8x16.neg |
0x61 |
-- |
i8x16.any_true |
0x62 |
-- |
i8x16.all_true |
0x63 |
-- |
i8x16.bitmask |
0x64 |
-- |
i8x16.narrow_i16x8_s |
0x65 |
-- |
i8x16.narrow_i16x8_u |
0x66 |
-- |
---- widen ---- |
0x67 |
-- |
---- widen ---- |
0x68 |
-- |
---- widen ---- |
0x69 |
-- |
---- widen ---- |
0x6a |
-- |
i8x16.shl |
0x6b |
-- |
i8x16.shr_s |
0x6c |
-- |
i8x16.shr_u |
0x6d |
-- |
i8x16.add |
0x6e |
-- |
i8x16.add_sat_s |
0x6f |
-- |
i8x16.add_sat_u |
0x70 |
-- |
i8x16.sub |
0x71 |
-- |
i8x16.sub_sat_s |
0x72 |
-- |
i8x16.sub_sat_u |
0x73 |
-- |
---- dot ---- |
0x74 |
-- |
---- mul ---- |
0x75 |
-- |
i8x16.min_s |
0x76 |
-- |
i8x16.min_u |
0x77 |
-- |
i8x16.max_s |
0x78 |
-- |
i8x16.max_u |
0x79 |
-- |
---- avgr_s ---- |
0x7a |
-- |
i8x16.avgr_u |
0x7b |
-- |
i16x8 Arith Op |
Opcode |
Status |
i16x8.abs |
0x80 |
-- |
i16x8.neg |
0x81 |
-- |
i16x8.any_true |
0x82 |
-- |
i16x8.all_true |
0x83 |
-- |
i16x8.bitmask |
0x84 |
-- |
i16x8.narrow_i32x4_s |
0x85 |
-- |
i16x8.narrow_i32x4_u |
0x86 |
-- |
i16x8.widen_low_i8x16_s |
0x87 |
-- |
i16x8.widen_high_i8x16_s |
0x88 |
-- |
i16x8.widen_low_i8x16_u |
0x89 |
-- |
i16x8.widen_high_i8x16_u |
0x8a |
-- |
i16x8.shl |
0x8b |
-- |
i16x8.shr_s |
0x8c |
-- |
i16x8.shr_u |
0x8d |
-- |
i16x8.add |
0x8e |
-- |
i16x8.add_sat_s |
0x8f |
-- |
i16x8.add_sat_u |
0x90 |
-- |
i16x8.sub |
0x91 |
-- |
i16x8.sub_sat_s |
0x92 |
-- |
i16x8.sub_sat_u |
0x93 |
-- |
---- dot ---- |
0x94 |
-- |
i16x8.mul |
0x95 |
-- |
i16x8.min_s |
0x96 |
-- |
i16x8.min_u |
0x97 |
-- |
i16x8.max_s |
0x98 |
-- |
i16x8.max_u |
0x99 |
-- |
---- avgr_s ---- |
0x9a |
-- |
i16x8.avgr_u |
0x9b |
-- |
i32x4 Arith Op |
Opcode |
Status |
i32x4.abs |
0xa0 |
-- |
i32x4.neg |
0xa1 |
-- |
i32x4.any_true |
0xa2 |
-- |
i32x4.all_true |
0xa3 |
-- |
i32x4.bitmask |
0xa4 |
-- |
---- narrow ---- |
0xa5 |
-- |
---- narrow ---- |
0xa6 |
-- |
i32x4.widen_low_i16x8_s |
0xa7 |
-- |
i32x4.widen_high_i16x8_s |
0xa8 |
-- |
i32x4.widen_low_i16x8_u |
0xa9 |
-- |
i32x4.widen_high_i16x8_u |
0xaa |
-- |
i32x4.shl |
0xab |
-- |
i32x4.shr_s |
0xac |
-- |
i32x4.shr_u |
0xad |
-- |
i32x4.add |
0xae |
-- |
---- add_sat ---- |
0xaf |
-- |
---- add_sat ---- |
0xb0 |
-- |
i32x4.sub |
0xb1 |
-- |
---- sub_sat ---- |
0xb2 |
-- |
---- sub_sat ---- |
0xb3 |
-- |
---- dot ---- |
0xb4 |
-- |
i32x4.mul |
0xb5 |
-- |
i32x4.min_s |
0xb6 |
-- |
i32x4.min_u |
0xb7 |
-- |
i32x4.max_s |
0xb8 |
-- |
i32x4.max_u |
0xb9 |
-- |
---- avgr_s ---- |
0xba |
-- |
---- avgr_u ---- |
0xbb |
-- |
i64x2 Arith Op |
Opcode |
Status |
---- |
0xc0 |
-- |
i64x2.neg |
0xc1 |
-- |
---- |
0xc2 |
-- |
---- |
0xc3 |
-- |
---- |
0xc4 |
-- |
---- |
0xc5 |
-- |
---- |
0xc6 |
-- |
---- |
0xc7 |
-- |
---- |
0xc8 |
-- |
---- |
0xc9 |
-- |
---- |
0xca |
-- |
i64x2.shl |
0xcb |
-- |
i64x2.shr_s |
0xcc |
-- |
i64x2.shr_u |
0xcd |
-- |
i64x2.add |
0xce |
-- |
---- |
0xcf |
-- |
---- |
0xd0 |
-- |
i64x2.sub |
0xd1 |
-- |
---- |
0xd2 |
-- |
---- |
0xd3 |
-- |
---- |
0xd4 |
-- |
i64x2.mul |
0xd5 |
-- |
---- |
0xd6 |
-- |
---- |
0xd7 |
-- |
---- |
0xd8 |
-- |
---- |
0xd9 |
-- |
---- |
0xda |
-- |
---- |
0xdb |
-- |
f32x4 Op |
Opcode |
Status |
f32x4.abs |
0xe0 |
-- |
f32x4.neg |
0xe1 |
-- |
---- round ---- |
0xe2 |
-- |
f32x4.sqrt |
0xe3 |
-- |
f32x4.add |
0xe4 |
-- |
f32x4.sub |
0xe5 |
-- |
f32x4.mul |
0xe6 |
-- |
f32x4.div |
0xe7 |
-- |
f32x4.min |
0xe8 |
-- |
f32x4.max |
0xe9 |
-- |
f32x4.pmin |
0xea |
-- |
f32x4.pmax |
0xeb |
-- |
f64x2 Op |
Opcode |
Status |
f64x2.abs |
0xec |
-- |
f64x2.neg |
0xed |
-- |
---- round ---- |
0xee |
-- |
f64x2.sqrt |
0xef |
-- |
f64x2.add |
0xf0 |
-- |
f64x2.sub |
0xf1 |
-- |
f64x2.mul |
0xf2 |
-- |
f64x2.div |
0xf3 |
-- |
f64x2.min |
0xf4 |
-- |
f64x2.max |
0xf5 |
-- |
f64x2.pmin |
0xf6 |
-- |
f64x2.pmax |
0xf7 |
-- |
Conversion Op |
Opcode |
Status |
i32x4.trunc_sat_f32x4_s |
0xf8 |
-- |
i32x4.trunc_sat_f32x4_u |
0xf9 |
-- |
f32x4.convert_i32x4_s |
0xfa |
-- |
f32x4.convert_i32x4_u |
0xfb |
-- |
jlb6740 edited Issue #2272:
Status: Currently Not Valid (Initial Status WIP)
Last Update: 10/8/2020
https://gist.github.com/jlb6740/0a495404f6b3cc901e1b8e5ae8148020
Loads |
Opcode |
Status |
v128.load |
0x00 |
:+1: |
v128.load8x8_s |
0x01 |
:+1: |
v128.load8x8_u |
0x02 |
:+1: |
v128.load16x4_s |
0x03 |
:+1: |
v128.load16x4_u |
0x04 |
:+1: |
v128.load32x2_s |
0x05 |
:+1: |
v128.load32x2_u |
0x06 |
:+1: |
v128.load8_splat |
0x07 |
:+1: |
v128.load16_splat |
0x08 |
:+1: |
v128.load32_splat |
0x09 |
:+1: |
v128.load64_splat |
0x0a |
:+1: |
Basic operation |
Opcode |
Status |
v128.const |
0x0c |
:+1: |
i8x16.shuffle |
0x0d |
:+1: |
i8x16.swizzle |
0x0e |
:+1: |
Splat operation |
Opcode |
Status |
i8x16.splat |
0x0f |
:+1: |
i16x8.splat |
0x10 |
:+1: |
i32x4.splat |
0x11 |
:+1: |
i64x2.splat |
0x12 |
:+1: |
f32x4.splat |
0x13 |
:+1: |
f64x2.splat |
0x14 |
:+1: |
Lane operation |
Opcode |
Status |
i8x16.extract_lane_s |
0x15 |
:+1: |
i8x16.extract_lane_u |
0x16 |
:+1: |
i8x16.replace_lane |
0x17 |
:+1: |
i16x8.extract_lane_s |
0x18 |
:+1: |
i16x8.extract_lane_u |
0x19 |
:+1: |
i16x8.replace_lane |
0x1a |
:+1: |
i32x4.extract_lane |
0x1b |
:+1: |
i32x4.replace_lane |
0x1c |
:+1: |
i64x2.extract_lane |
0x1d |
:+1: |
i64x2.replace_lane |
0x1e |
:+1: |
f32x4.extract_lane |
0x1f |
:+1: |
f32x4.replace_lane |
0x20 |
:+1: |
f64x2.extract_lane |
0x21 |
:+1: |
f64x2.replace_lane |
0x22 |
:+1: |
Integer Cmp |
Opcode |
Status |
i8x16.eq |
0x23 |
:+1: |
i8x16.ne |
0x24 |
:+1: |
i8x16.lt_s |
0x25 |
:+1: |
i8x16.lt_u |
0x26 |
:+1: |
i8x16.gt_s |
0x27 |
:+1: |
i8x16.gt_u |
0x28 |
:+1: |
i8x16.le_s |
0x29 |
:+1: |
i8x16.le_u |
0x2a |
:+1: |
i8x16.ge_s |
0x2b |
:+1: |
i8x16.ge_u |
0x2c |
:+1: |
i16x8.eq |
0x2d |
:+1: |
i16x8.ne |
0x2e |
:+1: |
i16x8.lt_s |
0x2f |
:+1: |
i16x8.lt_u |
0x30 |
:+1: |
i16x8.gt_s |
0x31 |
:+1: |
i16x8.gt_u |
0x32 |
:+1: |
i16x8.le_s |
0x33 |
:+1: |
i16x8.le_u |
0x34 |
:+1: |
i16x8.ge_s |
0x35 |
:+1: |
i16x8.ge_u |
0x36 |
:+1: |
i32x4.eq |
0x37 |
:+1: |
i32x4.ne |
0x38 |
:+1: |
i32x4.lt_s |
0x39 |
:+1: |
i32x4.lt_u |
0x3a |
:+1: |
i32x4.gt_s |
0x3b |
:+1: |
i32x4.gt_u |
0x3c |
:+1: |
i32x4.le_s |
0x3d |
:+1: |
i32x4.le_u |
0x3e |
:+1: |
i32x4.ge_s |
0x3f |
:+1: |
i32x4.ge_u |
0x40 |
:+1: |
v128 Op |
Opcode |
Status |
v128.not |
0x4d |
:+1: |
v128.and |
0x4e |
:+1: |
v128.andnot |
0x4f |
:+1: |
v128.or |
0x50 |
:+1: |
v128.xor |
0x51 |
:+1: |
v128.bitselect |
0x52 |
:+1: |
i8x16 Arith Op |
Opcode |
-- |
i8x16.abs |
0x60 |
:+1: |
i8x16.neg |
0x61 |
-- |
i8x16.any_true |
0x62 |
-- |
i8x16.all_true |
0x63 |
-- |
i8x16.bitmask |
0x64 |
-- |
i8x16.narrow_i16x8_s |
0x65 |
-- |
i8x16.narrow_i16x8_u |
0x66 |
-- |
---- widen ---- |
0x67 |
-- |
---- widen ---- |
0x68 |
-- |
---- widen ---- |
0x69 |
-- |
---- widen ---- |
0x6a |
-- |
i8x16.shl |
0x6b |
:+1: |
i8x16.shr_s |
0x6c |
-- |
i8x16.shr_u |
0x6d |
-- |
i8x16.add |
0x6e |
-- |
i8x16.add_sat_s |
0x6f |
-- |
i8x16.add_sat_u |
0x70 |
-- |
i8x16.sub |
0x71 |
-- |
i8x16.sub_sat_s |
0x72 |
-- |
i8x16.sub_sat_u |
0x73 |
-- |
---- dot ---- |
0x74 |
-- |
---- mul ---- |
0x75 |
-- |
i8x16.min_s |
0x76 |
-- |
i8x16.min_u |
0x77 |
-- |
i8x16.max_s |
0x78 |
-- |
i8x16.max_u |
0x79 |
-- |
---- avgr_s ---- |
0x7a |
-- |
i8x16.avgr_u |
0x7b |
-- |
i16x8 Arith Op |
Opcode |
Status |
i16x8.abs |
0x80 |
:+1: |
i16x8.neg |
0x81 |
-- |
i16x8.any_true |
0x82 |
-- |
i16x8.all_true |
0x83 |
-- |
i16x8.bitmask |
0x84 |
-- |
i16x8.narrow_i32x4_s |
0x85 |
-- |
i16x8.narrow_i32x4_u |
0x86 |
-- |
i16x8.widen_low_i8x16_s |
0x87 |
-- |
i16x8.widen_high_i8x16_s |
0x88 |
-- |
i16x8.widen_low_i8x16_u |
0x89 |
-- |
i16x8.widen_high_i8x16_u |
0x8a |
-- |
i16x8.shl |
0x8b |
:+1: |
i16x8.shr_s |
0x8c |
-- |
i16x8.shr_u |
0x8d |
-- |
i16x8.add |
0x8e |
-- |
i16x8.add_sat_s |
0x8f |
-- |
i16x8.add_sat_u |
0x90 |
-- |
i16x8.sub |
0x91 |
-- |
i16x8.sub_sat_s |
0x92 |
-- |
i16x8.sub_sat_u |
0x93 |
-- |
---- dot ---- |
0x94 |
-- |
i16x8.mul |
0x95 |
-- |
i16x8.min_s |
0x96 |
-- |
i16x8.min_u |
0x97 |
-- |
i16x8.max_s |
0x98 |
-- |
i16x8.max_u |
0x99 |
-- |
---- avgr_s ---- |
0x9a |
-- |
i16x8.avgr_u |
0x9b |
-- |
i32x4 Arith Op |
Opcode |
Status |
i32x4.abs |
0xa0 |
:+1: |
i32x4.neg |
0xa1 |
-- |
i32x4.any_true |
0xa2 |
-- |
i32x4.all_true |
0xa3 |
-- |
i32x4.bitmask |
0xa4 |
-- |
---- narrow ---- |
0xa5 |
-- |
---- narrow ---- |
0xa6 |
-- |
i32x4.widen_low_i16x8_s |
0xa7 |
-- |
i32x4.widen_high_i16x8_s |
0xa8 |
-- |
i32x4.widen_low_i16x8_u |
0xa9 |
-- |
i32x4.widen_high_i16x8_u |
0xaa |
-- |
i32x4.shl |
0xab |
:+1: |
i32x4.shr_s |
0xac |
-- |
i32x4.shr_u |
0xad |
-- |
i32x4.add |
0xae |
-- |
---- add_sat ---- |
0xaf |
-- |
---- add_sat ---- |
0xb0 |
-- |
i32x4.sub |
0xb1 |
-- |
---- sub_sat ---- |
0xb2 |
-- |
---- sub_sat ---- |
0xb3 |
-- |
---- dot ---- |
0xb4 |
-- |
i32x4.mul |
0xb5 |
-- |
i32x4.min_s |
0xb6 |
-- |
i32x4.min_u |
0xb7 |
-- |
i32x4.max_s |
0xb8 |
-- |
i32x4.max_u |
0xb9 |
-- |
---- avgr_s ---- |
0xba |
-- |
---- avgr_u ---- |
0xbb |
-- |
i64x2 Arith Op |
Opcode |
Status |
---- |
0xc0 |
-- |
i64x2.neg |
0xc1 |
-- |
---- |
0xc2 |
-- |
---- |
0xc3 |
-- |
---- |
0xc4 |
-- |
---- |
0xc5 |
-- |
---- |
0xc6 |
-- |
---- |
0xc7 |
-- |
---- |
0xc8 |
-- |
---- |
0xc9 |
-- |
---- |
0xca |
-- |
i64x2.shl |
0xcb |
:+1: |
i64x2.shr_s |
0xcc |
-- |
i64x2.shr_u |
0xcd |
-- |
i64x2.add |
0xce |
-- |
---- |
0xcf |
-- |
---- |
0xd0 |
-- |
i64x2.sub |
0xd1 |
-- |
---- |
0xd2 |
-- |
---- |
0xd3 |
-- |
---- |
0xd4 |
-- |
i64x2.mul |
0xd5 |
-- |
---- |
0xd6 |
-- |
---- |
0xd7 |
-- |
---- |
0xd8 |
-- |
---- |
0xd9 |
-- |
---- |
0xda |
-- |
---- |
0xdb |
-- |
f32x4 Op |
Opcode |
Status |
f32x4.abs |
0xe0 |
-- |
f32x4.neg |
0xe1 |
-- |
---- round ---- |
0xe2 |
-- |
f32x4.sqrt |
0xe3 |
-- |
f32x4.add |
0xe4 |
-- |
f32x4.sub |
0xe5 |
-- |
f32x4.mul |
0xe6 |
-- |
f32x4.div |
0xe7 |
-- |
f32x4.min |
0xe8 |
-- |
f32x4.max |
0xe9 |
-- |
f32x4.pmin |
0xea |
-- |
f32x4.pmax |
0xeb |
-- |
f64x2 Op |
Opcode |
Status |
f64x2.abs |
0xec |
-- |
f64x2.neg |
0xed |
-- |
---- round ---- |
0xee |
-- |
f64x2.sqrt |
0xef |
-- |
f64x2.add |
0xf0 |
-- |
f64x2.sub |
0xf1 |
-- |
f64x2.mul |
0xf2 |
-- |
f64x2.div |
0xf3 |
-- |
f64x2.min |
0xf4 |
-- |
f64x2.max |
0xf5 |
-- |
f64x2.pmin |
0xf6 |
-- |
f64x2.pmax |
0xf7 |
-- |
Conversion Op |
Opcode |
Status |
i32x4.trunc_sat_f32x4_s |
0xf8 |
-- |
i32x4.trunc_sat_f32x4_u |
0xf9 |
-- |
f32x4.convert_i32x4_s |
0xfa |
-- |
f32x4.convert_i32x4_u |
0xfb |
-- |
jlb6740 edited Issue #2272:
Status: Currently Not Valid (Initial Status WIP)
Last Update: 10/8/2020
https://gist.github.com/jlb6740/0a495404f6b3cc901e1b8e5ae8148020
Loads |
Opcode |
Status |
v128.load |
0x00 |
:+1: |
v128.load8x8_s |
0x01 |
:+1: |
v128.load8x8_u |
0x02 |
:+1: |
v128.load16x4_s |
0x03 |
:+1: |
v128.load16x4_u |
0x04 |
:+1: |
v128.load32x2_s |
0x05 |
:+1: |
v128.load32x2_u |
0x06 |
:+1: |
v128.load8_splat |
0x07 |
:+1: |
v128.load16_splat |
0x08 |
:+1: |
v128.load32_splat |
0x09 |
:+1: |
v128.load64_splat |
0x0a |
:+1: |
Basic operation |
Opcode |
Status |
v128.const |
0x0c |
:+1: |
i8x16.shuffle |
0x0d |
:+1: |
i8x16.swizzle |
0x0e |
:+1: |
Splat operation |
Opcode |
Status |
i8x16.splat |
0x0f |
:+1: |
i16x8.splat |
0x10 |
:+1: |
i32x4.splat |
0x11 |
:+1: |
i64x2.splat |
0x12 |
:+1: |
f32x4.splat |
0x13 |
:+1: |
f64x2.splat |
0x14 |
:+1: |
Lane operation |
Opcode |
Status |
i8x16.extract_lane_s |
0x15 |
:+1: |
i8x16.extract_lane_u |
0x16 |
:+1: |
i8x16.replace_lane |
0x17 |
:+1: |
i16x8.extract_lane_s |
0x18 |
:+1: |
i16x8.extract_lane_u |
0x19 |
:+1: |
i16x8.replace_lane |
0x1a |
:+1: |
i32x4.extract_lane |
0x1b |
:+1: |
i32x4.replace_lane |
0x1c |
:+1: |
i64x2.extract_lane |
0x1d |
:+1: |
i64x2.replace_lane |
0x1e |
:+1: |
f32x4.extract_lane |
0x1f |
:+1: |
f32x4.replace_lane |
0x20 |
:+1: |
f64x2.extract_lane |
0x21 |
:+1: |
f64x2.replace_lane |
0x22 |
:+1: |
Integer Cmp |
Opcode |
Status |
i8x16.eq |
0x23 |
:+1: |
i8x16.ne |
0x24 |
:+1: |
i8x16.lt_s |
0x25 |
:+1: |
i8x16.lt_u |
0x26 |
:+1: |
i8x16.gt_s |
0x27 |
:+1: |
i8x16.gt_u |
0x28 |
:+1: |
i8x16.le_s |
0x29 |
:+1: |
i8x16.le_u |
0x2a |
:+1: |
i8x16.ge_s |
0x2b |
:+1: |
i8x16.ge_u |
0x2c |
:+1: |
i16x8.eq |
0x2d |
:+1: |
i16x8.ne |
0x2e |
:+1: |
i16x8.lt_s |
0x2f |
:+1: |
i16x8.lt_u |
0x30 |
:+1: |
i16x8.gt_s |
0x31 |
:+1: |
i16x8.gt_u |
0x32 |
:+1: |
i16x8.le_s |
0x33 |
:+1: |
i16x8.le_u |
0x34 |
:+1: |
i16x8.ge_s |
0x35 |
:+1: |
i16x8.ge_u |
0x36 |
:+1: |
i32x4.eq |
0x37 |
:+1: |
i32x4.ne |
0x38 |
:+1: |
i32x4.lt_s |
0x39 |
:+1: |
i32x4.lt_u |
0x3a |
:+1: |
i32x4.gt_s |
0x3b |
:+1: |
i32x4.gt_u |
0x3c |
:+1: |
i32x4.le_s |
0x3d |
:+1: |
i32x4.le_u |
0x3e |
:+1: |
i32x4.ge_s |
0x3f |
:+1: |
i32x4.ge_u |
0x40 |
:+1: |
v128 Op |
Opcode |
Status |
v128.not |
0x4d |
:+1: |
v128.and |
0x4e |
:+1: |
v128.andnot |
0x4f |
:+1: |
v128.or |
0x50 |
:+1: |
v128.xor |
0x51 |
:+1: |
v128.bitselect |
0x52 |
:+1: |
i8x16 Arith Op |
Opcode |
-- |
i8x16.abs |
0x60 |
:+1: |
i8x16.neg |
0x61 |
-- |
i8x16.any_true |
0x62 |
-- |
i8x16.all_true |
0x63 |
-- |
i8x16.bitmask |
0x64 |
-- |
i8x16.narrow_i16x8_s |
0x65 |
-- |
i8x16.narrow_i16x8_u |
0x66 |
-- |
---- widen ---- |
0x67 |
-- |
---- widen ---- |
0x68 |
-- |
---- widen ---- |
0x69 |
-- |
---- widen ---- |
0x6a |
-- |
i8x16.shl |
0x6b |
:+1: |
i8x16.shr_s |
0x6c |
:+1: |
i8x16.shr_u |
0x6d |
:+1: |
i8x16.add |
0x6e |
-- |
i8x16.add_sat_s |
0x6f |
-- |
i8x16.add_sat_u |
0x70 |
-- |
i8x16.sub |
0x71 |
-- |
i8x16.sub_sat_s |
0x72 |
-- |
i8x16.sub_sat_u |
0x73 |
-- |
---- dot ---- |
0x74 |
-- |
---- mul ---- |
0x75 |
-- |
i8x16.min_s |
0x76 |
-- |
i8x16.min_u |
0x77 |
-- |
i8x16.max_s |
0x78 |
-- |
i8x16.max_u |
0x79 |
-- |
---- avgr_s ---- |
0x7a |
-- |
i8x16.avgr_u |
0x7b |
-- |
i16x8 Arith Op |
Opcode |
Status |
i16x8.abs |
0x80 |
:+1: |
i16x8.neg |
0x81 |
-- |
i16x8.any_true |
0x82 |
-- |
i16x8.all_true |
0x83 |
-- |
i16x8.bitmask |
0x84 |
-- |
i16x8.narrow_i32x4_s |
0x85 |
-- |
i16x8.narrow_i32x4_u |
0x86 |
-- |
i16x8.widen_low_i8x16_s |
0x87 |
-- |
i16x8.widen_high_i8x16_s |
0x88 |
-- |
i16x8.widen_low_i8x16_u |
0x89 |
-- |
i16x8.widen_high_i8x16_u |
0x8a |
-- |
i16x8.shl |
0x8b |
:+1: |
i16x8.shr_s |
0x8c |
:+1: |
i16x8.shr_u |
0x8d |
:+1: |
i16x8.add |
0x8e |
-- |
i16x8.add_sat_s |
0x8f |
-- |
i16x8.add_sat_u |
0x90 |
-- |
i16x8.sub |
0x91 |
-- |
i16x8.sub_sat_s |
0x92 |
-- |
i16x8.sub_sat_u |
0x93 |
-- |
---- dot ---- |
0x94 |
-- |
i16x8.mul |
0x95 |
-- |
i16x8.min_s |
0x96 |
-- |
i16x8.min_u |
0x97 |
-- |
i16x8.max_s |
0x98 |
-- |
i16x8.max_u |
0x99 |
-- |
---- avgr_s ---- |
0x9a |
-- |
i16x8.avgr_u |
0x9b |
-- |
i32x4 Arith Op |
Opcode |
Status |
i32x4.abs |
0xa0 |
:+1: |
i32x4.neg |
0xa1 |
-- |
i32x4.any_true |
0xa2 |
-- |
i32x4.all_true |
0xa3 |
-- |
i32x4.bitmask |
0xa4 |
-- |
---- narrow ---- |
0xa5 |
-- |
---- narrow ---- |
0xa6 |
-- |
i32x4.widen_low_i16x8_s |
0xa7 |
-- |
i32x4.widen_high_i16x8_s |
0xa8 |
-- |
i32x4.widen_low_i16x8_u |
0xa9 |
-- |
i32x4.widen_high_i16x8_u |
0xaa |
-- |
i32x4.shl |
0xab |
:+1: |
i32x4.shr_s |
0xac |
:+1: |
i32x4.shr_u |
0xad |
:+1: |
i32x4.add |
0xae |
-- |
---- add_sat ---- |
0xaf |
-- |
---- add_sat ---- |
0xb0 |
-- |
i32x4.sub |
0xb1 |
-- |
---- sub_sat ---- |
0xb2 |
-- |
---- sub_sat ---- |
0xb3 |
-- |
---- dot ---- |
0xb4 |
-- |
i32x4.mul |
0xb5 |
-- |
i32x4.min_s |
0xb6 |
-- |
i32x4.min_u |
0xb7 |
-- |
i32x4.max_s |
0xb8 |
-- |
i32x4.max_u |
0xb9 |
-- |
---- avgr_s ---- |
0xba |
-- |
---- avgr_u ---- |
0xbb |
-- |
i64x2 Arith Op |
Opcode |
Status |
---- |
0xc0 |
-- |
i64x2.neg |
0xc1 |
-- |
---- |
0xc2 |
-- |
---- |
0xc3 |
-- |
---- |
0xc4 |
-- |
---- |
0xc5 |
-- |
---- |
0xc6 |
-- |
---- |
0xc7 |
-- |
---- |
0xc8 |
-- |
---- |
0xc9 |
-- |
---- |
0xca |
-- |
i64x2.shl |
0xcb |
:+1: |
i64x2.shr_s |
0xcc |
:+1: |
i64x2.shr_u |
0xcd |
:+1: |
i64x2.add |
0xce |
-- |
---- |
0xcf |
-- |
---- |
0xd0 |
-- |
i64x2.sub |
0xd1 |
-- |
---- |
0xd2 |
-- |
---- |
0xd3 |
-- |
---- |
0xd4 |
-- |
i64x2.mul |
0xd5 |
-- |
---- |
0xd6 |
-- |
---- |
0xd7 |
-- |
---- |
0xd8 |
-- |
---- |
0xd9 |
-- |
---- |
0xda |
-- |
---- |
0xdb |
-- |
f32x4 Op |
Opcode |
Status |
f32x4.abs |
0xe0 |
-- |
f32x4.neg |
0xe1 |
-- |
---- round ---- |
0xe2 |
-- |
f32x4.sqrt |
0xe3 |
-- |
f32x4.add |
0xe4 |
-- |
f32x4.sub |
0xe5 |
-- |
f32x4.mul |
0xe6 |
-- |
f32x4.div |
0xe7 |
-- |
f32x4.min |
0xe8 |
-- |
f32x4.max |
0xe9 |
-- |
f32x4.pmin |
0xea |
-- |
f32x4.pmax |
0xeb |
-- |
f64x2 Op |
Opcode |
Status |
f64x2.abs |
0xec |
-- |
f64x2.neg |
0xed |
-- |
---- round ---- |
0xee |
-- |
f64x2.sqrt |
0xef |
-- |
f64x2.add |
0xf0 |
-- |
f64x2.sub |
0xf1 |
-- |
f64x2.mul |
0xf2 |
-- |
f64x2.div |
0xf3 |
-- |
f64x2.min |
0xf4 |
-- |
f64x2.max |
0xf5 |
-- |
f64x2.pmin |
0xf6 |
-- |
f64x2.pmax |
0xf7 |
-- |
Conversion Op |
Opcode |
Status |
i32x4.trunc_sat_f32x4_s |
0xf8 |
-- |
i32x4.trunc_sat_f32x4_u |
0xf9 |
-- |
f32x4.convert_i32x4_s |
0xfa |
-- |
f32x4.convert_i32x4_u |
0xfb |
-- |
jlb6740 edited Issue #2272:
Status: Currently Not Valid (Initial Status WIP)
Last Update: 10/8/2020
https://gist.github.com/jlb6740/0a495404f6b3cc901e1b8e5ae8148020
Loads |
Opcode |
Status |
v128.load |
0x00 |
:+1: |
v128.load8x8_s |
0x01 |
:+1: |
v128.load8x8_u |
0x02 |
:+1: |
v128.load16x4_s |
0x03 |
:+1: |
v128.load16x4_u |
0x04 |
:+1: |
v128.load32x2_s |
0x05 |
:+1: |
v128.load32x2_u |
0x06 |
:+1: |
v128.load8_splat |
0x07 |
:+1: |
v128.load16_splat |
0x08 |
:+1: |
v128.load32_splat |
0x09 |
:+1: |
v128.load64_splat |
0x0a |
:+1: |
Basic operation |
Opcode |
Status |
v128.const |
0x0c |
:+1: |
i8x16.shuffle |
0x0d |
:+1: |
i8x16.swizzle |
0x0e |
:+1: |
Splat operation |
Opcode |
Status |
i8x16.splat |
0x0f |
:+1: |
i16x8.splat |
0x10 |
:+1: |
i32x4.splat |
0x11 |
:+1: |
i64x2.splat |
0x12 |
:+1: |
f32x4.splat |
0x13 |
:+1: |
f64x2.splat |
0x14 |
:+1: |
Lane operation |
Opcode |
Status |
i8x16.extract_lane_s |
0x15 |
:+1: |
i8x16.extract_lane_u |
0x16 |
:+1: |
i8x16.replace_lane |
0x17 |
:+1: |
i16x8.extract_lane_s |
0x18 |
:+1: |
i16x8.extract_lane_u |
0x19 |
:+1: |
i16x8.replace_lane |
0x1a |
:+1: |
i32x4.extract_lane |
0x1b |
:+1: |
i32x4.replace_lane |
0x1c |
:+1: |
i64x2.extract_lane |
0x1d |
:+1: |
i64x2.replace_lane |
0x1e |
:+1: |
f32x4.extract_lane |
0x1f |
:+1: |
f32x4.replace_lane |
0x20 |
:+1: |
f64x2.extract_lane |
0x21 |
:+1: |
f64x2.replace_lane |
0x22 |
:+1: |
Integer Cmp |
Opcode |
Status |
i8x16.eq |
0x23 |
:+1: |
i8x16.ne |
0x24 |
:+1: |
i8x16.lt_s |
0x25 |
:+1: |
i8x16.lt_u |
0x26 |
:+1: |
i8x16.gt_s |
0x27 |
:+1: |
i8x16.gt_u |
0x28 |
:+1: |
i8x16.le_s |
0x29 |
:+1: |
i8x16.le_u |
0x2a |
:+1: |
i8x16.ge_s |
0x2b |
:+1: |
i8x16.ge_u |
0x2c |
:+1: |
i16x8.eq |
0x2d |
:+1: |
i16x8.ne |
0x2e |
:+1: |
i16x8.lt_s |
0x2f |
:+1: |
i16x8.lt_u |
0x30 |
:+1: |
i16x8.gt_s |
0x31 |
:+1: |
i16x8.gt_u |
0x32 |
:+1: |
i16x8.le_s |
0x33 |
:+1: |
i16x8.le_u |
0x34 |
:+1: |
i16x8.ge_s |
0x35 |
:+1: |
i16x8.ge_u |
0x36 |
:+1: |
i32x4.eq |
0x37 |
:+1: |
i32x4.ne |
0x38 |
:+1: |
i32x4.lt_s |
0x39 |
:+1: |
i32x4.lt_u |
0x3a |
:+1: |
i32x4.gt_s |
0x3b |
:+1: |
i32x4.gt_u |
0x3c |
:+1: |
i32x4.le_s |
0x3d |
:+1: |
i32x4.le_u |
0x3e |
:+1: |
i32x4.ge_s |
0x3f |
:+1: |
i32x4.ge_u |
0x40 |
:+1: |
v128 Op |
Opcode |
Status |
v128.not |
0x4d |
:+1: |
v128.and |
0x4e |
:+1: |
v128.andnot |
0x4f |
:+1: |
v128.or |
0x50 |
:+1: |
v128.xor |
0x51 |
:+1: |
v128.bitselect |
0x52 |
:+1: |
i8x16 Arith Op |
Opcode |
-- |
i8x16.abs |
0x60 |
:+1: |
i8x16.neg |
0x61 |
-- |
i8x16.any_true |
0x62 |
:+1: |
i8x16.all_true |
0x63 |
:+1: |
i8x16.bitmask |
0x64 |
-- |
i8x16.narrow_i16x8_s |
0x65 |
-- |
i8x16.narrow_i16x8_u |
0x66 |
-- |
---- widen ---- |
0x67 |
-- |
---- widen ---- |
0x68 |
-- |
---- widen ---- |
0x69 |
-- |
---- widen ---- |
0x6a |
-- |
i8x16.shl |
0x6b |
:+1: |
i8x16.shr_s |
0x6c |
:+1: |
i8x16.shr_u |
0x6d |
:+1: |
i8x16.add |
0x6e |
-- |
i8x16.add_sat_s |
0x6f |
-- |
i8x16.add_sat_u |
0x70 |
-- |
i8x16.sub |
0x71 |
-- |
i8x16.sub_sat_s |
0x72 |
-- |
i8x16.sub_sat_u |
0x73 |
-- |
---- dot ---- |
0x74 |
-- |
---- mul ---- |
0x75 |
-- |
i8x16.min_s |
0x76 |
-- |
i8x16.min_u |
0x77 |
-- |
i8x16.max_s |
0x78 |
-- |
i8x16.max_u |
0x79 |
-- |
---- avgr_s ---- |
0x7a |
-- |
i8x16.avgr_u |
0x7b |
-- |
i16x8 Arith Op |
Opcode |
Status |
i16x8.abs |
0x80 |
:+1: |
i16x8.neg |
0x81 |
-- |
i16x8.any_true |
0x82 |
:+1: |
i16x8.all_true |
0x83 |
:+1: |
i16x8.bitmask |
0x84 |
:x: |
i16x8.narrow_i32x4_s |
0x85 |
-- |
i16x8.narrow_i32x4_u |
0x86 |
-- |
i16x8.widen_low_i8x16_s |
0x87 |
-- |
i16x8.widen_high_i8x16_s |
0x88 |
-- |
i16x8.widen_low_i8x16_u |
0x89 |
-- |
i16x8.widen_high_i8x16_u |
0x8a |
-- |
i16x8.shl |
0x8b |
:+1: |
i16x8.shr_s |
0x8c |
:+1: |
i16x8.shr_u |
0x8d |
:+1: |
i16x8.add |
0x8e |
-- |
i16x8.add_sat_s |
0x8f |
-- |
i16x8.add_sat_u |
0x90 |
-- |
i16x8.sub |
0x91 |
-- |
i16x8.sub_sat_s |
0x92 |
-- |
i16x8.sub_sat_u |
0x93 |
-- |
---- dot ---- |
0x94 |
-- |
i16x8.mul |
0x95 |
-- |
i16x8.min_s |
0x96 |
-- |
i16x8.min_u |
0x97 |
-- |
i16x8.max_s |
0x98 |
-- |
i16x8.max_u |
0x99 |
-- |
---- avgr_s ---- |
0x9a |
-- |
i16x8.avgr_u |
0x9b |
-- |
i32x4 Arith Op |
Opcode |
Status |
i32x4.abs |
0xa0 |
:+1: |
i32x4.neg |
0xa1 |
-- |
i32x4.any_true |
0xa2 |
:+1: |
i32x4.all_true |
0xa3 |
:+1: |
i32x4.bitmask |
0xa4 |
:question: |
---- narrow ---- |
0xa5 |
-- |
---- narrow ---- |
0xa6 |
-- |
i32x4.widen_low_i16x8_s |
0xa7 |
-- |
i32x4.widen_high_i16x8_s |
0xa8 |
-- |
i32x4.widen_low_i16x8_u |
0xa9 |
-- |
i32x4.widen_high_i16x8_u |
0xaa |
-- |
i32x4.shl |
0xab |
:+1: |
i32x4.shr_s |
0xac |
:+1: |
i32x4.shr_u |
0xad |
:+1: |
i32x4.add |
0xae |
-- |
---- add_sat ---- |
0xaf |
-- |
---- add_sat ---- |
0xb0 |
-- |
i32x4.sub |
0xb1 |
-- |
---- sub_sat ---- |
0xb2 |
-- |
---- sub_sat ---- |
0xb3 |
-- |
---- dot ---- |
0xb4 |
-- |
i32x4.mul |
0xb5 |
-- |
i32x4.min_s |
0xb6 |
-- |
i32x4.min_u |
0xb7 |
-- |
i32x4.max_s |
0xb8 |
-- |
i32x4.max_u |
0xb9 |
-- |
---- avgr_s ---- |
0xba |
-- |
---- avgr_u ---- |
0xbb |
-- |
i64x2 Arith Op |
Opcode |
Status |
---- |
0xc0 |
-- |
i64x2.neg |
0xc1 |
-- |
---- |
0xc2 |
-- |
---- |
0xc3 |
-- |
---- |
0xc4 |
-- |
---- |
0xc5 |
-- |
---- |
0xc6 |
-- |
---- |
0xc7 |
-- |
---- |
0xc8 |
-- |
---- |
0xc9 |
-- |
---- |
0xca |
-- |
i64x2.shl |
0xcb |
:+1: |
i64x2.shr_s |
0xcc |
:+1: |
i64x2.shr_u |
0xcd |
:+1: |
i64x2.add |
0xce |
-- |
---- |
0xcf |
-- |
---- |
0xd0 |
-- |
i64x2.sub |
0xd1 |
-- |
---- |
0xd2 |
-- |
---- |
0xd3 |
-- |
---- |
0xd4 |
-- |
i64x2.mul |
0xd5 |
-- |
---- |
0xd6 |
-- |
---- |
0xd7 |
-- |
---- |
0xd8 |
-- |
---- |
0xd9 |
-- |
---- |
0xda |
-- |
---- |
0xdb |
-- |
f32x4 Op |
Opcode |
Status |
f32x4.abs |
0xe0 |
-- |
f32x4.neg |
0xe1 |
-- |
---- round ---- |
0xe2 |
-- |
f32x4.sqrt |
0xe3 |
-- |
f32x4.add |
0xe4 |
-- |
f32x4.sub |
0xe5 |
-- |
f32x4.mul |
0xe6 |
-- |
f32x4.div |
0xe7 |
-- |
f32x4.min |
0xe8 |
-- |
f32x4.max |
0xe9 |
-- |
f32x4.pmin |
0xea |
-- |
f32x4.pmax |
0xeb |
-- |
f64x2 Op |
Opcode |
Status |
f64x2.abs |
0xec |
-- |
f64x2.neg |
0xed |
-- |
---- round ---- |
0xee |
-- |
f64x2.sqrt |
0xef |
-- |
f64x2.add |
0xf0 |
-- |
f64x2.sub |
0xf1 |
-- |
f64x2.mul |
0xf2 |
-- |
f64x2.div |
0xf3 |
-- |
f64x2.min |
0xf4 |
-- |
f64x2.max |
0xf5 |
-- |
f64x2.pmin |
0xf6 |
-- |
f64x2.pmax |
0xf7 |
-- |
Conversion Op |
Opcode |
Status |
i32x4.trunc_sat_f32x4_s |
0xf8 |
-- |
i32x4.trunc_sat_f32x4_u |
0xf9 |
-- |
f32x4.convert_i32x4_s |
0xfa |
-- |
f32x4.convert_i32x4_u |
0xfb |
-- |
jlb6740 edited Issue #2272:
Status: Currently Not Valid (Initial Status WIP)
Last Update: 10/8/2020
https://gist.github.com/jlb6740/0a495404f6b3cc901e1b8e5ae8148020
Loads |
Opcode |
Status |
v128.load |
0x00 |
:+1: |
v128.load8x8_s |
0x01 |
:+1: |
v128.load8x8_u |
0x02 |
:+1: |
v128.load16x4_s |
0x03 |
:+1: |
v128.load16x4_u |
0x04 |
:+1: |
v128.load32x2_s |
0x05 |
:+1: |
v128.load32x2_u |
0x06 |
:+1: |
v128.load8_splat |
0x07 |
:+1: |
v128.load16_splat |
0x08 |
:+1: |
v128.load32_splat |
0x09 |
:+1: |
v128.load64_splat |
0x0a |
:+1: |
Basic operation |
Opcode |
Status |
v128.const |
0x0c |
:+1: |
i8x16.shuffle |
0x0d |
:+1: |
i8x16.swizzle |
0x0e |
:+1: |
Splat operation |
Opcode |
Status |
i8x16.splat |
0x0f |
:+1: |
i16x8.splat |
0x10 |
:+1: |
i32x4.splat |
0x11 |
:+1: |
i64x2.splat |
0x12 |
:+1: |
f32x4.splat |
0x13 |
:+1: |
f64x2.splat |
0x14 |
:+1: |
Lane operation |
Opcode |
Status |
i8x16.extract_lane_s |
0x15 |
:+1: |
i8x16.extract_lane_u |
0x16 |
:+1: |
i8x16.replace_lane |
0x17 |
:+1: |
i16x8.extract_lane_s |
0x18 |
:+1: |
i16x8.extract_lane_u |
0x19 |
:+1: |
i16x8.replace_lane |
0x1a |
:+1: |
i32x4.extract_lane |
0x1b |
:+1: |
i32x4.replace_lane |
0x1c |
:+1: |
i64x2.extract_lane |
0x1d |
:+1: |
i64x2.replace_lane |
0x1e |
:+1: |
f32x4.extract_lane |
0x1f |
:+1: |
f32x4.replace_lane |
0x20 |
:+1: |
f64x2.extract_lane |
0x21 |
:+1: |
f64x2.replace_lane |
0x22 |
:+1: |
Integer Cmp |
Opcode |
Status |
i8x16.eq |
0x23 |
:+1: |
i8x16.ne |
0x24 |
:+1: |
i8x16.lt_s |
0x25 |
:+1: |
i8x16.lt_u |
0x26 |
:+1: |
i8x16.gt_s |
0x27 |
:+1: |
i8x16.gt_u |
0x28 |
:+1: |
i8x16.le_s |
0x29 |
:+1: |
i8x16.le_u |
0x2a |
:+1: |
i8x16.ge_s |
0x2b |
:+1: |
i8x16.ge_u |
0x2c |
:+1: |
i16x8.eq |
0x2d |
:+1: |
i16x8.ne |
0x2e |
:+1: |
i16x8.lt_s |
0x2f |
:+1: |
i16x8.lt_u |
0x30 |
:+1: |
i16x8.gt_s |
0x31 |
:+1: |
i16x8.gt_u |
0x32 |
:+1: |
i16x8.le_s |
0x33 |
:+1: |
i16x8.le_u |
0x34 |
:+1: |
i16x8.ge_s |
0x35 |
:+1: |
i16x8.ge_u |
0x36 |
:+1: |
i32x4.eq |
0x37 |
:+1: |
i32x4.ne |
0x38 |
:+1: |
i32x4.lt_s |
0x39 |
:+1: |
i32x4.lt_u |
0x3a |
:+1: |
i32x4.gt_s |
0x3b |
:+1: |
i32x4.gt_u |
0x3c |
:+1: |
i32x4.le_s |
0x3d |
:+1: |
i32x4.le_u |
0x3e |
:+1: |
i32x4.ge_s |
0x3f |
:+1: |
i32x4.ge_u |
0x40 |
:+1: |
v128 Op |
Opcode |
Status |
v128.not |
0x4d |
:+1: |
v128.and |
0x4e |
:+1: |
v128.andnot |
0x4f |
:+1: |
v128.or |
0x50 |
:+1: |
v128.xor |
0x51 |
:+1: |
v128.bitselect |
0x52 |
:+1: |
i8x16 Arith Op |
Opcode |
-- |
i8x16.abs |
0x60 |
:+1: |
i8x16.neg |
0x61 |
-- |
i8x16.any_true |
0x62 |
:+1: |
i8x16.all_true |
0x63 |
:+1: |
i8x16.bitmask |
0x64 |
:question: |
i8x16.narrow_i16x8_s |
0x65 |
-- |
i8x16.narrow_i16x8_u |
0x66 |
-- |
---- widen ---- |
0x67 |
-- |
---- widen ---- |
0x68 |
-- |
---- widen ---- |
0x69 |
-- |
---- widen ---- |
0x6a |
-- |
i8x16.shl |
0x6b |
:+1: |
i8x16.shr_s |
0x6c |
:+1: |
i8x16.shr_u |
0x6d |
:+1: |
i8x16.add |
0x6e |
-- |
i8x16.add_sat_s |
0x6f |
-- |
i8x16.add_sat_u |
0x70 |
-- |
i8x16.sub |
0x71 |
-- |
i8x16.sub_sat_s |
0x72 |
-- |
i8x16.sub_sat_u |
0x73 |
-- |
---- dot ---- |
0x74 |
-- |
---- mul ---- |
0x75 |
-- |
i8x16.min_s |
0x76 |
-- |
i8x16.min_u |
0x77 |
-- |
i8x16.max_s |
0x78 |
-- |
i8x16.max_u |
0x79 |
-- |
---- avgr_s ---- |
0x7a |
-- |
i8x16.avgr_u |
0x7b |
-- |
i16x8 Arith Op |
Opcode |
Status |
i16x8.abs |
0x80 |
:+1: |
i16x8.neg |
0x81 |
-- |
i16x8.any_true |
0x82 |
:+1: |
i16x8.all_true |
0x83 |
:+1: |
i16x8.bitmask |
0x84 |
:question: |
i16x8.narrow_i32x4_s |
0x85 |
-- |
i16x8.narrow_i32x4_u |
0x86 |
-- |
i16x8.widen_low_i8x16_s |
0x87 |
-- |
i16x8.widen_high_i8x16_s |
0x88 |
-- |
i16x8.widen_low_i8x16_u |
0x89 |
-- |
i16x8.widen_high_i8x16_u |
0x8a |
-- |
i16x8.shl |
0x8b |
:+1: |
i16x8.shr_s |
0x8c |
:+1: |
i16x8.shr_u |
0x8d |
:+1: |
i16x8.add |
0x8e |
-- |
i16x8.add_sat_s |
0x8f |
-- |
i16x8.add_sat_u |
0x90 |
-- |
i16x8.sub |
0x91 |
-- |
i16x8.sub_sat_s |
0x92 |
-- |
i16x8.sub_sat_u |
0x93 |
-- |
---- dot ---- |
0x94 |
-- |
i16x8.mul |
0x95 |
-- |
i16x8.min_s |
0x96 |
-- |
i16x8.min_u |
0x97 |
-- |
i16x8.max_s |
0x98 |
-- |
i16x8.max_u |
0x99 |
-- |
---- avgr_s ---- |
0x9a |
-- |
i16x8.avgr_u |
0x9b |
-- |
i32x4 Arith Op |
Opcode |
Status |
i32x4.abs |
0xa0 |
:+1: |
i32x4.neg |
0xa1 |
-- |
i32x4.any_true |
0xa2 |
:+1: |
i32x4.all_true |
0xa3 |
:+1: |
i32x4.bitmask |
0xa4 |
:question: |
---- narrow ---- |
0xa5 |
-- |
---- narrow ---- |
0xa6 |
-- |
i32x4.widen_low_i16x8_s |
0xa7 |
-- |
i32x4.widen_high_i16x8_s |
0xa8 |
-- |
i32x4.widen_low_i16x8_u |
0xa9 |
-- |
i32x4.widen_high_i16x8_u |
0xaa |
-- |
i32x4.shl |
0xab |
:+1: |
i32x4.shr_s |
0xac |
:+1: |
i32x4.shr_u |
0xad |
:+1: |
i32x4.add |
0xae |
-- |
---- add_sat ---- |
0xaf |
-- |
---- add_sat ---- |
0xb0 |
-- |
i32x4.sub |
0xb1 |
-- |
---- sub_sat ---- |
0xb2 |
-- |
---- sub_sat ---- |
0xb3 |
-- |
---- dot ---- |
0xb4 |
-- |
i32x4.mul |
0xb5 |
-- |
i32x4.min_s |
0xb6 |
-- |
i32x4.min_u |
0xb7 |
-- |
i32x4.max_s |
0xb8 |
-- |
i32x4.max_u |
0xb9 |
-- |
---- avgr_s ---- |
0xba |
-- |
---- avgr_u ---- |
0xbb |
-- |
i64x2 Arith Op |
Opcode |
Status |
---- |
0xc0 |
-- |
i64x2.neg |
0xc1 |
-- |
---- |
0xc2 |
-- |
---- |
0xc3 |
-- |
---- |
0xc4 |
-- |
---- |
0xc5 |
-- |
---- |
0xc6 |
-- |
---- |
0xc7 |
-- |
---- |
0xc8 |
-- |
---- |
0xc9 |
-- |
---- |
0xca |
-- |
i64x2.shl |
0xcb |
:+1: |
i64x2.shr_s |
0xcc |
:+1: |
i64x2.shr_u |
0xcd |
:+1: |
i64x2.add |
0xce |
-- |
---- |
0xcf |
-- |
---- |
0xd0 |
-- |
i64x2.sub |
0xd1 |
-- |
---- |
0xd2 |
-- |
---- |
0xd3 |
-- |
---- |
0xd4 |
-- |
i64x2.mul |
0xd5 |
-- |
---- |
0xd6 |
-- |
---- |
0xd7 |
-- |
---- |
0xd8 |
-- |
---- |
0xd9 |
-- |
---- |
0xda |
-- |
---- |
0xdb |
-- |
f32x4 Op |
Opcode |
Status |
f32x4.abs |
0xe0 |
-- |
f32x4.neg |
0xe1 |
-- |
---- round ---- |
0xe2 |
-- |
f32x4.sqrt |
0xe3 |
-- |
f32x4.add |
0xe4 |
-- |
f32x4.sub |
0xe5 |
-- |
f32x4.mul |
0xe6 |
-- |
f32x4.div |
0xe7 |
-- |
f32x4.min |
0xe8 |
-- |
f32x4.max |
0xe9 |
-- |
f32x4.pmin |
0xea |
-- |
f32x4.pmax |
0xeb |
-- |
f64x2 Op |
Opcode |
Status |
f64x2.abs |
0xec |
-- |
f64x2.neg |
0xed |
-- |
---- round ---- |
0xee |
-- |
f64x2.sqrt |
0xef |
-- |
f64x2.add |
0xf0 |
-- |
f64x2.sub |
0xf1 |
-- |
f64x2.mul |
0xf2 |
-- |
f64x2.div |
0xf3 |
-- |
f64x2.min |
0xf4 |
-- |
f64x2.max |
0xf5 |
-- |
f64x2.pmin |
0xf6 |
-- |
f64x2.pmax |
0xf7 |
-- |
Conversion Op |
Opcode |
Status |
i32x4.trunc_sat_f32x4_s |
0xf8 |
-- |
i32x4.trunc_sat_f32x4_u |
0xf9 |
-- |
f32x4.convert_i32x4_s |
0xfa |
-- |
f32x4.convert_i32x4_u |
0xfb |
-- |
jlb6740 edited Issue #2272:
Status: Currently Not Valid (Initial Status WIP)
Last Update: 10/8/2020
https://gist.github.com/jlb6740/0a495404f6b3cc901e1b8e5ae8148020
Loads |
Opcode |
Status |
v128.load |
0x00 |
:+1: |
v128.load8x8_s |
0x01 |
:+1: |
v128.load8x8_u |
0x02 |
:+1: |
v128.load16x4_s |
0x03 |
:+1: |
v128.load16x4_u |
0x04 |
:+1: |
v128.load32x2_s |
0x05 |
:+1: |
v128.load32x2_u |
0x06 |
:+1: |
v128.load8_splat |
0x07 |
:+1: |
v128.load16_splat |
0x08 |
:+1: |
v128.load32_splat |
0x09 |
:+1: |
v128.load64_splat |
0x0a |
:+1: |
Basic operation |
Opcode |
Status |
v128.const |
0x0c |
:+1: |
i8x16.shuffle |
0x0d |
:+1: |
i8x16.swizzle |
0x0e |
:+1: |
Splat operation |
Opcode |
Status |
i8x16.splat |
0x0f |
:+1: |
i16x8.splat |
0x10 |
:+1: |
i32x4.splat |
0x11 |
:+1: |
i64x2.splat |
0x12 |
:+1: |
f32x4.splat |
0x13 |
:+1: |
f64x2.splat |
0x14 |
:+1: |
Lane operation |
Opcode |
Status |
i8x16.extract_lane_s |
0x15 |
:+1: |
i8x16.extract_lane_u |
0x16 |
:+1: |
i8x16.replace_lane |
0x17 |
:+1: |
i16x8.extract_lane_s |
0x18 |
:+1: |
i16x8.extract_lane_u |
0x19 |
:+1: |
i16x8.replace_lane |
0x1a |
:+1: |
i32x4.extract_lane |
0x1b |
:+1: |
i32x4.replace_lane |
0x1c |
:+1: |
i64x2.extract_lane |
0x1d |
:+1: |
i64x2.replace_lane |
0x1e |
:+1: |
f32x4.extract_lane |
0x1f |
:+1: |
f32x4.replace_lane |
0x20 |
:+1: |
f64x2.extract_lane |
0x21 |
:+1: |
f64x2.replace_lane |
0x22 |
:+1: |
Integer Cmp |
Opcode |
Status |
i8x16.eq |
0x23 |
:+1: |
i8x16.ne |
0x24 |
:+1: |
i8x16.lt_s |
0x25 |
:+1: |
i8x16.lt_u |
0x26 |
:+1: |
i8x16.gt_s |
0x27 |
:+1: |
i8x16.gt_u |
0x28 |
:+1: |
i8x16.le_s |
0x29 |
:+1: |
i8x16.le_u |
0x2a |
:+1: |
i8x16.ge_s |
0x2b |
:+1: |
i8x16.ge_u |
0x2c |
:+1: |
i16x8.eq |
0x2d |
:+1: |
i16x8.ne |
0x2e |
:+1: |
i16x8.lt_s |
0x2f |
:+1: |
i16x8.lt_u |
0x30 |
:+1: |
i16x8.gt_s |
0x31 |
:+1: |
i16x8.gt_u |
0x32 |
:+1: |
i16x8.le_s |
0x33 |
:+1: |
i16x8.le_u |
0x34 |
:+1: |
i16x8.ge_s |
0x35 |
:+1: |
i16x8.ge_u |
0x36 |
:+1: |
i32x4.eq |
0x37 |
:+1: |
i32x4.ne |
0x38 |
:+1: |
i32x4.lt_s |
0x39 |
:+1: |
i32x4.lt_u |
0x3a |
:+1: |
i32x4.gt_s |
0x3b |
:+1: |
i32x4.gt_u |
0x3c |
:+1: |
i32x4.le_s |
0x3d |
:+1: |
i32x4.le_u |
0x3e |
:+1: |
i32x4.ge_s |
0x3f |
:+1: |
i32x4.ge_u |
0x40 |
:+1: |
v128 Op |
Opcode |
Status |
v128.not |
0x4d |
:+1: |
v128.and |
0x4e |
:+1: |
v128.andnot |
0x4f |
:+1: |
v128.or |
0x50 |
:+1: |
v128.xor |
0x51 |
:+1: |
v128.bitselect |
0x52 |
:+1: |
i8x16 Arith Op |
Opcode |
-- |
i8x16.abs |
0x60 |
:+1: |
i8x16.neg |
0x61 |
:+1: |
i8x16.any_true |
0x62 |
:+1: |
i8x16.all_true |
0x63 |
:+1: |
i8x16.bitmask |
0x64 |
:question: |
i8x16.narrow_i16x8_s |
0x65 |
-- |
i8x16.narrow_i16x8_u |
0x66 |
-- |
---- widen ---- |
0x67 |
-- |
---- widen ---- |
0x68 |
-- |
---- widen ---- |
0x69 |
-- |
---- widen ---- |
0x6a |
-- |
i8x16.shl |
0x6b |
:+1: |
i8x16.shr_s |
0x6c |
:+1: |
i8x16.shr_u |
0x6d |
:+1: |
i8x16.add |
0x6e |
-- |
i8x16.add_sat_s |
0x6f |
:+1: |
i8x16.add_sat_u |
0x70 |
:+1: |
i8x16.sub |
0x71 |
-- |
i8x16.sub_sat_s |
0x72 |
:+1: |
i8x16.sub_sat_u |
0x73 |
:+1: |
---- dot ---- |
0x74 |
-- |
---- mul ---- |
0x75 |
-- |
i8x16.min_s |
0x76 |
:+1: |
i8x16.min_u |
0x77 |
:+1: |
i8x16.max_s |
0x78 |
:+1: |
i8x16.max_u |
0x79 |
:+1: |
---- avgr_s ---- |
0x7a |
-- |
i8x16.avgr_u |
0x7b |
:+1: |
i16x8 Arith Op |
Opcode |
Status |
i16x8.abs |
0x80 |
:+1: |
i16x8.neg |
0x81 |
:+1: |
i16x8.any_true |
0x82 |
:+1: |
i16x8.all_true |
0x83 |
:+1: |
i16x8.bitmask |
0x84 |
:question: |
i16x8.narrow_i32x4_s |
0x85 |
-- |
i16x8.narrow_i32x4_u |
0x86 |
-- |
i16x8.widen_low_i8x16_s |
0x87 |
-- |
i16x8.widen_high_i8x16_s |
0x88 |
-- |
i16x8.widen_low_i8x16_u |
0x89 |
-- |
i16x8.widen_high_i8x16_u |
0x8a |
-- |
i16x8.shl |
0x8b |
:+1: |
i16x8.shr_s |
0x8c |
:+1: |
i16x8.shr_u |
0x8d |
:+1: |
i16x8.add |
0x8e |
-- |
i16x8.add_sat_s |
0x8f |
:+1: |
i16x8.add_sat_u |
0x90 |
:+1: |
i16x8.sub |
0x91 |
-- |
i16x8.sub_sat_s |
0x92 |
:+1: |
i16x8.sub_sat_u |
0x93 |
:+1: |
---- dot ---- |
0x94 |
-- |
i16x8.mul |
0x95 |
-- |
i16x8.min_s |
0x96 |
:+1: |
i16x8.min_u |
0x97 |
:+1: |
i16x8.max_s |
0x98 |
:+1: |
i16x8.max_u |
0x99 |
:+1: |
---- avgr_s ---- |
0x9a |
-- |
i16x8.avgr_u |
0x9b |
:+1: |
i32x4 Arith Op |
Opcode |
Status |
i32x4.abs |
0xa0 |
:+1: |
i32x4.neg |
0xa1 |
:+1: |
i32x4.any_true |
0xa2 |
:+1: |
i32x4.all_true |
0xa3 |
:+1: |
i32x4.bitmask |
0xa4 |
:question: |
---- narrow ---- |
0xa5 |
-- |
---- narrow ---- |
0xa6 |
-- |
i32x4.widen_low_i16x8_s |
0xa7 |
-- |
i32x4.widen_high_i16x8_s |
0xa8 |
-- |
i32x4.widen_low_i16x8_u |
0xa9 |
-- |
i32x4.widen_high_i16x8_u |
0xaa |
-- |
i32x4.shl |
0xab |
:+1: |
i32x4.shr_s |
0xac |
:+1: |
i32x4.shr_u |
0xad |
:+1: |
i32x4.add |
0xae |
-- |
---- add_sat ---- |
0xaf |
-- |
---- add_sat ---- |
0xb0 |
-- |
i32x4.sub |
0xb1 |
-- |
---- sub_sat ---- |
0xb2 |
-- |
---- sub_sat ---- |
0xb3 |
-- |
---- dot ---- |
0xb4 |
-- |
i32x4.mul |
0xb5 |
-- |
i32x4.min_s |
0xb6 |
:+1: |
i32x4.min_u |
0xb7 |
:+1: |
i32x4.max_s |
0xb8 |
:+1: |
i32x4.max_u |
0xb9 |
:+1: |
---- avgr_s ---- |
0xba |
-- |
---- avgr_u ---- |
0xbb |
-- |
i64x2 Arith Op |
Opcode |
Status |
---- |
0xc0 |
-- |
i64x2.neg |
0xc1 |
:+1: |
---- |
0xc2 |
-- |
---- |
0xc3 |
-- |
---- |
0xc4 |
-- |
---- |
0xc5 |
-- |
---- |
0xc6 |
-- |
---- |
0xc7 |
-- |
---- |
0xc8 |
-- |
---- |
0xc9 |
-- |
---- |
0xca |
-- |
i64x2.shl |
0xcb |
:+1: |
i64x2.shr_s |
0xcc |
:+1: |
i64x2.shr_u |
0xcd |
:+1: |
i64x2.add |
0xce |
-- |
---- |
0xcf |
-- |
---- |
0xd0 |
-- |
i64x2.sub |
0xd1 |
-- |
---- |
0xd2 |
-- |
---- |
0xd3 |
-- |
---- |
0xd4 |
-- |
i64x2.mul |
0xd5 |
-- |
---- |
0xd6 |
-- |
---- |
0xd7 |
-- |
---- |
0xd8 |
-- |
---- |
0xd9 |
-- |
---- |
0xda |
-- |
---- |
0xdb |
-- |
f32x4 Op |
Opcode |
Status |
f32x4.abs |
0xe0 |
-- |
f32x4.neg |
0xe1 |
-- |
---- round ---- |
0xe2 |
-- |
f32x4.sqrt |
0xe3 |
-- |
f32x4.add |
0xe4 |
-- |
f32x4.sub |
0xe5 |
-- |
f32x4.mul |
0xe6 |
-- |
f32x4.div |
0xe7 |
-- |
f32x4.min |
0xe8 |
-- |
f32x4.max |
0xe9 |
-- |
f32x4.pmin |
0xea |
-- |
f32x4.pmax |
0xeb |
-- |
f64x2 Op |
Opcode |
Status |
f64x2.abs |
0xec |
-- |
f64x2.neg |
0xed |
-- |
---- round ---- |
0xee |
-- |
f64x2.sqrt |
0xef |
-- |
f64x2.add |
0xf0 |
-- |
f64x2.sub |
0xf1 |
-- |
f64x2.mul |
0xf2 |
-- |
f64x2.div |
0xf3 |
-- |
f64x2.min |
0xf4 |
-- |
f64x2.max |
0xf5 |
-- |
f64x2.pmin |
0xf6 |
-- |
f64x2.pmax |
0xf7 |
-- |
Conversion Op |
Opcode |
Status |
i32x4.trunc_sat_f32x4_s |
0xf8 |
-- |
i32x4.trunc_sat_f32x4_u |
0xf9 |
-- |
f32x4.convert_i32x4_s |
0xfa |
-- |
f32x4.convert_i32x4_u |
0xfb |
-- |
jlb6740 edited Issue #2272:
Status: Currently Not Valid (Initial Status WIP)
Last Update: 10/8/2020
https://gist.github.com/jlb6740/0a495404f6b3cc901e1b8e5ae8148020
Loads |
Opcode |
Status |
v128.load |
0x00 |
:+1: |
v128.load8x8_s |
0x01 |
:+1: |
v128.load8x8_u |
0x02 |
:+1: |
v128.load16x4_s |
0x03 |
:+1: |
v128.load16x4_u |
0x04 |
:+1: |
v128.load32x2_s |
0x05 |
:+1: |
v128.load32x2_u |
0x06 |
:+1: |
v128.load8_splat |
0x07 |
:+1: |
v128.load16_splat |
0x08 |
:+1: |
v128.load32_splat |
0x09 |
:+1: |
v128.load64_splat |
0x0a |
:+1: |
Basic operation |
Opcode |
Status |
v128.const |
0x0c |
:+1: |
i8x16.shuffle |
0x0d |
:+1: |
i8x16.swizzle |
0x0e |
:+1: |
Splat operation |
Opcode |
Status |
i8x16.splat |
0x0f |
:+1: |
i16x8.splat |
0x10 |
:+1: |
i32x4.splat |
0x11 |
:+1: |
i64x2.splat |
0x12 |
:+1: |
f32x4.splat |
0x13 |
:+1: |
f64x2.splat |
0x14 |
:+1: |
Lane operation |
Opcode |
Status |
i8x16.extract_lane_s |
0x15 |
:+1: |
i8x16.extract_lane_u |
0x16 |
:+1: |
i8x16.replace_lane |
0x17 |
:+1: |
i16x8.extract_lane_s |
0x18 |
:+1: |
i16x8.extract_lane_u |
0x19 |
:+1: |
i16x8.replace_lane |
0x1a |
:+1: |
i32x4.extract_lane |
0x1b |
:+1: |
i32x4.replace_lane |
0x1c |
:+1: |
i64x2.extract_lane |
0x1d |
:+1: |
i64x2.replace_lane |
0x1e |
:+1: |
f32x4.extract_lane |
0x1f |
:+1: |
f32x4.replace_lane |
0x20 |
:+1: |
f64x2.extract_lane |
0x21 |
:+1: |
f64x2.replace_lane |
0x22 |
:+1: |
Integer Cmp |
Opcode |
Status |
i8x16.eq |
0x23 |
:+1: |
i8x16.ne |
0x24 |
:+1: |
i8x16.lt_s |
0x25 |
:+1: |
i8x16.lt_u |
0x26 |
:+1: |
i8x16.gt_s |
0x27 |
:+1: |
i8x16.gt_u |
0x28 |
:+1: |
i8x16.le_s |
0x29 |
:+1: |
i8x16.le_u |
0x2a |
:+1: |
i8x16.ge_s |
0x2b |
:+1: |
i8x16.ge_u |
0x2c |
:+1: |
i16x8.eq |
0x2d |
:+1: |
i16x8.ne |
0x2e |
:+1: |
i16x8.lt_s |
0x2f |
:+1: |
i16x8.lt_u |
0x30 |
:+1: |
i16x8.gt_s |
0x31 |
:+1: |
i16x8.gt_u |
0x32 |
:+1: |
i16x8.le_s |
0x33 |
:+1: |
i16x8.le_u |
0x34 |
:+1: |
i16x8.ge_s |
0x35 |
:+1: |
i16x8.ge_u |
0x36 |
:+1: |
i32x4.eq |
0x37 |
:+1: |
i32x4.ne |
0x38 |
:+1: |
i32x4.lt_s |
0x39 |
:+1: |
i32x4.lt_u |
0x3a |
:+1: |
i32x4.gt_s |
0x3b |
:+1: |
i32x4.gt_u |
0x3c |
:+1: |
i32x4.le_s |
0x3d |
:+1: |
i32x4.le_u |
0x3e |
:+1: |
i32x4.ge_s |
0x3f |
:+1: |
i32x4.ge_u |
0x40 |
:+1: |
v128 Op |
Opcode |
Status |
v128.not |
0x4d |
:+1: |
v128.and |
0x4e |
:+1: |
v128.andnot |
0x4f |
:+1: |
v128.or |
0x50 |
:+1: |
v128.xor |
0x51 |
:+1: |
v128.bitselect |
0x52 |
:+1: |
i8x16 Arith Op |
Opcode |
-- |
i8x16.abs |
0x60 |
:+1: |
i8x16.neg |
0x61 |
:+1: |
i8x16.any_true |
0x62 |
:+1: |
i8x16.all_true |
0x63 |
:+1: |
i8x16.bitmask |
0x64 |
:question: |
i8x16.narrow_i16x8_s |
0x65 |
-- |
i8x16.narrow_i16x8_u |
0x66 |
-- |
---- widen ---- |
0x67 |
-- |
---- widen ---- |
0x68 |
-- |
---- widen ---- |
0x69 |
-- |
---- widen ---- |
0x6a |
-- |
i8x16.shl |
0x6b |
:+1: |
i8x16.shr_s |
0x6c |
:+1: |
i8x16.shr_u |
0x6d |
:+1: |
i8x16.add |
0x6e |
:+1: |
i8x16.add_sat_s |
0x6f |
:+1: |
i8x16.add_sat_u |
0x70 |
:+1: |
i8x16.sub |
0x71 |
:+1: |
i8x16.sub_sat_s |
0x72 |
:+1: |
i8x16.sub_sat_u |
0x73 |
:+1: |
---- dot ---- |
0x74 |
-- |
---- mul ---- |
0x75 |
-- |
i8x16.min_s |
0x76 |
:+1: |
i8x16.min_u |
0x77 |
:+1: |
i8x16.max_s |
0x78 |
:+1: |
i8x16.max_u |
0x79 |
:+1: |
---- avgr_s ---- |
0x7a |
-- |
i8x16.avgr_u |
0x7b |
:+1: |
i16x8 Arith Op |
Opcode |
Status |
i16x8.abs |
0x80 |
:+1: |
i16x8.neg |
0x81 |
:+1: |
i16x8.any_true |
0x82 |
:+1: |
i16x8.all_true |
0x83 |
:+1: |
i16x8.bitmask |
0x84 |
:question: |
i16x8.narrow_i32x4_s |
0x85 |
-- |
i16x8.narrow_i32x4_u |
0x86 |
-- |
i16x8.widen_low_i8x16_s |
0x87 |
-- |
i16x8.widen_high_i8x16_s |
0x88 |
-- |
i16x8.widen_low_i8x16_u |
0x89 |
-- |
i16x8.widen_high_i8x16_u |
0x8a |
-- |
i16x8.shl |
0x8b |
:+1: |
i16x8.shr_s |
0x8c |
:+1: |
i16x8.shr_u |
0x8d |
:+1: |
i16x8.add |
0x8e |
:+1: |
i16x8.add_sat_s |
0x8f |
:+1: |
i16x8.add_sat_u |
0x90 |
:+1: |
i16x8.sub |
0x91 |
:+1: |
i16x8.sub_sat_s |
0x92 |
:+1: |
i16x8.sub_sat_u |
0x93 |
:+1: |
---- dot ---- |
0x94 |
-- |
i16x8.mul |
0x95 |
:+1: |
i16x8.min_s |
0x96 |
:+1: |
i16x8.min_u |
0x97 |
:+1: |
i16x8.max_s |
0x98 |
:+1: |
i16x8.max_u |
0x99 |
:+1: |
---- avgr_s ---- |
0x9a |
-- |
i16x8.avgr_u |
0x9b |
:+1: |
i32x4 Arith Op |
Opcode |
Status |
i32x4.abs |
0xa0 |
:+1: |
i32x4.neg |
0xa1 |
:+1: |
i32x4.any_true |
0xa2 |
:+1: |
i32x4.all_true |
0xa3 |
:+1: |
i32x4.bitmask |
0xa4 |
:question: |
---- narrow ---- |
0xa5 |
-- |
---- narrow ---- |
0xa6 |
-- |
i32x4.widen_low_i16x8_s |
0xa7 |
-- |
i32x4.widen_high_i16x8_s |
0xa8 |
-- |
i32x4.widen_low_i16x8_u |
0xa9 |
-- |
i32x4.widen_high_i16x8_u |
0xaa |
-- |
i32x4.shl |
0xab |
:+1: |
i32x4.shr_s |
0xac |
:+1: |
i32x4.shr_u |
0xad |
:+1: |
i32x4.add |
0xae |
:+1: |
---- add_sat ---- |
0xaf |
-- |
---- add_sat ---- |
0xb0 |
-- |
i32x4.sub |
0xb1 |
:+1: |
---- sub_sat ---- |
0xb2 |
-- |
---- sub_sat ---- |
0xb3 |
-- |
---- dot ---- |
0xb4 |
-- |
i32x4.mul |
0xb5 |
:+1: |
i32x4.min_s |
0xb6 |
:+1: |
i32x4.min_u |
0xb7 |
:+1: |
i32x4.max_s |
0xb8 |
:+1: |
i32x4.max_u |
0xb9 |
:+1: |
---- avgr_s ---- |
0xba |
-- |
---- avgr_u ---- |
0xbb |
-- |
i64x2 Arith Op |
Opcode |
Status |
---- |
0xc0 |
-- |
i64x2.neg |
0xc1 |
:+1: |
---- |
0xc2 |
-- |
---- |
0xc3 |
-- |
---- |
0xc4 |
-- |
---- |
0xc5 |
-- |
---- |
0xc6 |
-- |
---- |
0xc7 |
-- |
---- |
0xc8 |
-- |
---- |
0xc9 |
-- |
---- |
0xca |
-- |
i64x2.shl |
0xcb |
:+1: |
i64x2.shr_s |
0xcc |
:+1: |
i64x2.shr_u |
0xcd |
:+1: |
i64x2.add |
0xce |
-- |
---- |
0xcf |
-- |
---- |
0xd0 |
-- |
i64x2.sub |
0xd1 |
-- |
---- |
0xd2 |
-- |
---- |
0xd3 |
-- |
---- |
0xd4 |
-- |
i64x2.mul |
0xd5 |
-- |
---- |
0xd6 |
-- |
---- |
0xd7 |
-- |
---- |
0xd8 |
-- |
---- |
0xd9 |
-- |
---- |
0xda |
-- |
---- |
0xdb |
-- |
f32x4 Op |
Opcode |
Status |
f32x4.abs |
0xe0 |
-- |
f32x4.neg |
0xe1 |
-- |
---- round ---- |
0xe2 |
-- |
f32x4.sqrt |
0xe3 |
-- |
f32x4.add |
0xe4 |
-- |
f32x4.sub |
0xe5 |
-- |
f32x4.mul |
0xe6 |
-- |
f32x4.div |
0xe7 |
-- |
f32x4.min |
0xe8 |
-- |
f32x4.max |
0xe9 |
-- |
f32x4.pmin |
0xea |
-- |
f32x4.pmax |
0xeb |
-- |
f64x2 Op |
Opcode |
Status |
f64x2.abs |
0xec |
-- |
f64x2.neg |
0xed |
-- |
---- round ---- |
0xee |
-- |
f64x2.sqrt |
0xef |
-- |
f64x2.add |
0xf0 |
-- |
f64x2.sub |
0xf1 |
-- |
f64x2.mul |
0xf2 |
-- |
f64x2.div |
0xf3 |
-- |
f64x2.min |
0xf4 |
-- |
f64x2.max |
0xf5 |
-- |
f64x2.pmin |
0xf6 |
-- |
f64x2.pmax |
0xf7 |
-- |
Conversion Op |
Opcode |
Status |
i32x4.trunc_sat_f32x4_s |
0xf8 |
-- |
i32x4.trunc_sat_f32x4_u |
0xf9 |
-- |
f32x4.convert_i32x4_s |
0xfa |
-- |
f32x4.convert_i32x4_u |
0xfb |
-- |
jlb6740 edited Issue #2272:
Status: Currently Not Valid (Initial Status WIP)
Last Update: 10/8/2020
https://gist.github.com/jlb6740/0a495404f6b3cc901e1b8e5ae8148020
Loads |
Opcode |
Status |
v128.load |
0x00 |
:+1: |
v128.load8x8_s |
0x01 |
:+1: |
v128.load8x8_u |
0x02 |
:+1: |
v128.load16x4_s |
0x03 |
:+1: |
v128.load16x4_u |
0x04 |
:+1: |
v128.load32x2_s |
0x05 |
:+1: |
v128.load32x2_u |
0x06 |
:+1: |
v128.load8_splat |
0x07 |
:+1: |
v128.load16_splat |
0x08 |
:+1: |
v128.load32_splat |
0x09 |
:+1: |
v128.load64_splat |
0x0a |
:+1: |
Basic operation |
Opcode |
Status |
v128.const |
0x0c |
:+1: |
i8x16.shuffle |
0x0d |
:+1: |
i8x16.swizzle |
0x0e |
:+1: |
Splat operation |
Opcode |
Status |
i8x16.splat |
0x0f |
:+1: |
i16x8.splat |
0x10 |
:+1: |
i32x4.splat |
0x11 |
:+1: |
i64x2.splat |
0x12 |
:+1: |
f32x4.splat |
0x13 |
:+1: |
f64x2.splat |
0x14 |
:+1: |
Lane operation |
Opcode |
Status |
i8x16.extract_lane_s |
0x15 |
:+1: |
i8x16.extract_lane_u |
0x16 |
:+1: |
i8x16.replace_lane |
0x17 |
:+1: |
i16x8.extract_lane_s |
0x18 |
:+1: |
i16x8.extract_lane_u |
0x19 |
:+1: |
i16x8.replace_lane |
0x1a |
:+1: |
i32x4.extract_lane |
0x1b |
:+1: |
i32x4.replace_lane |
0x1c |
:+1: |
i64x2.extract_lane |
0x1d |
:+1: |
i64x2.replace_lane |
0x1e |
:+1: |
f32x4.extract_lane |
0x1f |
:+1: |
f32x4.replace_lane |
0x20 |
:+1: |
f64x2.extract_lane |
0x21 |
:+1: |
f64x2.replace_lane |
0x22 |
:+1: |
Integer Cmp |
Opcode |
Status |
i8x16.eq |
0x23 |
:+1: |
i8x16.ne |
0x24 |
:+1: |
i8x16.lt_s |
0x25 |
:+1: |
i8x16.lt_u |
0x26 |
:+1: |
i8x16.gt_s |
0x27 |
:+1: |
i8x16.gt_u |
0x28 |
:+1: |
i8x16.le_s |
0x29 |
:+1: |
i8x16.le_u |
0x2a |
:+1: |
i8x16.ge_s |
0x2b |
:+1: |
i8x16.ge_u |
0x2c |
:+1: |
i16x8.eq |
0x2d |
:+1: |
i16x8.ne |
0x2e |
:+1: |
i16x8.lt_s |
0x2f |
:+1: |
i16x8.lt_u |
0x30 |
:+1: |
i16x8.gt_s |
0x31 |
:+1: |
i16x8.gt_u |
0x32 |
:+1: |
i16x8.le_s |
0x33 |
:+1: |
i16x8.le_u |
0x34 |
:+1: |
i16x8.ge_s |
0x35 |
:+1: |
i16x8.ge_u |
0x36 |
:+1: |
i32x4.eq |
0x37 |
:+1: |
i32x4.ne |
0x38 |
:+1: |
i32x4.lt_s |
0x39 |
:+1: |
i32x4.lt_u |
0x3a |
:+1: |
i32x4.gt_s |
0x3b |
:+1: |
i32x4.gt_u |
0x3c |
:+1: |
i32x4.le_s |
0x3d |
:+1: |
i32x4.le_u |
0x3e |
:+1: |
i32x4.ge_s |
0x3f |
:+1: |
i32x4.ge_u |
0x40 |
:+1: |
v128 Op |
Opcode |
Status |
v128.not |
0x4d |
:+1: |
v128.and |
0x4e |
:+1: |
v128.andnot |
0x4f |
:+1: |
v128.or |
0x50 |
:+1: |
v128.xor |
0x51 |
:+1: |
v128.bitselect |
0x52 |
:+1: |
i8x16 Arith Op |
Opcode |
-- |
i8x16.abs |
0x60 |
:+1: |
i8x16.neg |
0x61 |
:+1: |
i8x16.any_true |
0x62 |
:+1: |
i8x16.all_true |
0x63 |
:+1: |
i8x16.bitmask |
0x64 |
:question: |
i8x16.narrow_i16x8_s |
0x65 |
-- |
i8x16.narrow_i16x8_u |
0x66 |
-- |
---- widen ---- |
0x67 |
-- |
---- widen ---- |
0x68 |
-- |
---- widen ---- |
0x69 |
-- |
---- widen ---- |
0x6a |
-- |
i8x16.shl |
0x6b |
:+1: |
i8x16.shr_s |
0x6c |
:+1: |
i8x16.shr_u |
0x6d |
:+1: |
i8x16.add |
0x6e |
:+1: |
i8x16.add_sat_s |
0x6f |
:+1: |
i8x16.add_sat_u |
0x70 |
:+1: |
i8x16.sub |
0x71 |
:+1: |
i8x16.sub_sat_s |
0x72 |
:+1: |
i8x16.sub_sat_u |
0x73 |
:+1: |
---- dot ---- |
0x74 |
-- |
---- mul ---- |
0x75 |
:+1: |
i8x16.min_s |
0x76 |
:+1: |
i8x16.min_u |
0x77 |
:+1: |
i8x16.max_s |
0x78 |
:+1: |
i8x16.max_u |
0x79 |
:+1: |
---- avgr_s ---- |
0x7a |
-- |
i8x16.avgr_u |
0x7b |
:+1: |
i16x8 Arith Op |
Opcode |
Status |
i16x8.abs |
0x80 |
:+1: |
i16x8.neg |
0x81 |
:+1: |
i16x8.any_true |
0x82 |
:+1: |
i16x8.all_true |
0x83 |
:+1: |
i16x8.bitmask |
0x84 |
:question: |
i16x8.narrow_i32x4_s |
0x85 |
-- |
i16x8.narrow_i32x4_u |
0x86 |
-- |
i16x8.widen_low_i8x16_s |
0x87 |
-- |
i16x8.widen_high_i8x16_s |
0x88 |
-- |
i16x8.widen_low_i8x16_u |
0x89 |
-- |
i16x8.widen_high_i8x16_u |
0x8a |
-- |
i16x8.shl |
0x8b |
:+1: |
i16x8.shr_s |
0x8c |
:+1: |
i16x8.shr_u |
0x8d |
:+1: |
i16x8.add |
0x8e |
:+1: |
i16x8.add_sat_s |
0x8f |
:+1: |
i16x8.add_sat_u |
0x90 |
:+1: |
i16x8.sub |
0x91 |
:+1: |
i16x8.sub_sat_s |
0x92 |
:+1: |
i16x8.sub_sat_u |
0x93 |
:+1: |
---- dot ---- |
0x94 |
-- |
i16x8.mul |
0x95 |
:+1: |
i16x8.min_s |
0x96 |
:+1: |
i16x8.min_u |
0x97 |
:+1: |
i16x8.max_s |
0x98 |
:+1: |
i16x8.max_u |
0x99 |
:+1: |
---- avgr_s ---- |
0x9a |
-- |
i16x8.avgr_u |
0x9b |
:+1: |
i32x4 Arith Op |
Opcode |
Status |
i32x4.abs |
0xa0 |
:+1: |
i32x4.neg |
0xa1 |
:+1: |
i32x4.any_true |
0xa2 |
:+1: |
i32x4.all_true |
0xa3 |
:+1: |
i32x4.bitmask |
0xa4 |
:question: |
---- narrow ---- |
0xa5 |
-- |
---- narrow ---- |
0xa6 |
-- |
i32x4.widen_low_i16x8_s |
0xa7 |
-- |
i32x4.widen_high_i16x8_s |
0xa8 |
-- |
i32x4.widen_low_i16x8_u |
0xa9 |
-- |
i32x4.widen_high_i16x8_u |
0xaa |
-- |
i32x4.shl |
0xab |
:+1: |
i32x4.shr_s |
0xac |
:+1: |
i32x4.shr_u |
0xad |
:+1: |
i32x4.add |
0xae |
:+1: |
---- add_sat ---- |
0xaf |
-- |
---- add_sat ---- |
0xb0 |
-- |
i32x4.sub |
0xb1 |
:+1: |
---- sub_sat ---- |
0xb2 |
-- |
---- sub_sat ---- |
0xb3 |
-- |
---- dot ---- |
0xb4 |
-- |
i32x4.mul |
0xb5 |
:+1: |
i32x4.min_s |
0xb6 |
:+1: |
i32x4.min_u |
0xb7 |
:+1: |
i32x4.max_s |
0xb8 |
:+1: |
i32x4.max_u |
0xb9 |
:+1: |
---- avgr_s ---- |
0xba |
-- |
---- avgr_u ---- |
0xbb |
-- |
i64x2 Arith Op |
Opcode |
Status |
---- |
0xc0 |
-- |
i64x2.neg |
0xc1 |
:+1: |
---- |
0xc2 |
-- |
---- |
0xc3 |
-- |
---- |
0xc4 |
-- |
---- |
0xc5 |
-- |
---- |
0xc6 |
-- |
---- |
0xc7 |
-- |
---- |
0xc8 |
-- |
---- |
0xc9 |
-- |
---- |
0xca |
-- |
i64x2.shl |
0xcb |
:+1: |
i64x2.shr_s |
0xcc |
:+1: |
i64x2.shr_u |
0xcd |
:+1: |
i64x2.add |
0xce |
-- |
---- |
0xcf |
-- |
---- |
0xd0 |
-- |
i64x2.sub |
0xd1 |
-- |
---- |
0xd2 |
-- |
---- |
0xd3 |
-- |
---- |
0xd4 |
-- |
i64x2.mul |
0xd5 |
-- |
---- |
0xd6 |
-- |
---- |
0xd7 |
-- |
---- |
0xd8 |
-- |
---- |
0xd9 |
-- |
---- |
0xda |
-- |
---- |
0xdb |
-- |
f32x4 Op |
Opcode |
Status |
f32x4.abs |
0xe0 |
-- |
f32x4.neg |
0xe1 |
-- |
---- round ---- |
0xe2 |
-- |
f32x4.sqrt |
0xe3 |
-- |
f32x4.add |
0xe4 |
-- |
f32x4.sub |
0xe5 |
-- |
f32x4.mul |
0xe6 |
-- |
f32x4.div |
0xe7 |
-- |
f32x4.min |
0xe8 |
-- |
f32x4.max |
0xe9 |
-- |
f32x4.pmin |
0xea |
-- |
f32x4.pmax |
0xeb |
-- |
f64x2 Op |
Opcode |
Status |
f64x2.abs |
0xec |
-- |
f64x2.neg |
0xed |
-- |
---- round ---- |
0xee |
-- |
f64x2.sqrt |
0xef |
-- |
f64x2.add |
0xf0 |
-- |
f64x2.sub |
0xf1 |
-- |
f64x2.mul |
0xf2 |
-- |
f64x2.div |
0xf3 |
-- |
f64x2.min |
0xf4 |
-- |
f64x2.max |
0xf5 |
-- |
f64x2.pmin |
0xf6 |
-- |
f64x2.pmax |
0xf7 |
-- |
Conversion Op |
Opcode |
Status |
i32x4.trunc_sat_f32x4_s |
0xf8 |
-- |
i32x4.trunc_sat_f32x4_u |
0xf9 |
-- |
f32x4.convert_i32x4_s |
0xfa |
-- |
f32x4.convert_i32x4_u |
0xfb |
-- |
jlb6740 edited Issue #2272:
Status: Currently Not Valid (Initial Status WIP)
Last Update: 10/8/2020
https://gist.github.com/jlb6740/0a495404f6b3cc901e1b8e5ae8148020
Loads |
Opcode |
Status |
v128.load |
0x00 |
:+1: |
v128.load8x8_s |
0x01 |
:+1: |
v128.load8x8_u |
0x02 |
:+1: |
v128.load16x4_s |
0x03 |
:+1: |
v128.load16x4_u |
0x04 |
:+1: |
v128.load32x2_s |
0x05 |
:+1: |
v128.load32x2_u |
0x06 |
:+1: |
v128.load8_splat |
0x07 |
:+1: |
v128.load16_splat |
0x08 |
:+1: |
v128.load32_splat |
0x09 |
:+1: |
v128.load64_splat |
0x0a |
:+1: |
Basic operation |
Opcode |
Status |
v128.const |
0x0c |
:+1: |
i8x16.shuffle |
0x0d |
:+1: |
i8x16.swizzle |
0x0e |
:+1: |
Splat operation |
Opcode |
Status |
i8x16.splat |
0x0f |
:+1: |
i16x8.splat |
0x10 |
:+1: |
i32x4.splat |
0x11 |
:+1: |
i64x2.splat |
0x12 |
:+1: |
f32x4.splat |
0x13 |
:+1: |
f64x2.splat |
0x14 |
:+1: |
Lane operation |
Opcode |
Status |
i8x16.extract_lane_s |
0x15 |
:+1: |
i8x16.extract_lane_u |
0x16 |
:+1: |
i8x16.replace_lane |
0x17 |
:+1: |
i16x8.extract_lane_s |
0x18 |
:+1: |
i16x8.extract_lane_u |
0x19 |
:+1: |
i16x8.replace_lane |
0x1a |
:+1: |
i32x4.extract_lane |
0x1b |
:+1: |
i32x4.replace_lane |
0x1c |
:+1: |
i64x2.extract_lane |
0x1d |
:+1: |
i64x2.replace_lane |
0x1e |
:+1: |
f32x4.extract_lane |
0x1f |
:+1: |
f32x4.replace_lane |
0x20 |
:+1: |
f64x2.extract_lane |
0x21 |
:+1: |
f64x2.replace_lane |
0x22 |
:+1: |
Integer Cmp |
Opcode |
Status |
i8x16.eq |
0x23 |
:+1: |
i8x16.ne |
0x24 |
:+1: |
i8x16.lt_s |
0x25 |
:+1: |
i8x16.lt_u |
0x26 |
:+1: |
i8x16.gt_s |
0x27 |
:+1: |
i8x16.gt_u |
0x28 |
:+1: |
i8x16.le_s |
0x29 |
:+1: |
i8x16.le_u |
0x2a |
:+1: |
i8x16.ge_s |
0x2b |
:+1: |
i8x16.ge_u |
0x2c |
:+1: |
i16x8.eq |
0x2d |
:+1: |
i16x8.ne |
0x2e |
:+1: |
i16x8.lt_s |
0x2f |
:+1: |
i16x8.lt_u |
0x30 |
:+1: |
i16x8.gt_s |
0x31 |
:+1: |
i16x8.gt_u |
0x32 |
:+1: |
i16x8.le_s |
0x33 |
:+1: |
i16x8.le_u |
0x34 |
:+1: |
i16x8.ge_s |
0x35 |
:+1: |
i16x8.ge_u |
0x36 |
:+1: |
i32x4.eq |
0x37 |
:+1: |
i32x4.ne |
0x38 |
:+1: |
i32x4.lt_s |
0x39 |
:+1: |
i32x4.lt_u |
0x3a |
:+1: |
i32x4.gt_s |
0x3b |
:+1: |
i32x4.gt_u |
0x3c |
:+1: |
i32x4.le_s |
0x3d |
:+1: |
i32x4.le_u |
0x3e |
:+1: |
i32x4.ge_s |
0x3f |
:+1: |
i32x4.ge_u |
0x40 |
:+1: |
v128 Op |
Opcode |
Status |
v128.not |
0x4d |
:+1: |
v128.and |
0x4e |
:+1: |
v128.andnot |
0x4f |
:+1: |
v128.or |
0x50 |
:+1: |
v128.xor |
0x51 |
:+1: |
v128.bitselect |
0x52 |
:+1: |
i8x16 Arith Op |
Opcode |
-- |
i8x16.abs |
0x60 |
:+1: |
i8x16.neg |
0x61 |
:+1: |
i8x16.any_true |
0x62 |
:+1: |
i8x16.all_true |
0x63 |
:+1: |
i8x16.bitmask |
0x64 |
:question: |
i8x16.narrow_i16x8_s |
0x65 |
-- |
i8x16.narrow_i16x8_u |
0x66 |
-- |
---- widen ---- |
0x67 |
-- |
---- widen ---- |
0x68 |
-- |
---- widen ---- |
0x69 |
-- |
---- widen ---- |
0x6a |
-- |
i8x16.shl |
0x6b |
:+1: |
i8x16.shr_s |
0x6c |
:+1: |
i8x16.shr_u |
0x6d |
:+1: |
i8x16.add |
0x6e |
:+1: |
i8x16.add_sat_s |
0x6f |
:+1: |
i8x16.add_sat_u |
0x70 |
:+1: |
i8x16.sub |
0x71 |
:+1: |
i8x16.sub_sat_s |
0x72 |
:+1: |
i8x16.sub_sat_u |
0x73 |
:+1: |
---- dot ---- |
0x74 |
-- |
---- mul ---- |
0x75 |
:question: |
i8x16.min_s |
0x76 |
:+1: |
i8x16.min_u |
0x77 |
:+1: |
i8x16.max_s |
0x78 |
:+1: |
i8x16.max_u |
0x79 |
:+1: |
---- avgr_s ---- |
0x7a |
-- |
i8x16.avgr_u |
0x7b |
:+1: |
i16x8 Arith Op |
Opcode |
Status |
i16x8.abs |
0x80 |
:+1: |
i16x8.neg |
0x81 |
:+1: |
i16x8.any_true |
0x82 |
:+1: |
i16x8.all_true |
0x83 |
:+1: |
i16x8.bitmask |
0x84 |
:question: |
i16x8.narrow_i32x4_s |
0x85 |
-- |
i16x8.narrow_i32x4_u |
0x86 |
-- |
i16x8.widen_low_i8x16_s |
0x87 |
-- |
i16x8.widen_high_i8x16_s |
0x88 |
-- |
i16x8.widen_low_i8x16_u |
0x89 |
-- |
i16x8.widen_high_i8x16_u |
0x8a |
-- |
i16x8.shl |
0x8b |
:+1: |
i16x8.shr_s |
0x8c |
:+1: |
i16x8.shr_u |
0x8d |
:+1: |
i16x8.add |
0x8e |
:+1: |
i16x8.add_sat_s |
0x8f |
:+1: |
i16x8.add_sat_u |
0x90 |
:+1: |
i16x8.sub |
0x91 |
:+1: |
i16x8.sub_sat_s |
0x92 |
:+1: |
i16x8.sub_sat_u |
0x93 |
:+1: |
---- dot ---- |
0x94 |
-- |
i16x8.mul |
0x95 |
:+1: |
i16x8.min_s |
0x96 |
:+1: |
i16x8.min_u |
0x97 |
:+1: |
i16x8.max_s |
0x98 |
:+1: |
i16x8.max_u |
0x99 |
:+1: |
---- avgr_s ---- |
0x9a |
-- |
i16x8.avgr_u |
0x9b |
:+1: |
i32x4 Arith Op |
Opcode |
Status |
i32x4.abs |
0xa0 |
:+1: |
i32x4.neg |
0xa1 |
:+1: |
i32x4.any_true |
0xa2 |
:+1: |
i32x4.all_true |
0xa3 |
:+1: |
i32x4.bitmask |
0xa4 |
:question: |
---- narrow ---- |
0xa5 |
-- |
---- narrow ---- |
0xa6 |
-- |
i32x4.widen_low_i16x8_s |
0xa7 |
-- |
i32x4.widen_high_i16x8_s |
0xa8 |
-- |
i32x4.widen_low_i16x8_u |
0xa9 |
-- |
i32x4.widen_high_i16x8_u |
0xaa |
-- |
i32x4.shl |
0xab |
:+1: |
i32x4.shr_s |
0xac |
:+1: |
i32x4.shr_u |
0xad |
:+1: |
i32x4.add |
0xae |
:+1: |
---- add_sat ---- |
0xaf |
-- |
---- add_sat ---- |
0xb0 |
-- |
i32x4.sub |
0xb1 |
:+1: |
---- sub_sat ---- |
0xb2 |
-- |
---- sub_sat ---- |
0xb3 |
-- |
---- dot ---- |
0xb4 |
-- |
i32x4.mul |
0xb5 |
:+1: |
i32x4.min_s |
0xb6 |
:+1: |
i32x4.min_u |
0xb7 |
:+1: |
i32x4.max_s |
0xb8 |
:+1: |
i32x4.max_u |
0xb9 |
:+1: |
---- avgr_s ---- |
0xba |
-- |
---- avgr_u ---- |
0xbb |
-- |
i64x2 Arith Op |
Opcode |
Status |
---- |
0xc0 |
-- |
i64x2.neg |
0xc1 |
:+1: |
---- |
0xc2 |
-- |
---- |
0xc3 |
-- |
---- |
0xc4 |
-- |
---- |
0xc5 |
-- |
---- |
0xc6 |
-- |
---- |
0xc7 |
-- |
---- |
0xc8 |
-- |
---- |
0xc9 |
-- |
---- |
0xca |
-- |
i64x2.shl |
0xcb |
:+1: |
i64x2.shr_s |
0xcc |
:+1: |
i64x2.shr_u |
0xcd |
:+1: |
i64x2.add |
0xce |
-- |
---- |
0xcf |
-- |
---- |
0xd0 |
-- |
i64x2.sub |
0xd1 |
-- |
---- |
0xd2 |
-- |
---- |
0xd3 |
-- |
---- |
0xd4 |
-- |
i64x2.mul |
0xd5 |
-- |
---- |
0xd6 |
-- |
---- |
0xd7 |
-- |
---- |
0xd8 |
-- |
---- |
0xd9 |
-- |
---- |
0xda |
-- |
---- |
0xdb |
-- |
f32x4 Op |
Opcode |
Status |
f32x4.abs |
0xe0 |
-- |
f32x4.neg |
0xe1 |
-- |
---- round ---- |
0xe2 |
-- |
f32x4.sqrt |
0xe3 |
-- |
f32x4.add |
0xe4 |
-- |
f32x4.sub |
0xe5 |
-- |
f32x4.mul |
0xe6 |
-- |
f32x4.div |
0xe7 |
-- |
f32x4.min |
0xe8 |
-- |
f32x4.max |
0xe9 |
-- |
f32x4.pmin |
0xea |
-- |
f32x4.pmax |
0xeb |
-- |
f64x2 Op |
Opcode |
Status |
f64x2.abs |
0xec |
-- |
f64x2.neg |
0xed |
-- |
---- round ---- |
0xee |
-- |
f64x2.sqrt |
0xef |
-- |
f64x2.add |
0xf0 |
-- |
f64x2.sub |
0xf1 |
-- |
f64x2.mul |
0xf2 |
-- |
f64x2.div |
0xf3 |
-- |
f64x2.min |
0xf4 |
-- |
f64x2.max |
0xf5 |
-- |
f64x2.pmin |
0xf6 |
-- |
f64x2.pmax |
0xf7 |
-- |
Conversion Op |
Opcode |
Status |
i32x4.trunc_sat_f32x4_s |
0xf8 |
-- |
i32x4.trunc_sat_f32x4_u |
0xf9 |
-- |
f32x4.convert_i32x4_s |
0xfa |
-- |
f32x4.convert_i32x4_u |
0xfb |
-- |
jlb6740 edited Issue #2272:
Status: Currently Not Valid (Initial Status WIP)
Last Update: 10/8/2020
https://gist.github.com/jlb6740/0a495404f6b3cc901e1b8e5ae8148020
Loads |
Opcode |
Status |
v128.load |
0x00 |
:+1: |
v128.load8x8_s |
0x01 |
:+1: |
v128.load8x8_u |
0x02 |
:+1: |
v128.load16x4_s |
0x03 |
:+1: |
v128.load16x4_u |
0x04 |
:+1: |
v128.load32x2_s |
0x05 |
:+1: |
v128.load32x2_u |
0x06 |
:+1: |
v128.load8_splat |
0x07 |
:+1: |
v128.load16_splat |
0x08 |
:+1: |
v128.load32_splat |
0x09 |
:+1: |
v128.load64_splat |
0x0a |
:+1: |
Basic operation |
Opcode |
Status |
v128.const |
0x0c |
:+1: |
i8x16.shuffle |
0x0d |
:+1: |
i8x16.swizzle |
0x0e |
:+1: |
Splat operation |
Opcode |
Status |
i8x16.splat |
0x0f |
:+1: |
i16x8.splat |
0x10 |
:+1: |
i32x4.splat |
0x11 |
:+1: |
i64x2.splat |
0x12 |
:+1: |
f32x4.splat |
0x13 |
:+1: |
f64x2.splat |
0x14 |
:+1: |
Lane operation |
Opcode |
Status |
i8x16.extract_lane_s |
0x15 |
:+1: |
i8x16.extract_lane_u |
0x16 |
:+1: |
i8x16.replace_lane |
0x17 |
:+1: |
i16x8.extract_lane_s |
0x18 |
:+1: |
i16x8.extract_lane_u |
0x19 |
:+1: |
i16x8.replace_lane |
0x1a |
:+1: |
i32x4.extract_lane |
0x1b |
:+1: |
i32x4.replace_lane |
0x1c |
:+1: |
i64x2.extract_lane |
0x1d |
:+1: |
i64x2.replace_lane |
0x1e |
:+1: |
f32x4.extract_lane |
0x1f |
:+1: |
f32x4.replace_lane |
0x20 |
:+1: |
f64x2.extract_lane |
0x21 |
:+1: |
f64x2.replace_lane |
0x22 |
:+1: |
Integer Cmp |
Opcode |
Status |
i8x16.eq |
0x23 |
:+1: |
i8x16.ne |
0x24 |
:+1: |
i8x16.lt_s |
0x25 |
:+1: |
i8x16.lt_u |
0x26 |
:+1: |
i8x16.gt_s |
0x27 |
:+1: |
i8x16.gt_u |
0x28 |
:+1: |
i8x16.le_s |
0x29 |
:+1: |
i8x16.le_u |
0x2a |
:+1: |
i8x16.ge_s |
0x2b |
:+1: |
i8x16.ge_u |
0x2c |
:+1: |
i16x8.eq |
0x2d |
:+1: |
i16x8.ne |
0x2e |
:+1: |
i16x8.lt_s |
0x2f |
:+1: |
i16x8.lt_u |
0x30 |
:+1: |
i16x8.gt_s |
0x31 |
:+1: |
i16x8.gt_u |
0x32 |
:+1: |
i16x8.le_s |
0x33 |
:+1: |
i16x8.le_u |
0x34 |
:+1: |
i16x8.ge_s |
0x35 |
:+1: |
i16x8.ge_u |
0x36 |
:+1: |
i32x4.eq |
0x37 |
:+1: |
i32x4.ne |
0x38 |
:+1: |
i32x4.lt_s |
0x39 |
:+1: |
i32x4.lt_u |
0x3a |
:+1: |
i32x4.gt_s |
0x3b |
:+1: |
i32x4.gt_u |
0x3c |
:+1: |
i32x4.le_s |
0x3d |
:+1: |
i32x4.le_u |
0x3e |
:+1: |
i32x4.ge_s |
0x3f |
:+1: |
i32x4.ge_u |
0x40 |
:+1: |
v128 Op |
Opcode |
Status |
v128.not |
0x4d |
:+1: |
v128.and |
0x4e |
:+1: |
v128.andnot |
0x4f |
:+1: |
v128.or |
0x50 |
:+1: |
v128.xor |
0x51 |
:+1: |
v128.bitselect |
0x52 |
:+1: |
i8x16 Arith Op |
Opcode |
-- |
i8x16.abs |
0x60 |
:+1: |
i8x16.neg |
0x61 |
:+1: |
i8x16.any_true |
0x62 |
:+1: |
i8x16.all_true |
0x63 |
:+1: |
i8x16.bitmask |
0x64 |
:question: |
i8x16.narrow_i16x8_s |
0x65 |
-- |
i8x16.narrow_i16x8_u |
0x66 |
-- |
---- widen ---- |
0x67 |
-- |
---- widen ---- |
0x68 |
-- |
---- widen ---- |
0x69 |
-- |
---- widen ---- |
0x6a |
-- |
i8x16.shl |
0x6b |
:+1: |
i8x16.shr_s |
0x6c |
:+1: |
i8x16.shr_u |
0x6d |
:+1: |
i8x16.add |
0x6e |
:+1: |
i8x16.add_sat_s |
0x6f |
:+1: |
i8x16.add_sat_u |
0x70 |
:+1: |
i8x16.sub |
0x71 |
:+1: |
i8x16.sub_sat_s |
0x72 |
:+1: |
i8x16.sub_sat_u |
0x73 |
:+1: |
---- dot ---- |
0x74 |
-- |
---- mul ---- |
0x75 |
:question: |
i8x16.min_s |
0x76 |
:+1: |
i8x16.min_u |
0x77 |
:+1: |
i8x16.max_s |
0x78 |
:+1: |
i8x16.max_u |
0x79 |
:+1: |
---- avgr_s ---- |
0x7a |
-- |
i8x16.avgr_u |
0x7b |
:+1: |
i16x8 Arith Op |
Opcode |
Status |
i16x8.abs |
0x80 |
:+1: |
i16x8.neg |
0x81 |
:+1: |
i16x8.any_true |
0x82 |
:+1: |
i16x8.all_true |
0x83 |
:+1: |
i16x8.bitmask |
0x84 |
:question: |
i16x8.narrow_i32x4_s |
0x85 |
-- |
i16x8.narrow_i32x4_u |
0x86 |
-- |
i16x8.widen_low_i8x16_s |
0x87 |
-- |
i16x8.widen_high_i8x16_s |
0x88 |
-- |
i16x8.widen_low_i8x16_u |
0x89 |
-- |
i16x8.widen_high_i8x16_u |
0x8a |
-- |
i16x8.shl |
0x8b |
:+1: |
i16x8.shr_s |
0x8c |
:+1: |
i16x8.shr_u |
0x8d |
:+1: |
i16x8.add |
0x8e |
:+1: |
i16x8.add_sat_s |
0x8f |
:+1: |
i16x8.add_sat_u |
0x90 |
:+1: |
i16x8.sub |
0x91 |
:+1: |
i16x8.sub_sat_s |
0x92 |
:+1: |
i16x8.sub_sat_u |
0x93 |
:+1: |
---- dot ---- |
0x94 |
-- |
i16x8.mul |
0x95 |
:+1: |
i16x8.min_s |
0x96 |
:+1: |
i16x8.min_u |
0x97 |
:+1: |
i16x8.max_s |
0x98 |
:+1: |
i16x8.max_u |
0x99 |
:+1: |
---- avgr_s ---- |
0x9a |
-- |
i16x8.avgr_u |
0x9b |
:+1: |
i32x4 Arith Op |
Opcode |
Status |
i32x4.abs |
0xa0 |
:+1: |
i32x4.neg |
0xa1 |
:+1: |
i32x4.any_true |
0xa2 |
:+1: |
i32x4.all_true |
0xa3 |
:+1: |
i32x4.bitmask |
0xa4 |
:question: |
---- narrow ---- |
0xa5 |
-- |
---- narrow ---- |
0xa6 |
-- |
i32x4.widen_low_i16x8_s |
0xa7 |
-- |
i32x4.widen_high_i16x8_s |
0xa8 |
-- |
i32x4.widen_low_i16x8_u |
0xa9 |
-- |
i32x4.widen_high_i16x8_u |
0xaa |
-- |
i32x4.shl |
0xab |
:+1: |
i32x4.shr_s |
0xac |
:+1: |
i32x4.shr_u |
0xad |
:+1: |
i32x4.add |
0xae |
:+1: |
---- add_sat ---- |
0xaf |
-- |
---- add_sat ---- |
0xb0 |
-- |
i32x4.sub |
0xb1 |
:+1: |
---- sub_sat ---- |
0xb2 |
-- |
---- sub_sat ---- |
0xb3 |
-- |
---- dot ---- |
0xb4 |
-- |
i32x4.mul |
0xb5 |
:+1: |
i32x4.min_s |
0xb6 |
:+1: |
i32x4.min_u |
0xb7 |
:+1: |
i32x4.max_s |
0xb8 |
:+1: |
i32x4.max_u |
0xb9 |
:+1: |
---- avgr_s ---- |
0xba |
-- |
---- avgr_u ---- |
0xbb |
-- |
i64x2 Arith Op |
Opcode |
Status |
---- |
0xc0 |
-- |
i64x2.neg |
0xc1 |
:+1: |
---- |
0xc2 |
-- |
---- |
0xc3 |
-- |
---- |
0xc4 |
-- |
---- |
0xc5 |
-- |
---- |
0xc6 |
-- |
---- |
0xc7 |
-- |
---- |
0xc8 |
-- |
---- |
0xc9 |
-- |
---- |
0xca |
-- |
i64x2.shl |
0xcb |
:+1: |
i64x2.shr_s |
0xcc |
:+1: |
i64x2.shr_u |
0xcd |
:+1: |
i64x2.add |
0xce |
:+1: |
---- |
0xcf |
-- |
---- |
0xd0 |
-- |
i64x2.sub |
0xd1 |
:+1: |
---- |
0xd2 |
-- |
---- |
0xd3 |
-- |
---- |
0xd4 |
-- |
i64x2.mul |
0xd5 |
:+1: |
---- |
0xd6 |
-- |
---- |
0xd7 |
-- |
---- |
0xd8 |
-- |
---- |
0xd9 |
-- |
---- |
0xda |
-- |
---- |
0xdb |
-- |
f32x4 Op |
Opcode |
Status |
f32x4.abs |
0xe0 |
-- |
f32x4.neg |
0xe1 |
-- |
---- round ---- |
0xe2 |
-- |
f32x4.sqrt |
0xe3 |
-- |
f32x4.add |
0xe4 |
-- |
f32x4.sub |
0xe5 |
-- |
f32x4.mul |
0xe6 |
-- |
f32x4.div |
0xe7 |
-- |
f32x4.min |
0xe8 |
-- |
f32x4.max |
0xe9 |
-- |
f32x4.pmin |
0xea |
-- |
f32x4.pmax |
0xeb |
-- |
f64x2 Op |
Opcode |
Status |
f64x2.abs |
0xec |
-- |
f64x2.neg |
0xed |
-- |
---- round ---- |
0xee |
-- |
f64x2.sqrt |
0xef |
-- |
f64x2.add |
0xf0 |
-- |
f64x2.sub |
0xf1 |
-- |
f64x2.mul |
0xf2 |
-- |
f64x2.div |
0xf3 |
-- |
f64x2.min |
0xf4 |
-- |
f64x2.max |
0xf5 |
-- |
f64x2.pmin |
0xf6 |
-- |
f64x2.pmax |
0xf7 |
-- |
Conversion Op |
Opcode |
Status |
i32x4.trunc_sat_f32x4_s |
0xf8 |
-- |
i32x4.trunc_sat_f32x4_u |
0xf9 |
-- |
f32x4.convert_i32x4_s |
0xfa |
-- |
f32x4.convert_i32x4_u |
0xfb |
-- |
jlb6740 edited Issue #2272:
Status: Currently Not Valid (Initial Status WIP)
Last Update: 10/8/2020
https://gist.github.com/jlb6740/0a495404f6b3cc901e1b8e5ae8148020
Loads |
Opcode |
Status |
v128.load |
0x00 |
:+1: |
v128.load8x8_s |
0x01 |
:+1: |
v128.load8x8_u |
0x02 |
:+1: |
v128.load16x4_s |
0x03 |
:+1: |
v128.load16x4_u |
0x04 |
:+1: |
v128.load32x2_s |
0x05 |
:+1: |
v128.load32x2_u |
0x06 |
:+1: |
v128.load8_splat |
0x07 |
:+1: |
v128.load16_splat |
0x08 |
:+1: |
v128.load32_splat |
0x09 |
:+1: |
v128.load64_splat |
0x0a |
:+1: |
Basic operation |
Opcode |
Status |
v128.const |
0x0c |
:+1: |
i8x16.shuffle |
0x0d |
:+1: |
i8x16.swizzle |
0x0e |
:+1: |
Splat operation |
Opcode |
Status |
i8x16.splat |
0x0f |
:+1: |
i16x8.splat |
0x10 |
:+1: |
i32x4.splat |
0x11 |
:+1: |
i64x2.splat |
0x12 |
:+1: |
f32x4.splat |
0x13 |
:+1: |
f64x2.splat |
0x14 |
:+1: |
Lane operation |
Opcode |
Status |
i8x16.extract_lane_s |
0x15 |
:+1: |
i8x16.extract_lane_u |
0x16 |
:+1: |
i8x16.replace_lane |
0x17 |
:+1: |
i16x8.extract_lane_s |
0x18 |
:+1: |
i16x8.extract_lane_u |
0x19 |
:+1: |
i16x8.replace_lane |
0x1a |
:+1: |
i32x4.extract_lane |
0x1b |
:+1: |
i32x4.replace_lane |
0x1c |
:+1: |
i64x2.extract_lane |
0x1d |
:+1: |
i64x2.replace_lane |
0x1e |
:+1: |
f32x4.extract_lane |
0x1f |
:+1: |
f32x4.replace_lane |
0x20 |
:+1: |
f64x2.extract_lane |
0x21 |
:+1: |
f64x2.replace_lane |
0x22 |
:+1: |
Integer Cmp |
Opcode |
Status |
i8x16.eq |
0x23 |
:+1: |
i8x16.ne |
0x24 |
:+1: |
i8x16.lt_s |
0x25 |
:+1: |
i8x16.lt_u |
0x26 |
:+1: |
i8x16.gt_s |
0x27 |
:+1: |
i8x16.gt_u |
0x28 |
:+1: |
i8x16.le_s |
0x29 |
:+1: |
i8x16.le_u |
0x2a |
:+1: |
i8x16.ge_s |
0x2b |
:+1: |
i8x16.ge_u |
0x2c |
:+1: |
i16x8.eq |
0x2d |
:+1: |
i16x8.ne |
0x2e |
:+1: |
i16x8.lt_s |
0x2f |
:+1: |
i16x8.lt_u |
0x30 |
:+1: |
i16x8.gt_s |
0x31 |
:+1: |
i16x8.gt_u |
0x32 |
:+1: |
i16x8.le_s |
0x33 |
:+1: |
i16x8.le_u |
0x34 |
:+1: |
i16x8.ge_s |
0x35 |
:+1: |
i16x8.ge_u |
0x36 |
:+1: |
i32x4.eq |
0x37 |
:+1: |
i32x4.ne |
0x38 |
:+1: |
i32x4.lt_s |
0x39 |
:+1: |
i32x4.lt_u |
0x3a |
:+1: |
i32x4.gt_s |
0x3b |
:+1: |
i32x4.gt_u |
0x3c |
:+1: |
i32x4.le_s |
0x3d |
:+1: |
i32x4.le_u |
0x3e |
:+1: |
i32x4.ge_s |
0x3f |
:+1: |
i32x4.ge_u |
0x40 |
:+1: |
v128 Op |
Opcode |
Status |
v128.not |
0x4d |
:+1: |
v128.and |
0x4e |
:+1: |
v128.andnot |
0x4f |
:+1: |
v128.or |
0x50 |
:+1: |
v128.xor |
0x51 |
:+1: |
v128.bitselect |
0x52 |
:+1: |
i8x16 Arith Op |
Opcode |
-- |
i8x16.abs |
0x60 |
:+1: |
i8x16.neg |
0x61 |
:+1: |
i8x16.any_true |
0x62 |
:+1: |
i8x16.all_true |
0x63 |
:+1: |
i8x16.bitmask |
0x64 |
:question: |
i8x16.narrow_i16x8_s |
0x65 |
:+1: |
i8x16.narrow_i16x8_u |
0x66 |
:+1: |
---- widen ---- |
0x67 |
-- |
---- widen ---- |
0x68 |
-- |
---- widen ---- |
0x69 |
-- |
---- widen ---- |
0x6a |
-- |
i8x16.shl |
0x6b |
:+1: |
i8x16.shr_s |
0x6c |
:+1: |
i8x16.shr_u |
0x6d |
:+1: |
i8x16.add |
0x6e |
:+1: |
i8x16.add_sat_s |
0x6f |
:+1: |
i8x16.add_sat_u |
0x70 |
:+1: |
i8x16.sub |
0x71 |
:+1: |
i8x16.sub_sat_s |
0x72 |
:+1: |
i8x16.sub_sat_u |
0x73 |
:+1: |
---- dot ---- |
0x74 |
-- |
---- mul ---- |
0x75 |
:question: |
i8x16.min_s |
0x76 |
:+1: |
i8x16.min_u |
0x77 |
:+1: |
i8x16.max_s |
0x78 |
:+1: |
i8x16.max_u |
0x79 |
:+1: |
---- avgr_s ---- |
0x7a |
-- |
i8x16.avgr_u |
0x7b |
:+1: |
i16x8 Arith Op |
Opcode |
Status |
i16x8.abs |
0x80 |
:+1: |
i16x8.neg |
0x81 |
:+1: |
i16x8.any_true |
0x82 |
:+1: |
i16x8.all_true |
0x83 |
:+1: |
i16x8.bitmask |
0x84 |
:question: |
i16x8.narrow_i32x4_s |
0x85 |
:+1: |
i16x8.narrow_i32x4_u |
0x86 |
:+1: |
i16x8.widen_low_i8x16_s |
0x87 |
:+1: |
i16x8.widen_high_i8x16_s |
0x88 |
:+1: |
i16x8.widen_low_i8x16_u |
0x89 |
:+1: |
i16x8.widen_high_i8x16_u |
0x8a |
:+1: |
i16x8.shl |
0x8b |
:+1: |
i16x8.shr_s |
0x8c |
:+1: |
i16x8.shr_u |
0x8d |
:+1: |
i16x8.add |
0x8e |
:+1: |
i16x8.add_sat_s |
0x8f |
:+1: |
i16x8.add_sat_u |
0x90 |
:+1: |
i16x8.sub |
0x91 |
:+1: |
i16x8.sub_sat_s |
0x92 |
:+1: |
i16x8.sub_sat_u |
0x93 |
:+1: |
---- dot ---- |
0x94 |
-- |
i16x8.mul |
0x95 |
:+1: |
i16x8.min_s |
0x96 |
:+1: |
i16x8.min_u |
0x97 |
:+1: |
i16x8.max_s |
0x98 |
:+1: |
i16x8.max_u |
0x99 |
:+1: |
---- avgr_s ---- |
0x9a |
-- |
i16x8.avgr_u |
0x9b |
:+1: |
i32x4 Arith Op |
Opcode |
Status |
i32x4.abs |
0xa0 |
:+1: |
i32x4.neg |
0xa1 |
:+1: |
i32x4.any_true |
0xa2 |
:+1: |
i32x4.all_true |
0xa3 |
:+1: |
i32x4.bitmask |
0xa4 |
:question: |
---- narrow ---- |
0xa5 |
-- |
---- narrow ---- |
0xa6 |
-- |
i32x4.widen_low_i16x8_s |
0xa7 |
:+1: |
i32x4.widen_high_i16x8_s |
0xa8 |
:+1: |
i32x4.widen_low_i16x8_u |
0xa9 |
:+1: |
i32x4.widen_high_i16x8_u |
0xaa |
:+1: |
i32x4.shl |
0xab |
:+1: |
i32x4.shr_s |
0xac |
:+1: |
i32x4.shr_u |
0xad |
:+1: |
i32x4.add |
0xae |
:+1: |
---- add_sat ---- |
0xaf |
-- |
---- add_sat ---- |
0xb0 |
-- |
i32x4.sub |
0xb1 |
:+1: |
---- sub_sat ---- |
0xb2 |
-- |
---- sub_sat ---- |
0xb3 |
-- |
---- dot ---- |
0xb4 |
-- |
i32x4.mul |
0xb5 |
:+1: |
i32x4.min_s |
0xb6 |
:+1: |
i32x4.min_u |
0xb7 |
:+1: |
i32x4.max_s |
0xb8 |
:+1: |
i32x4.max_u |
0xb9 |
:+1: |
---- avgr_s ---- |
0xba |
-- |
---- avgr_u ---- |
0xbb |
-- |
i64x2 Arith Op |
Opcode |
Status |
---- |
0xc0 |
-- |
i64x2.neg |
0xc1 |
:+1: |
---- |
0xc2 |
-- |
---- |
0xc3 |
-- |
---- |
0xc4 |
-- |
---- |
0xc5 |
-- |
---- |
0xc6 |
-- |
---- |
0xc7 |
-- |
---- |
0xc8 |
-- |
---- |
0xc9 |
-- |
---- |
0xca |
-- |
i64x2.shl |
0xcb |
:+1: |
i64x2.shr_s |
0xcc |
:+1: |
i64x2.shr_u |
0xcd |
:+1: |
i64x2.add |
0xce |
:+1: |
---- |
0xcf |
-- |
---- |
0xd0 |
-- |
i64x2.sub |
0xd1 |
:+1: |
---- |
0xd2 |
-- |
---- |
0xd3 |
-- |
---- |
0xd4 |
-- |
i64x2.mul |
0xd5 |
:+1: |
---- |
0xd6 |
-- |
---- |
0xd7 |
-- |
---- |
0xd8 |
-- |
---- |
0xd9 |
-- |
---- |
0xda |
-- |
---- |
0xdb |
-- |
f32x4 Op |
Opcode |
Status |
f32x4.abs |
0xe0 |
-- |
f32x4.neg |
0xe1 |
-- |
---- round ---- |
0xe2 |
-- |
f32x4.sqrt |
0xe3 |
-- |
f32x4.add |
0xe4 |
-- |
f32x4.sub |
0xe5 |
-- |
f32x4.mul |
0xe6 |
-- |
f32x4.div |
0xe7 |
-- |
f32x4.min |
0xe8 |
-- |
f32x4.max |
0xe9 |
-- |
f32x4.pmin |
0xea |
-- |
f32x4.pmax |
0xeb |
-- |
f64x2 Op |
Opcode |
Status |
f64x2.abs |
0xec |
-- |
f64x2.neg |
0xed |
-- |
---- round ---- |
0xee |
-- |
f64x2.sqrt |
0xef |
-- |
f64x2.add |
0xf0 |
-- |
f64x2.sub |
0xf1 |
-- |
f64x2.mul |
0xf2 |
-- |
f64x2.div |
0xf3 |
-- |
f64x2.min |
0xf4 |
-- |
f64x2.max |
0xf5 |
-- |
f64x2.pmin |
0xf6 |
-- |
f64x2.pmax |
0xf7 |
-- |
Conversion Op |
Opcode |
Status |
i32x4.trunc_sat_f32x4_s |
0xf8 |
-- |
i32x4.trunc_sat_f32x4_u |
0xf9 |
-- |
f32x4.convert_i32x4_s |
0xfa |
-- |
f32x4.convert_i32x4_u |
0xfb |
-- |
jlb6740 edited Issue #2272:
Status: Currently Not Valid (Initial Status WIP)
Last Update: 10/8/2020
https://gist.github.com/jlb6740/0a495404f6b3cc901e1b8e5ae8148020
Loads |
Opcode |
Status |
v128.load |
0x00 |
:+1: |
v128.load8x8_s |
0x01 |
:+1: |
v128.load8x8_u |
0x02 |
:+1: |
v128.load16x4_s |
0x03 |
:+1: |
v128.load16x4_u |
0x04 |
:+1: |
v128.load32x2_s |
0x05 |
:+1: |
v128.load32x2_u |
0x06 |
:+1: |
v128.load8_splat |
0x07 |
:+1: |
v128.load16_splat |
0x08 |
:+1: |
v128.load32_splat |
0x09 |
:+1: |
v128.load64_splat |
0x0a |
:+1: |
Basic operation |
Opcode |
Status |
v128.const |
0x0c |
:+1: |
i8x16.shuffle |
0x0d |
:+1: |
i8x16.swizzle |
0x0e |
:+1: |
Splat operation |
Opcode |
Status |
i8x16.splat |
0x0f |
:+1: |
i16x8.splat |
0x10 |
:+1: |
i32x4.splat |
0x11 |
:+1: |
i64x2.splat |
0x12 |
:+1: |
f32x4.splat |
0x13 |
:+1: |
f64x2.splat |
0x14 |
:+1: |
Lane operation |
Opcode |
Status |
i8x16.extract_lane_s |
0x15 |
:+1: |
i8x16.extract_lane_u |
0x16 |
:+1: |
i8x16.replace_lane |
0x17 |
:+1: |
i16x8.extract_lane_s |
0x18 |
:+1: |
i16x8.extract_lane_u |
0x19 |
:+1: |
i16x8.replace_lane |
0x1a |
:+1: |
i32x4.extract_lane |
0x1b |
:+1: |
i32x4.replace_lane |
0x1c |
:+1: |
i64x2.extract_lane |
0x1d |
:+1: |
i64x2.replace_lane |
0x1e |
:+1: |
f32x4.extract_lane |
0x1f |
:+1: |
f32x4.replace_lane |
0x20 |
:+1: |
f64x2.extract_lane |
0x21 |
:+1: |
f64x2.replace_lane |
0x22 |
:+1: |
Integer Cmp |
Opcode |
Status |
i8x16.eq |
0x23 |
:+1: |
i8x16.ne |
0x24 |
:+1: |
i8x16.lt_s |
0x25 |
:+1: |
i8x16.lt_u |
0x26 |
:+1: |
i8x16.gt_s |
0x27 |
:+1: |
i8x16.gt_u |
0x28 |
:+1: |
i8x16.le_s |
0x29 |
:+1: |
i8x16.le_u |
0x2a |
:+1: |
i8x16.ge_s |
0x2b |
:+1: |
i8x16.ge_u |
0x2c |
:+1: |
i16x8.eq |
0x2d |
:+1: |
i16x8.ne |
0x2e |
:+1: |
i16x8.lt_s |
0x2f |
:+1: |
i16x8.lt_u |
0x30 |
:+1: |
i16x8.gt_s |
0x31 |
:+1: |
i16x8.gt_u |
0x32 |
:+1: |
i16x8.le_s |
0x33 |
:+1: |
i16x8.le_u |
0x34 |
:+1: |
i16x8.ge_s |
0x35 |
:+1: |
i16x8.ge_u |
0x36 |
:+1: |
i32x4.eq |
0x37 |
:+1: |
i32x4.ne |
0x38 |
:+1: |
i32x4.lt_s |
0x39 |
:+1: |
i32x4.lt_u |
0x3a |
:+1: |
i32x4.gt_s |
0x3b |
:+1: |
i32x4.gt_u |
0x3c |
:+1: |
i32x4.le_s |
0x3d |
:+1: |
i32x4.le_u |
0x3e |
:+1: |
i32x4.ge_s |
0x3f |
:+1: |
i32x4.ge_u |
0x40 |
:+1: |
v128 Op |
Opcode |
Status |
v128.not |
0x4d |
:+1: |
v128.and |
0x4e |
:+1: |
v128.andnot |
0x4f |
:+1: |
v128.or |
0x50 |
:+1: |
v128.xor |
0x51 |
:+1: |
v128.bitselect |
0x52 |
:+1: |
i8x16 Arith Op |
Opcode |
-- |
i8x16.abs |
0x60 |
:+1: |
i8x16.neg |
0x61 |
:+1: |
i8x16.any_true |
0x62 |
:+1: |
i8x16.all_true |
0x63 |
:+1: |
i8x16.bitmask |
0x64 |
:question: |
i8x16.narrow_i16x8_s |
0x65 |
:+1: |
i8x16.narrow_i16x8_u |
0x66 |
:+1: |
---- widen ---- |
0x67 |
-- |
---- widen ---- |
0x68 |
-- |
---- widen ---- |
0x69 |
-- |
---- widen ---- |
0x6a |
-- |
i8x16.shl |
0x6b |
:+1: |
i8x16.shr_s |
0x6c |
:+1: |
i8x16.shr_u |
0x6d |
:+1: |
i8x16.add |
0x6e |
:+1: |
i8x16.add_sat_s |
0x6f |
:+1: |
i8x16.add_sat_u |
0x70 |
:+1: |
i8x16.sub |
0x71 |
:+1: |
i8x16.sub_sat_s |
0x72 |
:+1: |
i8x16.sub_sat_u |
0x73 |
:+1: |
---- dot ---- |
0x74 |
-- |
---- mul ---- |
0x75 |
:question: |
i8x16.min_s |
0x76 |
:+1: |
i8x16.min_u |
0x77 |
:+1: |
i8x16.max_s |
0x78 |
:+1: |
i8x16.max_u |
0x79 |
:+1: |
---- avgr_s ---- |
0x7a |
-- |
i8x16.avgr_u |
0x7b |
:+1: |
i16x8 Arith Op |
Opcode |
Status |
i16x8.abs |
0x80 |
:+1: |
i16x8.neg |
0x81 |
:+1: |
i16x8.any_true |
0x82 |
:+1: |
i16x8.all_true |
0x83 |
:+1: |
i16x8.bitmask |
0x84 |
:question: |
i16x8.narrow_i32x4_s |
0x85 |
:+1: |
i16x8.narrow_i32x4_u |
0x86 |
:+1: |
i16x8.widen_low_i8x16_s |
0x87 |
:+1: |
i16x8.widen_high_i8x16_s |
0x88 |
:+1: |
i16x8.widen_low_i8x16_u |
0x89 |
:+1: |
i16x8.widen_high_i8x16_u |
0x8a |
:+1: |
i16x8.shl |
0x8b |
:+1: |
i16x8.shr_s |
0x8c |
:+1: |
i16x8.shr_u |
0x8d |
:+1: |
i16x8.add |
0x8e |
:+1: |
i16x8.add_sat_s |
0x8f |
:+1: |
i16x8.add_sat_u |
0x90 |
:+1: |
i16x8.sub |
0x91 |
:+1: |
i16x8.sub_sat_s |
0x92 |
:+1: |
i16x8.sub_sat_u |
0x93 |
:+1: |
---- dot ---- |
0x94 |
-- |
i16x8.mul |
0x95 |
:+1: |
i16x8.min_s |
0x96 |
:+1: |
i16x8.min_u |
0x97 |
:+1: |
i16x8.max_s |
0x98 |
:+1: |
i16x8.max_u |
0x99 |
:+1: |
---- avgr_s ---- |
0x9a |
-- |
i16x8.avgr_u |
0x9b |
:+1: |
i32x4 Arith Op |
Opcode |
Status |
i32x4.abs |
0xa0 |
:+1: |
i32x4.neg |
0xa1 |
:+1: |
i32x4.any_true |
0xa2 |
:+1: |
i32x4.all_true |
0xa3 |
:+1: |
i32x4.bitmask |
0xa4 |
:question: |
---- narrow ---- |
0xa5 |
-- |
---- narrow ---- |
0xa6 |
-- |
i32x4.widen_low_i16x8_s |
0xa7 |
:+1: |
i32x4.widen_high_i16x8_s |
0xa8 |
:+1: |
i32x4.widen_low_i16x8_u |
0xa9 |
:+1: |
i32x4.widen_high_i16x8_u |
0xaa |
:+1: |
i32x4.shl |
0xab |
:+1: |
i32x4.shr_s |
0xac |
:+1: |
i32x4.shr_u |
0xad |
:+1: |
i32x4.add |
0xae |
:+1: |
---- add_sat ---- |
0xaf |
-- |
---- add_sat ---- |
0xb0 |
-- |
i32x4.sub |
0xb1 |
:+1: |
---- sub_sat ---- |
0xb2 |
-- |
---- sub_sat ---- |
0xb3 |
-- |
---- dot ---- |
0xb4 |
-- |
i32x4.mul |
0xb5 |
:+1: |
i32x4.min_s |
0xb6 |
:+1: |
i32x4.min_u |
0xb7 |
:+1: |
i32x4.max_s |
0xb8 |
:+1: |
i32x4.max_u |
0xb9 |
:+1: |
---- avgr_s ---- |
0xba |
-- |
---- avgr_u ---- |
0xbb |
-- |
i64x2 Arith Op |
Opcode |
Status |
---- |
0xc0 |
-- |
i64x2.neg |
0xc1 |
:+1: |
---- |
0xc2 |
-- |
---- |
0xc3 |
-- |
---- |
0xc4 |
-- |
---- |
0xc5 |
-- |
---- |
0xc6 |
-- |
---- |
0xc7 |
-- |
---- |
0xc8 |
-- |
---- |
0xc9 |
-- |
---- |
0xca |
-- |
i64x2.shl |
0xcb |
:+1: |
i64x2.shr_s |
0xcc |
:+1: |
i64x2.shr_u |
0xcd |
:+1: |
i64x2.add |
0xce |
:+1: |
---- |
0xcf |
-- |
---- |
0xd0 |
-- |
i64x2.sub |
0xd1 |
:+1: |
---- |
0xd2 |
-- |
---- |
0xd3 |
-- |
---- |
0xd4 |
-- |
i64x2.mul |
0xd5 |
:+1: |
---- |
0xd6 |
-- |
---- |
0xd7 |
-- |
---- |
0xd8 |
-- |
---- |
0xd9 |
-- |
---- |
0xda |
-- |
---- |
0xdb |
-- |
f32x4 Op |
Opcode |
Status |
f32x4.abs |
0xe0 |
:+1: |
f32x4.neg |
0xe1 |
:+1: |
---- round ---- |
0xe2 |
-- |
f32x4.sqrt |
0xe3 |
:+1: |
f32x4.add |
0xe4 |
:+1: |
f32x4.sub |
0xe5 |
:+1: |
f32x4.mul |
0xe6 |
:+1: |
f32x4.div |
0xe7 |
:+1: |
f32x4.min |
0xe8 |
:+1: |
f32x4.max |
0xe9 |
:+1: |
f32x4.pmin |
0xea |
:question: |
f32x4.pmax |
0xeb |
:question: |
f64x2 Op |
Opcode |
Status |
f64x2.abs |
0xec |
:+1: |
f64x2.neg |
0xed |
:+1: |
---- round ---- |
0xee |
-- |
f64x2.sqrt |
0xef |
:+1: |
f64x2.add |
0xf0 |
:+1: |
f64x2.sub |
0xf1 |
:+1: |
f64x2.mul |
0xf2 |
:+1: |
f64x2.div |
0xf3 |
:+1: |
f64x2.min |
0xf4 |
:+1: |
f64x2.max |
0xf5 |
:+1: |
f64x2.pmin |
0xf6 |
:question: |
f64x2.pmax |
0xf7 |
:question: |
Conversion Op |
Opcode |
Status |
i32x4.trunc_sat_f32x4_s |
0xf8 |
:+1: |
i32x4.trunc_sat_f32x4_u |
0xf9 |
:+1: |
f32x4.convert_i32x4_s |
0xfa |
:+1: |
f32x4.convert_i32x4_u |
0xfb |
:+1: |
jlb6740 edited Issue #2272:
Status: Currently Not Valid (Initial Status WIP)
Last Update: 10/8/2020
https://gist.github.com/jlb6740/0a495404f6b3cc901e1b8e5ae8148020
Loads |
Opcode |
Status |
v128.load |
0x00 |
:+1: |
v128.load8x8_s |
0x01 |
:+1: |
v128.load8x8_u |
0x02 |
:+1: |
v128.load16x4_s |
0x03 |
:+1: |
v128.load16x4_u |
0x04 |
:+1: |
v128.load32x2_s |
0x05 |
:+1: |
v128.load32x2_u |
0x06 |
:+1: |
v128.load8_splat |
0x07 |
:+1: |
v128.load16_splat |
0x08 |
:+1: |
v128.load32_splat |
0x09 |
:+1: |
v128.load64_splat |
0x0a |
:+1: |
Basic operation |
Opcode |
Status |
v128.const |
0x0c |
:+1: |
i8x16.shuffle |
0x0d |
:+1: |
i8x16.swizzle |
0x0e |
:+1: |
Splat operation |
Opcode |
Status |
i8x16.splat |
0x0f |
:+1: |
i16x8.splat |
0x10 |
:+1: |
i32x4.splat |
0x11 |
:+1: |
i64x2.splat |
0x12 |
:+1: |
f32x4.splat |
0x13 |
:+1: |
f64x2.splat |
0x14 |
:+1: |
Lane operation |
Opcode |
Status |
i8x16.extract_lane_s |
0x15 |
:+1: |
i8x16.extract_lane_u |
0x16 |
:+1: |
i8x16.replace_lane |
0x17 |
:+1: |
i16x8.extract_lane_s |
0x18 |
:+1: |
i16x8.extract_lane_u |
0x19 |
:+1: |
i16x8.replace_lane |
0x1a |
:+1: |
i32x4.extract_lane |
0x1b |
:+1: |
i32x4.replace_lane |
0x1c |
:+1: |
i64x2.extract_lane |
0x1d |
:+1: |
i64x2.replace_lane |
0x1e |
:+1: |
f32x4.extract_lane |
0x1f |
:+1: |
f32x4.replace_lane |
0x20 |
:+1: |
f64x2.extract_lane |
0x21 |
:+1: |
f64x2.replace_lane |
0x22 |
:+1: |
Integer Cmp |
Opcode |
Status |
i8x16.eq |
0x23 |
:+1: |
i8x16.ne |
0x24 |
:+1: |
i8x16.lt_s |
0x25 |
:+1: |
i8x16.lt_u |
0x26 |
:+1: |
i8x16.gt_s |
0x27 |
:+1: |
i8x16.gt_u |
0x28 |
:+1: |
i8x16.le_s |
0x29 |
:+1: |
i8x16.le_u |
0x2a |
:+1: |
i8x16.ge_s |
0x2b |
:+1: |
i8x16.ge_u |
0x2c |
:+1: |
i16x8.eq |
0x2d |
:+1: |
i16x8.ne |
0x2e |
:+1: |
i16x8.lt_s |
0x2f |
:+1: |
i16x8.lt_u |
0x30 |
:+1: |
i16x8.gt_s |
0x31 |
:+1: |
i16x8.gt_u |
0x32 |
:+1: |
i16x8.le_s |
0x33 |
:+1: |
i16x8.le_u |
0x34 |
:+1: |
i16x8.ge_s |
0x35 |
:+1: |
i16x8.ge_u |
0x36 |
:+1: |
i32x4.eq |
0x37 |
:+1: |
i32x4.ne |
0x38 |
:+1: |
i32x4.lt_s |
0x39 |
:+1: |
i32x4.lt_u |
0x3a |
:+1: |
i32x4.gt_s |
0x3b |
:+1: |
i32x4.gt_u |
0x3c |
:+1: |
i32x4.le_s |
0x3d |
:+1: |
i32x4.le_u |
0x3e |
:+1: |
i32x4.ge_s |
0x3f |
:+1: |
i32x4.ge_u |
0x40 |
:+1: |
v128 Op |
Opcode |
Status |
v128.not |
0x4d |
:+1: |
v128.and |
0x4e |
:+1: |
v128.andnot |
0x4f |
:+1: |
v128.or |
0x50 |
:+1: |
v128.xor |
0x51 |
:+1: |
v128.bitselect |
0x52 |
:+1: |
i8x16 Arith Op |
Opcode |
-- |
i8x16.abs |
0x60 |
:+1: |
i8x16.neg |
0x61 |
:+1: |
i8x16.any_true |
0x62 |
:+1: |
i8x16.all_true |
0x63 |
:+1: |
i8x16.bitmask |
0x64 |
:question: |
i8x16.narrow_i16x8_s |
0x65 |
:+1: |
i8x16.narrow_i16x8_u |
0x66 |
:+1: |
---- widen ---- |
0x67 |
-- |
---- widen ---- |
0x68 |
-- |
---- widen ---- |
0x69 |
-- |
---- widen ---- |
0x6a |
-- |
i8x16.shl |
0x6b |
:+1: |
i8x16.shr_s |
0x6c |
:+1: |
i8x16.shr_u |
0x6d |
:+1: |
i8x16.add |
0x6e |
:+1: |
i8x16.add_sat_s |
0x6f |
:+1: |
i8x16.add_sat_u |
0x70 |
:+1: |
i8x16.sub |
0x71 |
:+1: |
i8x16.sub_sat_s |
0x72 |
:+1: |
i8x16.sub_sat_u |
0x73 |
:+1: |
---- dot ---- |
0x74 |
-- |
---- mul ---- |
0x75 |
:question: |
i8x16.min_s |
0x76 |
:+1: |
i8x16.min_u |
0x77 |
:+1: |
i8x16.max_s |
0x78 |
:+1: |
i8x16.max_u |
0x79 |
:+1: |
---- avgr_s ---- |
0x7a |
-- |
i8x16.avgr_u |
0x7b |
:+1: |
i16x8 Arith Op |
Opcode |
Status |
i16x8.abs |
0x80 |
:+1: |
i16x8.neg |
0x81 |
:+1: |
i16x8.any_true |
0x82 |
:+1: |
i16x8.all_true |
0x83 |
:+1: |
i16x8.bitmask |
0x84 |
:question: |
i16x8.narrow_i32x4_s |
0x85 |
:+1: |
i16x8.narrow_i32x4_u |
0x86 |
:+1: |
i16x8.widen_low_i8x16_s |
0x87 |
:+1: |
i16x8.widen_high_i8x16_s |
0x88 |
:+1: |
i16x8.widen_low_i8x16_u |
0x89 |
:+1: |
i16x8.widen_high_i8x16_u |
0x8a |
:+1: |
i16x8.shl |
0x8b |
:+1: |
i16x8.shr_s |
0x8c |
:+1: |
i16x8.shr_u |
0x8d |
:+1: |
i16x8.add |
0x8e |
:+1: |
i16x8.add_sat_s |
0x8f |
:+1: |
i16x8.add_sat_u |
0x90 |
:+1: |
i16x8.sub |
0x91 |
:+1: |
i16x8.sub_sat_s |
0x92 |
:+1: |
i16x8.sub_sat_u |
0x93 |
:+1: |
---- dot ---- |
0x94 |
-- |
i16x8.mul |
0x95 |
:+1: |
i16x8.min_s |
0x96 |
:+1: |
i16x8.min_u |
0x97 |
:+1: |
i16x8.max_s |
0x98 |
:+1: |
i16x8.max_u |
0x99 |
:+1: |
---- avgr_s ---- |
0x9a |
-- |
i16x8.avgr_u |
0x9b |
:+1: |
i32x4 Arith Op |
Opcode |
Status |
i32x4.abs |
0xa0 |
:+1: |
i32x4.neg |
0xa1 |
:+1: |
i32x4.any_true |
0xa2 |
:+1: |
i32x4.all_true |
0xa3 |
:+1: |
i32x4.bitmask |
0xa4 |
:question: |
---- narrow ---- |
0xa5 |
-- |
---- narrow ---- |
0xa6 |
-- |
i32x4.widen_low_i16x8_s |
0xa7 |
:+1: |
i32x4.widen_high_i16x8_s |
0xa8 |
:+1: |
i32x4.widen_low_i16x8_u |
0xa9 |
:+1: |
i32x4.widen_high_i16x8_u |
0xaa |
:+1: |
i32x4.shl |
0xab |
:+1: |
i32x4.shr_s |
0xac |
:+1: |
i32x4.shr_u |
0xad |
:+1: |
i32x4.add |
0xae |
:+1: |
---- add_sat ---- |
0xaf |
-- |
---- add_sat ---- |
0xb0 |
-- |
i32x4.sub |
0xb1 |
:+1: |
---- sub_sat ---- |
0xb2 |
-- |
---- sub_sat ---- |
0xb3 |
-- |
---- dot ---- |
0xb4 |
-- |
i32x4.mul |
0xb5 |
:+1: |
i32x4.min_s |
0xb6 |
:+1: |
i32x4.min_u |
0xb7 |
:+1: |
i32x4.max_s |
0xb8 |
:+1: |
i32x4.max_u |
0xb9 |
:+1: |
---- avgr_s ---- |
0xba |
-- |
---- avgr_u ---- |
0xbb |
-- |
i64x2 Arith Op |
Opcode |
Status |
---- |
0xc0 |
-- |
i64x2.neg |
0xc1 |
:+1: |
---- |
0xc2 |
-- |
---- |
0xc3 |
-- |
---- |
0xc4 |
-- |
---- |
0xc5 |
-- |
---- |
0xc6 |
-- |
---- |
0xc7 |
-- |
---- |
0xc8 |
-- |
---- |
0xc9 |
-- |
---- |
0xca |
-- |
i64x2.shl |
0xcb |
:+1: |
i64x2.shr_s |
0xcc |
:+1: |
i64x2.shr_u |
0xcd |
:+1: |
i64x2.add |
0xce |
:+1: |
---- |
0xcf |
-- |
---- |
0xd0 |
-- |
i64x2.sub |
0xd1 |
:+1: |
---- |
0xd2 |
-- |
---- |
0xd3 |
-- |
---- |
0xd4 |
-- |
i64x2.mul |
0xd5 |
:+1: |
---- |
0xd6 |
-- |
---- |
0xd7 |
-- |
f32x4 Op |
Opcode |
Status |
f32x4.ceil |
0xd8 |
:question: |
f32x4.floor |
0xd9 |
:question: |
f32x4.trunc |
0xda |
:question: |
f32x4.nearest |
0xdb |
:question: |
f32x4.abs |
0xe0 |
:+1: |
f32x4.neg |
0xe1 |
:+1: |
---- round ---- |
0xe2 |
-- |
f32x4.sqrt |
0xe3 |
:+1: |
f32x4.add |
0xe4 |
:+1: |
f32x4.sub |
0xe5 |
:+1: |
f32x4.mul |
0xe6 |
:+1: |
f32x4.div |
0xe7 |
:+1: |
f32x4.min |
0xe8 |
:+1: |
f32x4.max |
0xe9 |
:+1: |
f32x4.pmin |
0xea |
:question: |
f32x4.pmax |
0xeb |
:question: |
f64x2 Op |
Opcode |
Status |
f64x2.ceil |
0xdc |
:question: |
f64x2.floor |
0xdd |
:question: |
f64x2.trunc |
0xde |
:question: |
f64x2.nearest |
0xdf |
:question: |
f64x2.abs |
0xec |
:+1: |
f64x2.neg |
0xed |
:+1: |
---- round ---- |
0xee |
-- |
f64x2.sqrt |
0xef |
:+1: |
f64x2.add |
0xf0 |
:+1: |
f64x2.sub |
0xf1 |
:+1: |
f64x2.mul |
0xf2 |
:+1: |
f64x2.div |
0xf3 |
:+1: |
f64x2.min |
0xf4 |
:+1: |
f64x2.max |
0xf5 |
:+1: |
f64x2.pmin |
0xf6 |
:question: |
f64x2.pmax |
0xf7 |
:question: |
Conversion Op |
Opcode |
Status |
i32x4.trunc_sat_f32x4_s |
0xf8 |
:+1: |
i32x4.trunc_sat_f32x4_u |
0xf9 |
:+1: |
f32x4.convert_i32x4_s |
0xfa |
:+1: |
f32x4.convert_i32x4_u |
0xfb |
:+1: |
jlb6740 edited Issue #2272:
Status: Currently Not Valid (Initial Status WIP)
Last Update: 10/8/2020
https://gist.github.com/jlb6740/0a495404f6b3cc901e1b8e5ae8148020
Loads | Opcode | Old Backend Status| VCode Status
-- | --| --
v128.load | 0x00 | :+1:
v128.load8x8_s | 0x01| :+1:
v128.load8x8_u | 0x02| :+1:
v128.load16x4_s | 0x03| :+1:
v128.load16x4_u | 0x04| :+1:
v128.load32x2_s | 0x05| :+1:
v128.load32x2_u | 0x06| :+1:
v128.load8_splat | 0x07| :+1:
v128.load16_splat | 0x08|:+1:
v128.load32_splat | 0x09| :+1:
v128.load64_splat | 0x0a| :+1:
Stores | Opcode | Old Backend Status| VCode Status
-- | --| --
v128.store | 0x0b| :+1:
Basic operation | Opcode | Old Backend Status| VCode Status
-- | -- | --
v128.const | 0x0c | :+1:
i8x16.shuffle | 0x0d | :+1:
i8x16.swizzle | 0x0e | :+1:
Splat operation | Opcode | Old Backend Status| VCode Status
-- | --| --
i8x16.splat | 0x0f| :+1:
i16x8.splat | 0x10| :+1:
i32x4.splat | 0x11| :+1:
i64x2.splat | 0x12| :+1:
f32x4.splat | 0x13| :+1:
f64x2.splat | 0x14| :+1:
Lane operation | Opcode | Old Backend Status| VCode Status
-- | --| --
i8x16.extract_lane_s | 0x15| :+1:
i8x16.extract_lane_u | 0x16| :+1:
i8x16.replace_lane | 0x17| :+1:
i16x8.extract_lane_s | 0x18| :+1:
i16x8.extract_lane_u | 0x19| :+1:
i16x8.replace_lane | 0x1a| :+1:
i32x4.extract_lane | 0x1b| :+1:
i32x4.replace_lane | 0x1c| :+1:
i64x2.extract_lane | 0x1d| :+1:
i64x2.replace_lane | 0x1e| :+1:
f32x4.extract_lane | 0x1f| :+1:
f32x4.replace_lane | 0x20| :+1:
f64x2.extract_lane | 0x21| :+1:
f64x2.replace_lane | 0x22| :+1:
Integer Cmp | Opcode | Old Backend Status| VCode Status
-- | -- | --
i8x16.eq | 0x23 | :+1:
i8x16.ne | 0x24 |:+1:
i8x16.lt_s | 0x25 | :+1:
i8x16.lt_u | 0x26 | :+1:
i8x16.gt_s | 0x27 | :+1:
i8x16.gt_u | 0x28 | :+1:
i8x16.le_s | 0x29 | :+1:
i8x16.le_u | 0x2a | :+1:
i8x16.ge_s | 0x2b | :+1:
i8x16.ge_u | 0x2c | :+1:
i16x8.eq | 0x2d | :+1:
i16x8.ne | 0x2e | :+1:
i16x8.lt_s | 0x2f | :+1:
i16x8.lt_u | 0x30 | :+1:
i16x8.gt_s | 0x31 | :+1:
i16x8.gt_u | 0x32 | :+1:
i16x8.le_s | 0x33 | :+1:
i16x8.le_u | 0x34 | :+1:
i16x8.ge_s | 0x35 | :+1:
i16x8.ge_u | 0x36 |:+1:
i32x4.eq | 0x37 | :+1:
i32x4.ne | 0x38 | :+1:
i32x4.lt_s | 0x39 | :+1:
i32x4.lt_u | 0x3a | :+1:
i32x4.gt_s | 0x3b | :+1:
i32x4.gt_u | 0x3c | :+1:
i32x4.le_s | 0x3d | :+1:
i32x4.le_u | 0x3e | :+1:
i32x4.ge_s | 0x3f | :+1:
i32x4.ge_u | 0x40 | :+1:
Float Cmp | Opcode | Old Backend Status| VCode Status
-- | -- | --
f32x4.eq | 0x41 | :+1:
f32x4.ne | 0x42 | :+1:
f32x4.lt | 0x43 | :+1:
f32x4.gt | 0x44 | :+1:
f32x4.le | 0x45 | :+1:
f32x4.ge | 0x46 | :+1:
f64x2.eq | 0x47| :+1:
f64x2.ne | 0x48| :+1:
f64x2.lt | 0x49| :+1:
f64x2.gt | 0x4a| :+1:
f64x2.le | 0x4b| :+1:
f64x2.ge | 0x4c| :+1:
v128 Op | Opcode | Old Backend Status| VCode Status
-- | --| --
v128.not | 0x4d| :+1:
v128.and | 0x4e| :+1:
v128.andnot | 0x4f| :+1:
v128.or | 0x50| :+1:
v128.xor | 0x51| :+1:
v128.bitselect | 0x52| :+1:
i8x16 Arith Op | Opcode |Old Backend Status| VCode Status
-- | -- | --
i8x16.abs | 0x60 | :+1:
i8x16.neg | 0x61 |:+1:
i8x16.any_true | 0x62 | :+1:
i8x16.all_true | 0x63 | :+1:
i8x16.bitmask | 0x64 |:question:
i8x16.narrow_i16x8_s | 0x65 |:+1:
i8x16.narrow_i16x8_u | 0x66 | :+1:
---- widen ---- | 0x67 |--
---- widen ---- | 0x68 |--
---- widen ---- | 0x69 |--
---- widen ---- | 0x6a | --
i8x16.shl | 0x6b |:+1:
i8x16.shr_s | 0x6c |:+1:
i8x16.shr_u | 0x6d | :+1:
i8x16.add | 0x6e | :+1:
i8x16.add_sat_s | 0x6f | :+1:
i8x16.add_sat_u | 0x70 |:+1:
i8x16.sub | 0x71 |:+1:
i8x16.sub_sat_s | 0x72 |:+1:
i8x16.sub_sat_u | 0x73 |:+1:
---- dot ---- | 0x74 | --
---- mul ---- | 0x75 | :question:
i8x16.min_s | 0x76 | :+1:
i8x16.min_u | 0x77 | :+1:
i8x16.max_s | 0x78 |:+1:
i8x16.max_u | 0x79 | :+1:
---- avgr_s ---- | 0x7a | --
i8x16.avgr_u | 0x7b |:+1:
i16x8 Arith Op | Opcode |Old Backend Status| VCode Status
-- | -- | --
i16x8.abs | 0x80 |:+1:
i16x8.neg | 0x81 |:+1:
i16x8.any_true | 0x82 | :+1:
i16x8.all_true | 0x83 | :+1:
i16x8.bitmask | 0x84 | :question:
i16x8.narrow_i32x4_s | 0x85 | :+1:
i16x8.narrow_i32x4_u | 0x86 | :+1:
i16x8.widen_low_i8x16_s | 0x87 | :+1:
i16x8.widen_high_i8x16_s | 0x88 |:+1:
i16x8.widen_low_i8x16_u | 0x89 |:+1:
i16x8.widen_high_i8x16_u | 0x8a | :+1:
i16x8.shl | 0x8b | :+1:
i16x8.shr_s | 0x8c | :+1:
i16x8.shr_u | 0x8d |:+1:
i16x8.add | 0x8e | :+1:
i16x8.add_sat_s | 0x8f | :+1:
i16x8.add_sat_u | 0x90 | :+1:
i16x8.sub | 0x91 | :+1:
i16x8.sub_sat_s | 0x92 | :+1:
i16x8.sub_sat_u | 0x93 | :+1:
---- dot ---- | 0x94 | --
i16x8.mul | 0x95 |:+1:
i16x8.min_s | 0x96 | :+1:
i16x8.min_u | 0x97 |:+1:
i16x8.max_s | 0x98 | :+1:
i16x8.max_u | 0x99 | :+1:
---- avgr_s ---- | 0x9a |--
i16x8.avgr_u | 0x9b | :+1:
i32x4 Arith Op | Opcode | Old Backend Status| VCode Status
-- | -- | --
i32x4.abs | 0xa0 |:+1:
i32x4.neg | 0xa1 |:+1:
i32x4.any_true | 0xa2 | :+1:
i32x4.all_true | 0xa3 | :+1:
i32x4.bitmask | 0xa4 | :question:
---- narrow ---- | 0xa5 | --
---- narrow ---- | 0xa6 |--
i32x4.widen_low_i16x8_s | 0xa7 |:+1:
i32x4.widen_high_i16x8_s | 0xa8 | :+1:
i32x4.widen_low_i16x8_u | 0xa9 | :+1:
i32x4.widen_high_i16x8_u | 0xaa | :+1:
i32x4.shl | 0xab |:+1:
i32x4.shr_s | 0xac | :+1:
i32x4.shr_u | 0xad |:+1:
i32x4.add | 0xae |:+1:
---- add_sat ---- | 0xaf | --
---- add_sat ---- | 0xb0 | --
i32x4.sub | 0xb1 | :+1:
---- sub_sat ---- | 0xb2 | --
---- sub_sat ---- | 0xb3 | --
---- dot ---- | 0xb4 | --
i32x4.mul | 0xb5 | :+1:
i32x4.min_s | 0xb6 | :+1:
i32x4.min_u | 0xb7 | :+1:
i32x4.max_s | 0xb8 | :+1:
i32x4.max_u | 0xb9 | :+1:
---- avgr_s ---- | 0xba | --
---- avgr_u ---- | 0xbb | --
i64x2 Arith Op | Opcode|Old Backend Status| VCode Status
-- | -- | --
---- | 0xc0| --
i64x2.neg | 0xc1| :+1:
---- | 0xc2| --
---- | 0xc3| --
---- | 0xc4| --
---- | 0xc5| --
---- | 0xc6| --
---- | 0xc7| --
---- | 0xc8| --
---- | 0xc9| --
---- | 0xca| --
i64x2.shl | 0xcb| :+1:
i64x2.shr_s | 0xcc | :+1:
i64x2.shr_u | 0xcd | :+1:
i64x2.add | 0xce | :+1:
---- | 0xcf | --
---- | 0xd0 | --
i64x2.sub | 0xd1 | :+1:
---- | 0xd2 | --
---- | 0xd3 | --
---- | 0xd4 | --
i64x2.mul | 0xd5 | :+1:
---- | 0xd6 | --
---- | 0xd7 | --
f32x4 Op | Opcode |Old Backend Status| VCode Status
-- | -- | --
f32x4.ceil | 0xd8 | :question:
f32x4.floor | 0xd9 |:question:
f32x4.trunc | 0xda |:question:
f32x4.nearest | 0xdb | :question:
f32x4.abs | 0xe0 |:+1:
f32x4.neg | 0xe1 | :+1:
---- round ---- | 0xe2 | --
f32x4.sqrt | 0xe3 |:+1:
f32x4.add | 0xe4 | :+1:
f32x4.sub | 0xe5 | :+1:
f32x4.mul | 0xe6 | :+1:
f32x4.div | 0xe7 |:+1:
f32x4.min | 0xe8 | :+1:
f32x4.max | 0xe9 | :+1:
f32x4.pmin | 0xea | :question:
f32x4.pmax | 0xeb | :question:
f64x2 Op | Opcode| Old Backend Status| VCode Status
-- | -- | --
f64x2.ceil | 0xdc | :question:
f64x2.floor | 0xdd |:question:
f64x2.trunc | 0xde |:question:
f64x2.nearest | 0xdf | :question:
f64x2.abs | 0xec| :+1:
f64x2.neg | 0xed| :+1:
---- round ---- | 0xee| --
f64x2.sqrt | 0xef| :+1:
f64x2.add | 0xf0| :+1:
f64x2.sub | 0xf1| :+1:
f64x2.mul | 0xf2| :+1:
f64x2.div | 0xf3| :+1:
f64x2.min | 0xf4|:+1:
f64x2.max | 0xf5| :+1:
f64x2.pmin | 0xf6| :question:
f64x2.pmax | 0xf7| :question:
Conversion Op | Opcode| Old Backend Status| VCode Status
-- | --| --
i32x4.trunc_sat_f32x4_s | 0xf8| :+1:
i32x4.trunc_sat_f32x4_u | 0xf9| :+1:
f32x4.convert_i32x4_s | 0xfa| :+1:
f32x4.convert_i32x4_u | 0xfb| :+1:
jlb6740 edited Issue #2272:
Status: Currently Not Valid (Initial Status WIP)
Last Update: 10/8/2020
https://gist.github.com/jlb6740/0a495404f6b3cc901e1b8e5ae8148020
Loads |
Opcode |
Old Backend Status |
VCode Status |
v128.load |
0x00 |
:+1: |
|
v128.load8x8_s |
0x01 |
:+1: |
|
v128.load8x8_u |
0x02 |
:+1: |
|
v128.load16x4_s |
0x03 |
:+1: |
|
v128.load16x4_u |
0x04 |
:+1: |
|
v128.load32x2_s |
0x05 |
:+1: |
|
v128.load32x2_u |
0x06 |
:+1: |
|
v128.load8_splat |
0x07 |
:+1: |
|
v128.load16_splat |
0x08 |
:+1: |
|
v128.load32_splat |
0x09 |
:+1: |
|
v128.load64_splat |
0x0a |
:+1: |
|
Stores |
Opcode |
Old Backend Status |
VCode Status |
v128.store |
0x0b |
:+1: |
|
Basic operation |
Opcode |
Old Backend Status |
VCode Status |
v128.const |
0x0c |
:+1: |
|
i8x16.shuffle |
0x0d |
:+1: |
|
i8x16.swizzle |
0x0e |
:+1: |
|
Splat operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.splat |
0x0f |
:+1:v |
|
i16x8.splat |
0x10 |
:+1: |
|
i32x4.splat |
0x11 |
:+1: |
|
i64x2.splat |
0x12 |
:+1: |
|
f32x4.splat |
0x13 |
:+1: |
|
f64x2.splat |
0x14 |
:+1: |
|
Lane operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.extract_lane_s |
0x15 |
:+1: |
|
i8x16.extract_lane_u |
0x16 |
:+1: |
|
i8x16.replace_lane |
0x17 |
:+1: |
|
i16x8.extract_lane_s |
0x18 |
:+1: |
|
i16x8.extract_lane_u |
0x19 |
:+1: |
|
i16x8.replace_lane |
0x1a |
:+1: |
|
i32x4.extract_lane |
0x1b |
:+1: |
|
i32x4.replace_lane |
0x1c |
:+1: |
|
i64x2.extract_lane |
0x1d |
:+1: |
|
i64x2.replace_lane |
0x1e |
:+1: |
|
f32x4.extract_lane |
0x1f |
:+1: |
|
f32x4.replace_lane |
0x20 |
:+1: |
|
f64x2.extract_lane |
0x21 |
:+1: |
|
f64x2.replace_lane |
0x22 |
:+1: |
|
Integer Cmp |
Opcode |
Old Backend Status |
VCode Status |
i8x16.eq |
0x23 |
:+1: |
|
i8x16.ne |
0x24 |
:+1: |
|
i8x16.lt_s |
0x25 |
:+1: |
|
i8x16.lt_u |
0x26 |
:+1: |
|
i8x16.gt_s |
0x27 |
:+1: |
|
i8x16.gt_u |
0x28 |
:+1: |
|
i8x16.le_s |
0x29 |
:+1: |
|
i8x16.le_u |
0x2a |
:+1: |
|
i8x16.ge_s |
0x2b |
:+1: |
|
i8x16.ge_u |
0x2c |
:+1: |
|
i16x8.eq |
0x2d |
:+1: |
|
i16x8.ne |
0x2e |
:+1: |
|
i16x8.lt_s |
0x2f |
:+1: |
|
i16x8.lt_u |
0x30 |
:+1: |
|
i16x8.gt_s |
0x31 |
:+1: |
|
i16x8.gt_u |
0x32 |
:+1: |
|
i16x8.le_s |
0x33 |
:+1: |
|
i16x8.le_u |
0x34 |
:+1: |
|
i16x8.ge_s |
0x35 |
:+1: |
|
i16x8.ge_u |
0x36 |
:+1: |
|
i32x4.eq |
0x37 |
:+1: |
|
i32x4.ne |
0x38 |
:+1: |
|
i32x4.lt_s |
0x39 |
:+1: |
|
i32x4.lt_u |
0x3a |
:+1: |
|
i32x4.gt_s |
0x3b |
:+1: |
|
i32x4.gt_u |
0x3c |
:+1: |
|
i32x4.le_s |
0x3d |
:+1: |
|
i32x4.le_u |
0x3e |
:+1: |
|
i32x4.ge_s |
0x3f |
:+1: |
|
i32x4.ge_u |
0x40 |
:+1: |
|
v128 Op |
Opcode |
Old Backend Status |
VCode Status |
v128.not |
0x4d |
:+1: |
|
v128.and |
0x4e |
:+1: |
|
v128.andnot |
0x4f |
:+1: |
|
v128.or |
0x50 |
:+1: |
|
v128.xor |
0x51 |
:+1: |
|
v128.bitselect |
0x52 |
:+1: |
|
i8x16 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i8x16.abs |
0x60 |
:+1: |
|
i8x16.neg |
0x61 |
:+1: |
|
i8x16.any_true |
0x62 |
:+1: |
|
i8x16.all_true |
0x63 |
:+1: |
|
i8x16.bitmask |
0x64 |
:question: |
|
i8x16.narrow_i16x8_s |
0x65 |
:+1: |
|
i8x16.narrow_i16x8_u |
0x66 |
:+1: |
|
---- widen ---- |
0x67 |
-- |
|
---- widen ---- |
0x68 |
-- |
|
---- widen ---- |
0x69 |
-- |
|
---- widen ---- |
0x6a |
-- |
|
i8x16.shl |
0x6b |
:+1: |
|
i8x16.shr_s |
0x6c |
:+1: |
|
i8x16.shr_u |
0x6d |
:+1: |
|
i8x16.add |
0x6e |
:+1: |
|
i8x16.add_sat_s |
0x6f |
:+1: |
|
i8x16.add_sat_u |
0x70 |
:+1: |
|
i8x16.sub |
0x71 |
:+1: |
|
i8x16.sub_sat_s |
0x72 |
:+1: |
|
i8x16.sub_sat_u |
0x73 |
:+1: |
|
---- dot ---- |
0x74 |
-- |
|
---- mul ---- |
0x75 |
:question: |
|
i8x16.min_s |
0x76 |
:+1: |
|
i8x16.min_u |
0x77 |
:+1: |
|
i8x16.max_s |
0x78 |
:+1: |
|
i8x16.max_u |
0x79 |
:+1: |
|
---- avgr_s ---- |
0x7a |
-- |
|
i8x16.avgr_u |
0x7b |
:+1: |
|
i16x8 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i16x8.abs |
0x80 |
:+1: |
|
i16x8.neg |
0x81 |
:+1: |
|
i16x8.any_true |
0x82 |
:+1: |
|
i16x8.all_true |
0x83 |
:+1: |
|
i16x8.bitmask |
0x84 |
:question: |
|
i16x8.narrow_i32x4_s |
0x85 |
:+1: |
|
i16x8.narrow_i32x4_u |
0x86 |
:+1: |
|
i16x8.widen_low_i8x16_s |
0x87 |
:+1: |
|
i16x8.widen_high_i8x16_s |
0x88 |
:+1: |
|
i16x8.widen_low_i8x16_u |
0x89 |
:+1: |
|
i16x8.widen_high_i8x16_u |
0x8a |
:+1: |
|
i16x8.shl |
0x8b |
:+1: |
|
i16x8.shr_s |
0x8c |
:+1: |
|
i16x8.shr_u |
0x8d |
:+1: |
|
i16x8.add |
0x8e |
:+1: |
|
i16x8.add_sat_s |
0x8f |
:+1: |
|
i16x8.add_sat_u |
0x90 |
:+1: |
|
i16x8.sub |
0x91 |
:+1: |
|
i16x8.sub_sat_s |
0x92 |
:+1: |
|
i16x8.sub_sat_u |
0x93 |
:+1: |
|
---- dot ---- |
0x94 |
-- |
|
i16x8.mul |
0x95 |
:+1: |
|
i16x8.min_s |
0x96 |
:+1: |
|
i16x8.min_u |
0x97 |
:+1: |
|
i16x8.max_s |
0x98 |
:+1: |
|
i16x8.max_u |
0x99 |
:+1: |
|
---- avgr_s ---- |
0x9a |
-- |
|
i16x8.avgr_u |
0x9b |
:+1: |
|
i32x4 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
-- |
-- |
-- |
|
i32x4.abs |
0xa0 |
:+1: |
|
i32x4.neg |
0xa1 |
:+1: |
|
i32x4.any_true |
0xa2 |
:+1: |
|
i32x4.all_true |
0xa3 |
:+1: |
|
i32x4.bitmask |
0xa4 |
:question: |
|
---- narrow ---- |
0xa5 |
-- |
|
---- narrow ---- |
0xa6 |
-- |
|
i32x4.widen_low_i16x8_s |
0xa7 |
:+1: |
|
i32x4.widen_high_i16x8_s |
0xa8 |
:+1: |
|
i32x4.widen_low_i16x8_u |
0xa9 |
:+1: |
|
i32x4.widen_high_i16x8_u |
0xaa |
:+1: |
|
i32x4.shl |
0xab |
:+1: |
|
i32x4.shr_s |
0xac |
:+1: |
|
i32x4.shr_u |
0xad |
:+1: |
|
i32x4.add |
0xae |
:+1: |
|
---- add_sat ---- |
0xaf |
-- |
|
---- add_sat ---- |
0xb0 |
-- |
|
i32x4.sub |
0xb1 |
:+1: |
|
---- sub_sat ---- |
0xb2 |
-- |
|
---- sub_sat ---- |
0xb3 |
-- |
|
---- dot ---- |
0xb4 |
-- |
|
i32x4.mul |
0xb5 |
:+1: |
|
i32x4.min_s |
0xb6 |
:+1: |
|
i32x4.min_u |
0xb7 |
:+1: |
|
i32x4.max_s |
0xb8 |
:+1: |
|
i32x4.max_u |
0xb9 |
:+1: |
|
---- avgr_s ---- |
0xba |
-- |
|
---- avgr_u ---- |
0xbb |
-- |
|
i64x2 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
---- |
0xc0 |
-- |
|
i64x2.neg |
0xc1 |
:+1: |
|
---- |
0xc2 |
-- |
|
---- |
0xc3 |
-- |
|
---- |
0xc4 |
-- |
|
---- |
0xc5 |
-- |
|
---- |
0xc6 |
-- |
|
---- |
0xc7 |
-- |
|
---- |
0xc8 |
-- |
|
---- |
0xc9 |
-- |
|
---- |
0xca |
-- |
|
i64x2.shl |
0xcb |
:+1: |
|
i64x2.shr_s |
0xcc |
:+1: |
|
i64x2.shr_u |
0xcd |
:+1: |
|
i64x2.add |
0xce |
:+1: |
|
---- |
0xcf |
-- |
|
---- |
0xd0 |
-- |
|
i64x2.sub |
0xd1 |
:+1: |
|
---- |
0xd2 |
-- |
|
---- |
0xd3 |
-- |
|
---- |
0xd4 |
-- |
|
i64x2.mul |
0xd5 |
:+1: |
|
---- |
0xd6 |
-- |
|
---- |
0xd7 |
-- |
|
f32x4 Op |
Opcode |
Old Backend Status |
VCode Status |
f32x4.ceil |
0xd8 |
:question: |
|
f32x4.floor |
0xd9 |
:question: |
|
f32x4.trunc |
0xda |
:question: |
|
f32x4.nearest |
0xdb |
:question: |
|
f32x4.abs |
0xe0 |
:+1: |
|
f32x4.neg |
0xe1 |
:+1: |
|
---- round ---- |
0xe2 |
-- |
|
f32x4.sqrt |
0xe3 |
:+1: |
|
f32x4.add |
0xe4 |
:+1: |
|
f32x4.sub |
0xe5 |
:+1: |
|
f32x4.mul |
0xe6 |
:+1: |
|
f32x4.div |
0xe7 |
:+1: |
|
f32x4.min |
0xe8 |
:+1: |
|
f32x4.max |
0xe9 |
:+1: |
|
f32x4.pmin |
0xea |
:question: |
|
f32x4.pmax |
0xeb |
:question: |
|
f64x2 Op |
Opcode |
Old Backend Status |
VCode Status |
f64x2.ceil |
0xdc |
:question: |
|
f64x2.floor |
0xdd |
:question: |
|
f64x2.trunc |
0xde |
:question: |
|
f64x2.nearest |
0xdf |
:question: |
|
f64x2.abs |
0xec |
:+1: |
|
f64x2.neg |
0xed |
:+1: |
|
---- round ---- |
0xee |
-- |
|
f64x2.sqrt |
0xef |
:+1: |
|
f64x2.add |
0xf0 |
:+1: |
|
f64x2.sub |
0xf1 |
:+1: |
|
f64x2.mul |
0xf2 |
:+1: |
|
f64x2.div |
0xf3 |
:+1: |
|
f64x2.min |
0xf4 |
:+1: |
|
f64x2.max |
0xf5 |
:+1: |
|
f64x2.pmin |
0xf6 |
:question: |
|
f64x2.pmax |
0xf7 |
:question: |
|
Conversion Op |
Opcode |
Old Backend Status |
VCode Status |
i32x4.trunc_sat_f32x4_s |
0xf8 |
:+1: |
|
i32x4.trunc_sat_f32x4_u |
0xf9 |
:+1: |
|
f32x4.convert_i32x4_s |
0xfa |
:+1: |
|
f32x4.convert_i32x4_u |
0xfb |
:+1: |
|
jlb6740 edited Issue #2272:
Status: Currently Not Valid (Initial Status WIP)
Last Update: 10/8/2020
https://gist.github.com/jlb6740/0a495404f6b3cc901e1b8e5ae8148020
Loads |
Opcode |
Old Backend Status |
VCode Status |
v128.load |
0x00 |
:+1: |
|
v128.load8x8_s |
0x01 |
:+1: |
|
v128.load8x8_u |
0x02 |
:+1: |
|
v128.load16x4_s |
0x03 |
:+1: |
|
v128.load16x4_u |
0x04 |
:+1: |
|
v128.load32x2_s |
0x05 |
:+1: |
|
v128.load32x2_u |
0x06 |
:+1: |
|
v128.load8_splat |
0x07 |
:+1: |
|
v128.load16_splat |
0x08 |
:+1: |
|
v128.load32_splat |
0x09 |
:+1: |
|
v128.load64_splat |
0x0a |
:+1: |
|
Stores |
Opcode |
Old Backend Status |
VCode Status |
v128.store |
0x0b |
:+1: |
|
Basic operation |
Opcode |
Old Backend Status |
VCode Status |
v128.const |
0x0c |
:+1: |
|
i8x16.shuffle |
0x0d |
:+1: |
|
i8x16.swizzle |
0x0e |
:+1: |
|
Splat operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.splat |
0x0f |
:+1:v |
|
i16x8.splat |
0x10 |
:+1: |
|
i32x4.splat |
0x11 |
:+1: |
|
i64x2.splat |
0x12 |
:+1: |
|
f32x4.splat |
0x13 |
:+1: |
|
f64x2.splat |
0x14 |
:+1: |
|
Lane operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.extract_lane_s |
0x15 |
:+1: |
|
i8x16.extract_lane_u |
0x16 |
:+1: |
|
i8x16.replace_lane |
0x17 |
:+1: |
|
i16x8.extract_lane_s |
0x18 |
:+1: |
|
i16x8.extract_lane_u |
0x19 |
:+1: |
|
i16x8.replace_lane |
0x1a |
:+1: |
|
i32x4.extract_lane |
0x1b |
:+1: |
|
i32x4.replace_lane |
0x1c |
:+1: |
|
i64x2.extract_lane |
0x1d |
:+1: |
|
i64x2.replace_lane |
0x1e |
:+1: |
|
f32x4.extract_lane |
0x1f |
:+1: |
|
f32x4.replace_lane |
0x20 |
:+1: |
|
f64x2.extract_lane |
0x21 |
:+1: |
|
f64x2.replace_lane |
0x22 |
:+1: |
|
Integer Cmp |
Opcode |
Old Backend Status |
VCode Status |
i8x16.eq |
0x23 |
:+1: |
|
i8x16.ne |
0x24 |
:+1: |
|
i8x16.lt_s |
0x25 |
:+1: |
|
i8x16.lt_u |
0x26 |
:+1: |
|
i8x16.gt_s |
0x27 |
:+1: |
|
i8x16.gt_u |
0x28 |
:+1: |
|
i8x16.le_s |
0x29 |
:+1: |
|
i8x16.le_u |
0x2a |
:+1: |
|
i8x16.ge_s |
0x2b |
:+1: |
|
i8x16.ge_u |
0x2c |
:+1: |
|
i16x8.eq |
0x2d |
:+1: |
|
i16x8.ne |
0x2e |
:+1: |
|
i16x8.lt_s |
0x2f |
:+1: |
|
i16x8.lt_u |
0x30 |
:+1: |
|
i16x8.gt_s |
0x31 |
:+1: |
|
i16x8.gt_u |
0x32 |
:+1: |
|
i16x8.le_s |
0x33 |
:+1: |
|
i16x8.le_u |
0x34 |
:+1: |
|
i16x8.ge_s |
0x35 |
:+1: |
|
i16x8.ge_u |
0x36 |
:+1: |
|
i32x4.eq |
0x37 |
:+1: |
|
i32x4.ne |
0x38 |
:+1: |
|
i32x4.lt_s |
0x39 |
:+1: |
|
i32x4.lt_u |
0x3a |
:+1: |
|
i32x4.gt_s |
0x3b |
:+1: |
|
i32x4.gt_u |
0x3c |
:+1: |
|
i32x4.le_s |
0x3d |
:+1: |
|
i32x4.le_u |
0x3e |
:+1: |
|
i32x4.ge_s |
0x3f |
:+1: |
|
i32x4.ge_u |
0x40 |
:+1: |
|
v128 Op |
Opcode |
Old Backend Status |
VCode Status |
v128.not |
0x4d |
:+1: |
|
v128.and |
0x4e |
:+1: |
|
v128.andnot |
0x4f |
:+1: |
|
v128.or |
0x50 |
:+1: |
|
v128.xor |
0x51 |
:+1: |
|
v128.bitselect |
0x52 |
:+1: |
|
i8x16 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i8x16.abs |
0x60 |
:+1: |
|
i8x16.neg |
0x61 |
:+1: |
|
i8x16.any_true |
0x62 |
:+1: |
|
i8x16.all_true |
0x63 |
:+1: |
|
i8x16.bitmask |
0x64 |
:question: |
|
i8x16.narrow_i16x8_s |
0x65 |
:+1: |
|
i8x16.narrow_i16x8_u |
0x66 |
:+1: |
|
---- widen ---- |
0x67 |
-- |
|
---- widen ---- |
0x68 |
-- |
|
---- widen ---- |
0x69 |
-- |
|
---- widen ---- |
0x6a |
-- |
|
i8x16.shl |
0x6b |
:+1: |
|
i8x16.shr_s |
0x6c |
:+1: |
|
i8x16.shr_u |
0x6d |
:+1: |
|
i8x16.add |
0x6e |
:+1: |
|
i8x16.add_sat_s |
0x6f |
:+1: |
|
i8x16.add_sat_u |
0x70 |
:+1: |
|
i8x16.sub |
0x71 |
:+1: |
|
i8x16.sub_sat_s |
0x72 |
:+1: |
|
i8x16.sub_sat_u |
0x73 |
:+1: |
|
---- dot ---- |
0x74 |
-- |
|
---- mul ---- |
0x75 |
:question: |
|
i8x16.min_s |
0x76 |
:+1: |
|
i8x16.min_u |
0x77 |
:+1: |
|
i8x16.max_s |
0x78 |
:+1: |
|
i8x16.max_u |
0x79 |
:+1: |
|
---- avgr_s ---- |
0x7a |
-- |
|
i8x16.avgr_u |
0x7b |
:+1: |
|
i16x8 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i16x8.abs |
0x80 |
:+1: |
|
i16x8.neg |
0x81 |
:+1: |
|
i16x8.any_true |
0x82 |
:+1: |
|
i16x8.all_true |
0x83 |
:+1: |
|
i16x8.bitmask |
0x84 |
:question: |
|
i16x8.narrow_i32x4_s |
0x85 |
:+1: |
|
i16x8.narrow_i32x4_u |
0x86 |
:+1: |
|
i16x8.widen_low_i8x16_s |
0x87 |
:+1: |
|
i16x8.widen_high_i8x16_s |
0x88 |
:+1: |
|
i16x8.widen_low_i8x16_u |
0x89 |
:+1: |
|
i16x8.widen_high_i8x16_u |
0x8a |
:+1: |
|
i16x8.shl |
0x8b |
:+1: |
|
i16x8.shr_s |
0x8c |
:+1: |
|
i16x8.shr_u |
0x8d |
:+1: |
|
i16x8.add |
0x8e |
:+1: |
|
i16x8.add_sat_s |
0x8f |
:+1: |
|
i16x8.add_sat_u |
0x90 |
:+1: |
|
i16x8.sub |
0x91 |
:+1: |
|
i16x8.sub_sat_s |
0x92 |
:+1: |
|
i16x8.sub_sat_u |
0x93 |
:+1: |
|
---- dot ---- |
0x94 |
-- |
|
i16x8.mul |
0x95 |
:+1: |
|
i16x8.min_s |
0x96 |
:+1: |
|
i16x8.min_u |
0x97 |
:+1: |
|
i16x8.max_s |
0x98 |
:+1: |
|
i16x8.max_u |
0x99 |
:+1: |
|
---- avgr_s ---- |
0x9a |
-- |
|
i16x8.avgr_u |
0x9b |
:+1: |
|
i32x4 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
-- |
-- |
-- |
|
i32x4.abs |
0xa0 |
:+1: |
|
i32x4.neg |
0xa1 |
:+1: |
|
i32x4.any_true |
0xa2 |
:+1: |
|
i32x4.all_true |
0xa3 |
:+1: |
|
i32x4.bitmask |
0xa4 |
:question: |
|
---- narrow ---- |
0xa5 |
-- |
|
---- narrow ---- |
0xa6 |
-- |
|
i32x4.widen_low_i16x8_s |
0xa7 |
:+1: |
|
i32x4.widen_high_i16x8_s |
0xa8 |
:+1: |
|
i32x4.widen_low_i16x8_u |
0xa9 |
:+1: |
|
i32x4.widen_high_i16x8_u |
0xaa |
:+1: |
|
i32x4.shl |
0xab |
:+1: |
|
i32x4.shr_s |
0xac |
:+1: |
|
i32x4.shr_u |
0xad |
:+1: |
|
i32x4.add |
0xae |
:+1: |
|
---- add_sat ---- |
0xaf |
-- |
|
---- add_sat ---- |
0xb0 |
-- |
|
i32x4.sub |
0xb1 |
:+1: |
|
---- sub_sat ---- |
0xb2 |
-- |
|
---- sub_sat ---- |
0xb3 |
-- |
|
---- dot ---- |
0xb4 |
-- |
|
i32x4.mul |
0xb5 |
:+1: |
|
i32x4.min_s |
0xb6 |
:+1: |
|
i32x4.min_u |
0xb7 |
:+1: |
|
i32x4.max_s |
0xb8 |
:+1: |
|
i32x4.max_u |
0xb9 |
:+1: |
|
---- avgr_s ---- |
0xba |
-- |
|
---- avgr_u ---- |
0xbb |
-- |
|
i64x2 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
---- |
0xc0 |
-- |
|
i64x2.neg |
0xc1 |
:+1: |
|
---- |
0xc2 |
-- |
|
---- |
0xc3 |
-- |
|
---- |
0xc4 |
-- |
|
---- |
0xc5 |
-- |
|
---- |
0xc6 |
-- |
|
---- |
0xc7 |
-- |
|
---- |
0xc8 |
-- |
|
---- |
0xc9 |
-- |
|
---- |
0xca |
-- |
|
i64x2.shl |
0xcb |
:+1: |
|
i64x2.shr_s |
0xcc |
:+1: |
|
i64x2.shr_u |
0xcd |
:+1: |
|
i64x2.add |
0xce |
:+1: |
|
---- |
0xcf |
-- |
|
---- |
0xd0 |
-- |
|
i64x2.sub |
0xd1 |
:+1: |
|
---- |
0xd2 |
-- |
|
---- |
0xd3 |
-- |
|
---- |
0xd4 |
-- |
|
i64x2.mul |
0xd5 |
:+1: |
|
---- |
0xd6 |
-- |
|
---- |
0xd7 |
-- |
|
f32x4 Op |
Opcode |
Old Backend Status |
VCode Status |
f32x4.ceil |
0xd8 |
:question: |
|
f32x4.floor |
0xd9 |
:question: |
|
f32x4.trunc |
0xda |
:question: |
|
f32x4.nearest |
0xdb |
:question: |
|
f32x4.abs |
0xe0 |
:+1: |
|
f32x4.neg |
0xe1 |
:+1: |
|
---- round ---- |
0xe2 |
-- |
|
f32x4.sqrt |
0xe3 |
:+1: |
|
f32x4.add |
0xe4 |
:+1: |
|
f32x4.sub |
0xe5 |
:+1: |
|
f32x4.mul |
0xe6 |
:+1: |
|
f32x4.div |
0xe7 |
:+1: |
|
f32x4.min |
0xe8 |
:+1: |
|
f32x4.max |
0xe9 |
:+1: |
|
f32x4.pmin |
0xea |
:question: |
|
f32x4.pmax |
0xeb |
:question: |
|
f64x2 Op |
Opcode |
Old Backend Status |
VCode Status |
f64x2.ceil |
0xdc |
:question: |
|
f64x2.floor |
0xdd |
:question: |
|
f64x2.trunc |
0xde |
:question: |
|
f64x2.nearest |
0xdf |
:question: |
|
f64x2.abs |
0xec |
:+1: |
|
f64x2.neg |
0xed |
:+1: |
|
---- round ---- |
0xee |
-- |
|
f64x2.sqrt |
0xef |
:+1: |
|
f64x2.add |
0xf0 |
:+1: |
|
f64x2.sub |
0xf1 |
:+1: |
|
f64x2.mul |
0xf2 |
:+1: |
|
f64x2.div |
0xf3 |
:+1: |
|
f64x2.min |
0xf4 |
:+1: |
|
f64x2.max |
0xf5 |
:+1: |
|
f64x2.pmin |
0xf6 |
:question: |
|
f64x2.pmax |
0xf7 |
:question: |
|
Conversion Op |
Opcode |
Old Backend Status |
VCode Status |
i32x4.trunc_sat_f32x4_s |
0xf8 |
:+1: |
-- |
i32x4.trunc_sat_f32x4_u |
0xf9 |
:+1: |
-- |
f32x4.convert_i32x4_s |
0xfa |
:+1: |
-- |
f32x4.convert_i32x4_u |
0xfb |
:+1: |
-- |
jlb6740 edited Issue #2272:
Status: Currently Not Valid (Initial Status WIP)
Last Update: 10/8/2020
https://gist.github.com/jlb6740/0a495404f6b3cc901e1b8e5ae8148020
Loads |
Opcode |
Old Backend Status |
VCode Status |
v128.load |
0x00 |
:+1: |
|
v128.load8x8_s |
0x01 |
:+1: |
|
v128.load8x8_u |
0x02 |
:+1: |
|
v128.load16x4_s |
0x03 |
:+1: |
|
v128.load16x4_u |
0x04 |
:+1: |
|
v128.load32x2_s |
0x05 |
:+1: |
|
v128.load32x2_u |
0x06 |
:+1: |
|
v128.load8_splat |
0x07 |
:+1: |
|
v128.load16_splat |
0x08 |
:+1: |
|
v128.load32_splat |
0x09 |
:+1: |
|
v128.load64_splat |
0x0a |
:+1: |
|
Stores |
Opcode |
Old Backend Status |
VCode Status |
v128.store |
0x0b |
:+1: |
|
Basic operation |
Opcode |
Old Backend Status |
VCode Status |
v128.const |
0x0c |
:+1: |
|
i8x16.shuffle |
0x0d |
:+1: |
|
i8x16.swizzle |
0x0e |
:+1: |
|
Splat operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.splat |
0x0f |
:+1:v |
|
i16x8.splat |
0x10 |
:+1: |
|
i32x4.splat |
0x11 |
:+1: |
|
i64x2.splat |
0x12 |
:+1: |
|
f32x4.splat |
0x13 |
:+1: |
|
f64x2.splat |
0x14 |
:+1: |
|
Lane operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.extract_lane_s |
0x15 |
:+1: |
|
i8x16.extract_lane_u |
0x16 |
:+1: |
|
i8x16.replace_lane |
0x17 |
:+1: |
|
i16x8.extract_lane_s |
0x18 |
:+1: |
|
i16x8.extract_lane_u |
0x19 |
:+1: |
|
i16x8.replace_lane |
0x1a |
:+1: |
|
i32x4.extract_lane |
0x1b |
:+1: |
|
i32x4.replace_lane |
0x1c |
:+1: |
|
i64x2.extract_lane |
0x1d |
:+1: |
|
i64x2.replace_lane |
0x1e |
:+1: |
|
f32x4.extract_lane |
0x1f |
:+1: |
|
f32x4.replace_lane |
0x20 |
:+1: |
|
f64x2.extract_lane |
0x21 |
:+1: |
|
f64x2.replace_lane |
0x22 |
:+1: |
|
Integer Cmp |
Opcode |
Old Backend Status |
VCode Status |
i8x16.eq |
0x23 |
:+1: |
|
i8x16.ne |
0x24 |
:+1: |
|
i8x16.lt_s |
0x25 |
:+1: |
|
i8x16.lt_u |
0x26 |
:+1: |
|
i8x16.gt_s |
0x27 |
:+1: |
|
i8x16.gt_u |
0x28 |
:+1: |
|
i8x16.le_s |
0x29 |
:+1: |
|
i8x16.le_u |
0x2a |
:+1: |
|
i8x16.ge_s |
0x2b |
:+1: |
|
i8x16.ge_u |
0x2c |
:+1: |
|
i16x8.eq |
0x2d |
:+1: |
|
i16x8.ne |
0x2e |
:+1: |
|
i16x8.lt_s |
0x2f |
:+1: |
|
i16x8.lt_u |
0x30 |
:+1: |
|
i16x8.gt_s |
0x31 |
:+1: |
|
i16x8.gt_u |
0x32 |
:+1: |
|
i16x8.le_s |
0x33 |
:+1: |
|
i16x8.le_u |
0x34 |
:+1: |
|
i16x8.ge_s |
0x35 |
:+1: |
|
i16x8.ge_u |
0x36 |
:+1: |
|
i32x4.eq |
0x37 |
:+1: |
|
i32x4.ne |
0x38 |
:+1: |
|
i32x4.lt_s |
0x39 |
:+1: |
|
i32x4.lt_u |
0x3a |
:+1: |
|
i32x4.gt_s |
0x3b |
:+1: |
|
i32x4.gt_u |
0x3c |
:+1: |
|
i32x4.le_s |
0x3d |
:+1: |
|
i32x4.le_u |
0x3e |
:+1: |
|
i32x4.ge_s |
0x3f |
:+1: |
|
i32x4.ge_u |
0x40 |
:+1: |
|
v128 Op |
Opcode |
Old Backend Status |
VCode Status |
v128.not |
0x4d |
:+1: |
|
v128.and |
0x4e |
:+1: |
|
v128.andnot |
0x4f |
:+1: |
|
v128.or |
0x50 |
:+1: |
|
v128.xor |
0x51 |
:+1: |
|
v128.bitselect |
0x52 |
:+1: |
|
i8x16 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i8x16.abs |
0x60 |
:+1: |
|
i8x16.neg |
0x61 |
:+1: |
|
i8x16.any_true |
0x62 |
:+1: |
|
i8x16.all_true |
0x63 |
:+1: |
|
i8x16.bitmask |
0x64 |
:question: |
|
i8x16.narrow_i16x8_s |
0x65 |
:+1: |
|
i8x16.narrow_i16x8_u |
0x66 |
:+1: |
|
---- widen ---- |
0x67 |
-- |
|
---- widen ---- |
0x68 |
-- |
|
---- widen ---- |
0x69 |
-- |
|
---- widen ---- |
0x6a |
-- |
|
i8x16.shl |
0x6b |
:+1: |
|
i8x16.shr_s |
0x6c |
:+1: |
|
i8x16.shr_u |
0x6d |
:+1: |
|
i8x16.add |
0x6e |
:+1: |
|
i8x16.add_sat_s |
0x6f |
:+1: |
|
i8x16.add_sat_u |
0x70 |
:+1: |
|
i8x16.sub |
0x71 |
:+1: |
|
i8x16.sub_sat_s |
0x72 |
:+1: |
|
i8x16.sub_sat_u |
0x73 |
:+1: |
|
---- dot ---- |
0x74 |
-- |
|
---- mul ---- |
0x75 |
:question: |
|
i8x16.min_s |
0x76 |
:+1: |
|
i8x16.min_u |
0x77 |
:+1: |
|
i8x16.max_s |
0x78 |
:+1: |
|
i8x16.max_u |
0x79 |
:+1: |
|
---- avgr_s ---- |
0x7a |
-- |
|
i8x16.avgr_u |
0x7b |
:+1: |
|
i16x8 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i16x8.abs |
0x80 |
:+1: |
|
i16x8.neg |
0x81 |
:+1: |
|
i16x8.any_true |
0x82 |
:+1: |
|
i16x8.all_true |
0x83 |
:+1: |
|
i16x8.bitmask |
0x84 |
:question: |
|
i16x8.narrow_i32x4_s |
0x85 |
:+1: |
|
i16x8.narrow_i32x4_u |
0x86 |
:+1: |
|
i16x8.widen_low_i8x16_s |
0x87 |
:+1: |
|
i16x8.widen_high_i8x16_s |
0x88 |
:+1: |
|
i16x8.widen_low_i8x16_u |
0x89 |
:+1: |
|
i16x8.widen_high_i8x16_u |
0x8a |
:+1: |
|
i16x8.shl |
0x8b |
:+1: |
|
i16x8.shr_s |
0x8c |
:+1: |
|
i16x8.shr_u |
0x8d |
:+1: |
|
i16x8.add |
0x8e |
:+1: |
|
i16x8.add_sat_s |
0x8f |
:+1: |
|
i16x8.add_sat_u |
0x90 |
:+1: |
|
i16x8.sub |
0x91 |
:+1: |
|
i16x8.sub_sat_s |
0x92 |
:+1: |
|
i16x8.sub_sat_u |
0x93 |
:+1: |
|
---- dot ---- |
0x94 |
-- |
|
i16x8.mul |
0x95 |
:+1: |
|
i16x8.min_s |
0x96 |
:+1: |
|
i16x8.min_u |
0x97 |
:+1: |
|
i16x8.max_s |
0x98 |
:+1: |
|
i16x8.max_u |
0x99 |
:+1: |
|
---- avgr_s ---- |
0x9a |
-- |
|
i16x8.avgr_u |
0x9b |
:+1: |
|
i32x4 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
-- |
-- |
-- |
|
i32x4.abs |
0xa0 |
:+1: |
|
i32x4.neg |
0xa1 |
:+1: |
|
i32x4.any_true |
0xa2 |
:+1: |
|
i32x4.all_true |
0xa3 |
:+1: |
|
i32x4.bitmask |
0xa4 |
:question: |
|
---- narrow ---- |
0xa5 |
-- |
|
---- narrow ---- |
0xa6 |
-- |
|
i32x4.widen_low_i16x8_s |
0xa7 |
:+1: |
|
i32x4.widen_high_i16x8_s |
0xa8 |
:+1: |
|
i32x4.widen_low_i16x8_u |
0xa9 |
:+1: |
|
i32x4.widen_high_i16x8_u |
0xaa |
:+1: |
|
i32x4.shl |
0xab |
:+1: |
|
i32x4.shr_s |
0xac |
:+1: |
|
i32x4.shr_u |
0xad |
:+1: |
|
i32x4.add |
0xae |
:+1: |
|
---- add_sat ---- |
0xaf |
-- |
|
---- add_sat ---- |
0xb0 |
-- |
|
i32x4.sub |
0xb1 |
:+1: |
|
---- sub_sat ---- |
0xb2 |
-- |
|
---- sub_sat ---- |
0xb3 |
-- |
|
---- dot ---- |
0xb4 |
-- |
|
i32x4.mul |
0xb5 |
:+1: |
|
i32x4.min_s |
0xb6 |
:+1: |
|
i32x4.min_u |
0xb7 |
:+1: |
|
i32x4.max_s |
0xb8 |
:+1: |
|
i32x4.max_u |
0xb9 |
:+1: |
|
---- avgr_s ---- |
0xba |
-- |
|
---- avgr_u ---- |
0xbb |
-- |
|
i64x2 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
---- |
0xc0 |
-- |
|
i64x2.neg |
0xc1 |
:+1: |
|
---- |
0xc2 |
-- |
|
---- |
0xc3 |
-- |
|
---- |
0xc4 |
-- |
|
---- |
0xc5 |
-- |
|
---- |
0xc6 |
-- |
|
---- |
0xc7 |
-- |
|
---- |
0xc8 |
-- |
|
---- |
0xc9 |
-- |
|
---- |
0xca |
-- |
|
i64x2.shl |
0xcb |
:+1: |
|
i64x2.shr_s |
0xcc |
:+1: |
|
i64x2.shr_u |
0xcd |
:+1: |
|
i64x2.add |
0xce |
:+1: |
|
---- |
0xcf |
-- |
|
---- |
0xd0 |
-- |
|
i64x2.sub |
0xd1 |
:+1: |
|
---- |
0xd2 |
-- |
|
---- |
0xd3 |
-- |
|
---- |
0xd4 |
-- |
|
i64x2.mul |
0xd5 |
:+1: |
|
---- |
0xd6 |
-- |
|
---- |
0xd7 |
-- |
|
f32x4 Op |
Opcode |
Old Backend Status |
VCode Status |
f32x4.ceil |
0xd8 |
:question: |
|
f32x4.floor |
0xd9 |
:question: |
|
f32x4.trunc |
0xda |
:question: |
|
f32x4.nearest |
0xdb |
:question: |
|
f32x4.abs |
0xe0 |
:+1: |
|
f32x4.neg |
0xe1 |
:+1: |
|
---- round ---- |
0xe2 |
-- |
|
f32x4.sqrt |
0xe3 |
:+1: |
|
f32x4.add |
0xe4 |
:+1: |
|
f32x4.sub |
0xe5 |
:+1: |
|
f32x4.mul |
0xe6 |
:+1: |
|
f32x4.div |
0xe7 |
:+1: |
|
f32x4.min |
0xe8 |
:+1: |
|
f32x4.max |
0xe9 |
:+1: |
|
f32x4.pmin |
0xea |
:question: |
|
f32x4.pmax |
0xeb |
:question: |
|
f64x2 Op |
Opcode |
Old Backend Status |
VCode Status |
f64x2.ceil |
0xdc |
:question: |
|
f64x2.floor |
0xdd |
:question: |
|
f64x2.trunc |
0xde |
:question: |
|
f64x2.nearest |
0xdf |
:question: |
|
f64x2.abs |
0xec |
:+1: |
|
f64x2.neg |
0xed |
:+1: |
|
---- round ---- |
0xee |
-- |
|
f64x2.sqrt |
0xef |
:+1: |
|
f64x2.add |
0xf0 |
:+1: |
|
f64x2.sub |
0xf1 |
:+1: |
|
f64x2.mul |
0xf2 |
:+1: |
|
f64x2.div |
0xf3 |
:+1: |
|
f64x2.min |
0xf4 |
:+1: |
|
f64x2.max |
0xf5 |
:+1: |
|
f64x2.pmin |
0xf6 |
:question: |
|
f64x2.pmax |
0xf7 |
:question: |
|
Conversion Op |
Opcode |
Old Backend Status |
VCode Status |
i32x4.trunc_sat_f32x4_s |
0xf8 |
:+1: |
@jlb6740 |
i32x4.trunc_sat_f32x4_u |
0xf9 |
:+1: |
@jlb6740 |
f32x4.convert_i32x4_s |
0xfa |
:+1: |
@jlb6740 |
f32x4.convert_i32x4_u |
0xfb |
:+1: |
@jlb6740 |
jlb6740 edited Issue #2272:
Status: Currently Not Valid (Initial Status WIP)
Last Update: 10/8/2020
https://gist.github.com/jlb6740/0a495404f6b3cc901e1b8e5ae8148020
Loads |
Opcode |
Old Backend Status |
VCode Status |
v128.load |
0x00 |
:+1: |
|
v128.load8x8_s |
0x01 |
:+1: |
|
v128.load8x8_u |
0x02 |
:+1: |
|
v128.load16x4_s |
0x03 |
:+1: |
|
v128.load16x4_u |
0x04 |
:+1: |
|
v128.load32x2_s |
0x05 |
:+1: |
|
v128.load32x2_u |
0x06 |
:+1: |
|
v128.load8_splat |
0x07 |
:+1: |
|
v128.load16_splat |
0x08 |
:+1: |
|
v128.load32_splat |
0x09 |
:+1: |
|
v128.load64_splat |
0x0a |
:+1: |
|
Stores |
Opcode |
Old Backend Status |
VCode Status |
v128.store |
0x0b |
:+1: |
|
Basic operation |
Opcode |
Old Backend Status |
VCode Status |
v128.const |
0x0c |
:+1: |
|
i8x16.shuffle |
0x0d |
:+1: |
|
i8x16.swizzle |
0x0e |
:+1: |
|
Splat operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.splat |
0x0f |
:+1:v |
|
i16x8.splat |
0x10 |
:+1: |
|
i32x4.splat |
0x11 |
:+1: |
|
i64x2.splat |
0x12 |
:+1: |
|
f32x4.splat |
0x13 |
:+1: |
|
f64x2.splat |
0x14 |
:+1: |
|
Lane operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.extract_lane_s |
0x15 |
:+1: |
|
i8x16.extract_lane_u |
0x16 |
:+1: |
|
i8x16.replace_lane |
0x17 |
:+1: |
|
i16x8.extract_lane_s |
0x18 |
:+1: |
|
i16x8.extract_lane_u |
0x19 |
:+1: |
|
i16x8.replace_lane |
0x1a |
:+1: |
|
i32x4.extract_lane |
0x1b |
:+1: |
|
i32x4.replace_lane |
0x1c |
:+1: |
|
i64x2.extract_lane |
0x1d |
:+1: |
|
i64x2.replace_lane |
0x1e |
:+1: |
|
f32x4.extract_lane |
0x1f |
:+1: |
|
f32x4.replace_lane |
0x20 |
:+1: |
|
f64x2.extract_lane |
0x21 |
:+1: |
|
f64x2.replace_lane |
0x22 |
:+1: |
|
Integer Cmp |
Opcode |
Old Backend Status |
VCode Status |
i8x16.eq |
0x23 |
:+1: |
|
i8x16.ne |
0x24 |
:+1: |
|
i8x16.lt_s |
0x25 |
:+1: |
|
i8x16.lt_u |
0x26 |
:+1: |
|
i8x16.gt_s |
0x27 |
:+1: |
|
i8x16.gt_u |
0x28 |
:+1: |
|
i8x16.le_s |
0x29 |
:+1: |
|
i8x16.le_u |
0x2a |
:+1: |
|
i8x16.ge_s |
0x2b |
:+1: |
|
i8x16.ge_u |
0x2c |
:+1: |
|
i16x8.eq |
0x2d |
:+1: |
|
i16x8.ne |
0x2e |
:+1: |
|
i16x8.lt_s |
0x2f |
:+1: |
|
i16x8.lt_u |
0x30 |
:+1: |
|
i16x8.gt_s |
0x31 |
:+1: |
|
i16x8.gt_u |
0x32 |
:+1: |
|
i16x8.le_s |
0x33 |
:+1: |
|
i16x8.le_u |
0x34 |
:+1: |
|
i16x8.ge_s |
0x35 |
:+1: |
|
i16x8.ge_u |
0x36 |
:+1: |
|
i32x4.eq |
0x37 |
:+1: |
|
i32x4.ne |
0x38 |
:+1: |
|
i32x4.lt_s |
0x39 |
:+1: |
|
i32x4.lt_u |
0x3a |
:+1: |
|
i32x4.gt_s |
0x3b |
:+1: |
|
i32x4.gt_u |
0x3c |
:+1: |
|
i32x4.le_s |
0x3d |
:+1: |
|
i32x4.le_u |
0x3e |
:+1: |
|
i32x4.ge_s |
0x3f |
:+1: |
|
i32x4.ge_u |
0x40 |
:+1: |
|
v128 Op |
Opcode |
Old Backend Status |
VCode Status |
v128.not |
0x4d |
:+1: |
|
v128.and |
0x4e |
:+1: |
|
v128.andnot |
0x4f |
:+1: |
|
v128.or |
0x50 |
:+1: |
|
v128.xor |
0x51 |
:+1: |
|
v128.bitselect |
0x52 |
:+1: |
|
i8x16 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i8x16.abs |
0x60 |
:+1: |
|
i8x16.neg |
0x61 |
:+1: |
|
i8x16.any_true |
0x62 |
:+1: |
|
i8x16.all_true |
0x63 |
:+1: |
|
i8x16.bitmask |
0x64 |
:question: |
|
i8x16.narrow_i16x8_s |
0x65 |
:+1: |
|
i8x16.narrow_i16x8_u |
0x66 |
:+1: |
|
---- widen ---- |
0x67 |
-- |
|
---- widen ---- |
0x68 |
-- |
|
---- widen ---- |
0x69 |
-- |
|
---- widen ---- |
0x6a |
-- |
|
i8x16.shl |
0x6b |
:+1: |
|
i8x16.shr_s |
0x6c |
:+1: |
|
i8x16.shr_u |
0x6d |
:+1: |
|
i8x16.add |
0x6e |
:+1: |
|
i8x16.add_sat_s |
0x6f |
:+1: |
|
i8x16.add_sat_u |
0x70 |
:+1: |
|
i8x16.sub |
0x71 |
:+1: |
|
i8x16.sub_sat_s |
0x72 |
:+1: |
|
i8x16.sub_sat_u |
0x73 |
:+1: |
|
---- dot ---- |
0x74 |
-- |
|
---- mul ---- |
0x75 |
:question: |
|
i8x16.min_s |
0x76 |
:+1: |
|
i8x16.min_u |
0x77 |
:+1: |
|
i8x16.max_s |
0x78 |
:+1: |
|
i8x16.max_u |
0x79 |
:+1: |
|
---- avgr_s ---- |
0x7a |
-- |
|
i8x16.avgr_u |
0x7b |
:+1: |
|
i16x8 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i16x8.abs |
0x80 |
:+1: |
|
i16x8.neg |
0x81 |
:+1: |
|
i16x8.any_true |
0x82 |
:+1: |
|
i16x8.all_true |
0x83 |
:+1: |
|
i16x8.bitmask |
0x84 |
:question: |
|
i16x8.narrow_i32x4_s |
0x85 |
:+1: |
|
i16x8.narrow_i32x4_u |
0x86 |
:+1: |
|
i16x8.widen_low_i8x16_s |
0x87 |
:+1: |
|
i16x8.widen_high_i8x16_s |
0x88 |
:+1: |
|
i16x8.widen_low_i8x16_u |
0x89 |
:+1: |
|
i16x8.widen_high_i8x16_u |
0x8a |
:+1: |
|
i16x8.shl |
0x8b |
:+1: |
|
i16x8.shr_s |
0x8c |
:+1: |
|
i16x8.shr_u |
0x8d |
:+1: |
|
i16x8.add |
0x8e |
:+1: |
|
i16x8.add_sat_s |
0x8f |
:+1: |
|
i16x8.add_sat_u |
0x90 |
:+1: |
|
i16x8.sub |
0x91 |
:+1: |
|
i16x8.sub_sat_s |
0x92 |
:+1: |
|
i16x8.sub_sat_u |
0x93 |
:+1: |
|
---- dot ---- |
0x94 |
-- |
|
i16x8.mul |
0x95 |
:+1: |
|
i16x8.min_s |
0x96 |
:+1: |
|
i16x8.min_u |
0x97 |
:+1: |
|
i16x8.max_s |
0x98 |
:+1: |
|
i16x8.max_u |
0x99 |
:+1: |
|
---- avgr_s ---- |
0x9a |
-- |
|
i16x8.avgr_u |
0x9b |
:+1: |
|
i32x4 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
-- |
-- |
-- |
|
i32x4.abs |
0xa0 |
:+1: |
|
i32x4.neg |
0xa1 |
:+1: |
|
i32x4.any_true |
0xa2 |
:+1: |
|
i32x4.all_true |
0xa3 |
:+1: |
|
i32x4.bitmask |
0xa4 |
:question: |
|
---- narrow ---- |
0xa5 |
-- |
|
---- narrow ---- |
0xa6 |
-- |
|
i32x4.widen_low_i16x8_s |
0xa7 |
:+1: |
|
i32x4.widen_high_i16x8_s |
0xa8 |
:+1: |
|
i32x4.widen_low_i16x8_u |
0xa9 |
:+1: |
|
i32x4.widen_high_i16x8_u |
0xaa |
:+1: |
|
i32x4.shl |
0xab |
:+1: |
|
i32x4.shr_s |
0xac |
:+1: |
|
i32x4.shr_u |
0xad |
:+1: |
|
i32x4.add |
0xae |
:+1: |
|
---- add_sat ---- |
0xaf |
-- |
|
---- add_sat ---- |
0xb0 |
-- |
|
i32x4.sub |
0xb1 |
:+1: |
|
---- sub_sat ---- |
0xb2 |
-- |
|
---- sub_sat ---- |
0xb3 |
-- |
|
---- dot ---- |
0xb4 |
-- |
|
i32x4.mul |
0xb5 |
:+1: |
|
i32x4.min_s |
0xb6 |
:+1: |
|
i32x4.min_u |
0xb7 |
:+1: |
|
i32x4.max_s |
0xb8 |
:+1: |
|
i32x4.max_u |
0xb9 |
:+1: |
|
---- avgr_s ---- |
0xba |
-- |
|
---- avgr_u ---- |
0xbb |
-- |
|
i64x2 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
---- |
0xc0 |
-- |
|
i64x2.neg |
0xc1 |
:+1: |
|
---- |
0xc2 |
-- |
|
---- |
0xc3 |
-- |
|
---- |
0xc4 |
-- |
|
---- |
0xc5 |
-- |
|
---- |
0xc6 |
-- |
|
---- |
0xc7 |
-- |
|
---- |
0xc8 |
-- |
|
---- |
0xc9 |
-- |
|
---- |
0xca |
-- |
|
i64x2.shl |
0xcb |
:+1: |
|
i64x2.shr_s |
0xcc |
:+1: |
|
i64x2.shr_u |
0xcd |
:+1: |
|
i64x2.add |
0xce |
:+1: |
|
---- |
0xcf |
-- |
|
---- |
0xd0 |
-- |
|
i64x2.sub |
0xd1 |
:+1: |
|
---- |
0xd2 |
-- |
|
---- |
0xd3 |
-- |
|
---- |
0xd4 |
-- |
|
i64x2.mul |
0xd5 |
:+1: |
|
---- |
0xd6 |
-- |
|
---- |
0xd7 |
-- |
|
f32x4 Op |
Opcode |
Old Backend Status |
VCode Status |
f32x4.ceil |
0xd8 |
:question: |
|
f32x4.floor |
0xd9 |
:question: |
|
f32x4.trunc |
0xda |
:question: |
|
f32x4.nearest |
0xdb |
:question: |
|
f32x4.abs |
0xe0 |
:+1: |
|
f32x4.neg |
0xe1 |
:+1: |
|
---- round ---- |
0xe2 |
-- |
|
f32x4.sqrt |
0xe3 |
:+1: |
|
f32x4.add |
0xe4 |
:+1: |
|
f32x4.sub |
0xe5 |
:+1: |
|
f32x4.mul |
0xe6 |
:+1: |
|
f32x4.div |
0xe7 |
:+1: |
|
f32x4.min |
0xe8 |
:+1: |
|
f32x4.max |
0xe9 |
:+1: |
|
f32x4.pmin |
0xea |
:question: |
|
f32x4.pmax |
0xeb |
:question: |
|
f64x2 Op |
Opcode |
Old Backend Status |
VCode Status |
f64x2.ceil |
0xdc |
:question: |
|
f64x2.floor |
0xdd |
:question: |
|
f64x2.trunc |
0xde |
:question: |
|
f64x2.nearest |
0xdf |
:question: |
|
f64x2.abs |
0xec |
:+1: |
|
f64x2.neg |
0xed |
:+1: |
|
---- round ---- |
0xee |
-- |
|
f64x2.sqrt |
0xef |
:+1: |
|
f64x2.add |
0xf0 |
:+1: |
|
f64x2.sub |
0xf1 |
:+1: |
|
f64x2.mul |
0xf2 |
:+1: |
|
f64x2.div |
0xf3 |
:+1: |
|
f64x2.min |
0xf4 |
:+1: |
|
f64x2.max |
0xf5 |
:+1: |
|
f64x2.pmin |
0xf6 |
:question: |
|
f64x2.pmax |
0xf7 |
:question: |
|
Conversion Op |
Opcode |
Old Status |
VCode Status |
i32x4.trunc_sat_f32x4_s |
0xf8 |
:+1: |
@jlb6740 |
i32x4.trunc_sat_f32x4_u |
0xf9 |
:+1: |
@jlb6740 |
f32x4.convert_i32x4_s |
0xfa |
:+1: |
@jlb6740 |
f32x4.convert_i32x4_u |
0xfb |
:+1: |
@jlb6740 |
jlb6740 edited Issue #2272:
Status: Currently Not Valid (Initial Status WIP)
Last Update: 10/8/2020
https://gist.github.com/jlb6740/0a495404f6b3cc901e1b8e5ae8148020
Loads |
Opcode |
Old Backend Status |
VCode Status |
v128.load |
0x00 |
:+1: |
|
v128.load8x8_s |
0x01 |
:+1: |
|
v128.load8x8_u |
0x02 |
:+1: |
|
v128.load16x4_s |
0x03 |
:+1: |
|
v128.load16x4_u |
0x04 |
:+1: |
|
v128.load32x2_s |
0x05 |
:+1: |
|
v128.load32x2_u |
0x06 |
:+1: |
|
v128.load8_splat |
0x07 |
:+1: |
|
v128.load16_splat |
0x08 |
:+1: |
|
v128.load32_splat |
0x09 |
:+1: |
|
v128.load64_splat |
0x0a |
:+1: |
|
Stores |
Opcode |
Old Backend Status |
VCode Status |
v128.store |
0x0b |
:+1: |
|
Basic operation |
Opcode |
Old Backend Status |
VCode Status |
v128.const |
0x0c |
:+1: |
|
i8x16.shuffle |
0x0d |
:+1: |
|
i8x16.swizzle |
0x0e |
:+1: |
|
Splat operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.splat |
0x0f |
:+1:v |
|
i16x8.splat |
0x10 |
:+1: |
|
i32x4.splat |
0x11 |
:+1: |
|
i64x2.splat |
0x12 |
:+1: |
|
f32x4.splat |
0x13 |
:+1: |
|
f64x2.splat |
0x14 |
:+1: |
|
Lane operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.extract_lane_s |
0x15 |
:+1: |
|
i8x16.extract_lane_u |
0x16 |
:+1: |
|
i8x16.replace_lane |
0x17 |
:+1: |
|
i16x8.extract_lane_s |
0x18 |
:+1: |
|
i16x8.extract_lane_u |
0x19 |
:+1: |
|
i16x8.replace_lane |
0x1a |
:+1: |
|
i32x4.extract_lane |
0x1b |
:+1: |
|
i32x4.replace_lane |
0x1c |
:+1: |
|
i64x2.extract_lane |
0x1d |
:+1: |
|
i64x2.replace_lane |
0x1e |
:+1: |
|
f32x4.extract_lane |
0x1f |
:+1: |
|
f32x4.replace_lane |
0x20 |
:+1: |
|
f64x2.extract_lane |
0x21 |
:+1: |
|
f64x2.replace_lane |
0x22 |
:+1: |
|
Integer Cmp |
Opcode |
Old Backend Status |
VCode Status |
i8x16.eq |
0x23 |
:+1: |
|
i8x16.ne |
0x24 |
:+1: |
|
i8x16.lt_s |
0x25 |
:+1: |
|
i8x16.lt_u |
0x26 |
:+1: |
|
i8x16.gt_s |
0x27 |
:+1: |
|
i8x16.gt_u |
0x28 |
:+1: |
|
i8x16.le_s |
0x29 |
:+1: |
|
i8x16.le_u |
0x2a |
:+1: |
|
i8x16.ge_s |
0x2b |
:+1: |
|
i8x16.ge_u |
0x2c |
:+1: |
|
i16x8.eq |
0x2d |
:+1: |
|
i16x8.ne |
0x2e |
:+1: |
|
i16x8.lt_s |
0x2f |
:+1: |
|
i16x8.lt_u |
0x30 |
:+1: |
|
i16x8.gt_s |
0x31 |
:+1: |
|
i16x8.gt_u |
0x32 |
:+1: |
|
i16x8.le_s |
0x33 |
:+1: |
|
i16x8.le_u |
0x34 |
:+1: |
|
i16x8.ge_s |
0x35 |
:+1: |
|
i16x8.ge_u |
0x36 |
:+1: |
|
i32x4.eq |
0x37 |
:+1: |
|
i32x4.ne |
0x38 |
:+1: |
|
i32x4.lt_s |
0x39 |
:+1: |
|
i32x4.lt_u |
0x3a |
:+1: |
|
i32x4.gt_s |
0x3b |
:+1: |
|
i32x4.gt_u |
0x3c |
:+1: |
|
i32x4.le_s |
0x3d |
:+1: |
|
i32x4.le_u |
0x3e |
:+1: |
|
i32x4.ge_s |
0x3f |
:+1: |
|
i32x4.ge_u |
0x40 |
:+1: |
|
v128 Op |
Opcode |
Old Backend Status |
VCode Status |
v128.not |
0x4d |
:+1: |
|
v128.and |
0x4e |
:+1: |
|
v128.andnot |
0x4f |
:+1: |
|
v128.or |
0x50 |
:+1: |
|
v128.xor |
0x51 |
:+1: |
|
v128.bitselect |
0x52 |
:+1: |
|
i8x16 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i8x16.abs |
0x60 |
:+1: |
|
i8x16.neg |
0x61 |
:+1: |
|
i8x16.any_true |
0x62 |
:+1: |
|
i8x16.all_true |
0x63 |
:+1: |
|
i8x16.bitmask |
0x64 |
:question: |
|
i8x16.narrow_i16x8_s |
0x65 |
:+1: |
|
i8x16.narrow_i16x8_u |
0x66 |
:+1: |
|
---- widen ---- |
0x67 |
-- |
|
---- widen ---- |
0x68 |
-- |
|
---- widen ---- |
0x69 |
-- |
|
---- widen ---- |
0x6a |
-- |
|
i8x16.shl |
0x6b |
:+1: |
|
i8x16.shr_s |
0x6c |
:+1: |
|
i8x16.shr_u |
0x6d |
:+1: |
|
i8x16.add |
0x6e |
:+1: |
|
i8x16.add_sat_s |
0x6f |
:+1: |
|
i8x16.add_sat_u |
0x70 |
:+1: |
|
i8x16.sub |
0x71 |
:+1: |
|
i8x16.sub_sat_s |
0x72 |
:+1: |
|
i8x16.sub_sat_u |
0x73 |
:+1: |
|
---- dot ---- |
0x74 |
-- |
|
---- mul ---- |
0x75 |
:question: |
|
i8x16.min_s |
0x76 |
:+1: |
|
i8x16.min_u |
0x77 |
:+1: |
|
i8x16.max_s |
0x78 |
:+1: |
|
i8x16.max_u |
0x79 |
:+1: |
|
---- avgr_s ---- |
0x7a |
-- |
|
i8x16.avgr_u |
0x7b |
:+1: |
|
i16x8 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i16x8.abs |
0x80 |
:+1: |
|
i16x8.neg |
0x81 |
:+1: |
|
i16x8.any_true |
0x82 |
:+1: |
|
i16x8.all_true |
0x83 |
:+1: |
|
i16x8.bitmask |
0x84 |
:question: |
|
i16x8.narrow_i32x4_s |
0x85 |
:+1: |
|
i16x8.narrow_i32x4_u |
0x86 |
:+1: |
|
i16x8.widen_low_i8x16_s |
0x87 |
:+1: |
|
i16x8.widen_high_i8x16_s |
0x88 |
:+1: |
|
i16x8.widen_low_i8x16_u |
0x89 |
:+1: |
|
i16x8.widen_high_i8x16_u |
0x8a |
:+1: |
|
i16x8.shl |
0x8b |
:+1: |
|
i16x8.shr_s |
0x8c |
:+1: |
|
i16x8.shr_u |
0x8d |
:+1: |
|
i16x8.add |
0x8e |
:+1: |
|
i16x8.add_sat_s |
0x8f |
:+1: |
|
i16x8.add_sat_u |
0x90 |
:+1: |
|
i16x8.sub |
0x91 |
:+1: |
|
i16x8.sub_sat_s |
0x92 |
:+1: |
|
i16x8.sub_sat_u |
0x93 |
:+1: |
|
---- dot ---- |
0x94 |
-- |
|
i16x8.mul |
0x95 |
:+1: |
|
i16x8.min_s |
0x96 |
:+1: |
|
i16x8.min_u |
0x97 |
:+1: |
|
i16x8.max_s |
0x98 |
:+1: |
|
i16x8.max_u |
0x99 |
:+1: |
|
---- avgr_s ---- |
0x9a |
-- |
|
i16x8.avgr_u |
0x9b |
:+1: |
|
i32x4 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
-- |
-- |
-- |
|
i32x4.abs |
0xa0 |
:+1: |
|
i32x4.neg |
0xa1 |
:+1: |
|
i32x4.any_true |
0xa2 |
:+1: |
|
i32x4.all_true |
0xa3 |
:+1: |
|
i32x4.bitmask |
0xa4 |
:question: |
|
---- narrow ---- |
0xa5 |
-- |
|
---- narrow ---- |
0xa6 |
-- |
|
i32x4.widen_low_i16x8_s |
0xa7 |
:+1: |
|
i32x4.widen_high_i16x8_s |
0xa8 |
:+1: |
|
i32x4.widen_low_i16x8_u |
0xa9 |
:+1: |
|
i32x4.widen_high_i16x8_u |
0xaa |
:+1: |
|
i32x4.shl |
0xab |
:+1: |
|
i32x4.shr_s |
0xac |
:+1: |
|
i32x4.shr_u |
0xad |
:+1: |
|
i32x4.add |
0xae |
:+1: |
|
---- add_sat ---- |
0xaf |
-- |
|
---- add_sat ---- |
0xb0 |
-- |
|
i32x4.sub |
0xb1 |
:+1: |
|
---- sub_sat ---- |
0xb2 |
-- |
|
---- sub_sat ---- |
0xb3 |
-- |
|
---- dot ---- |
0xb4 |
-- |
|
i32x4.mul |
0xb5 |
:+1: |
|
i32x4.min_s |
0xb6 |
:+1: |
|
i32x4.min_u |
0xb7 |
:+1: |
|
i32x4.max_s |
0xb8 |
:+1: |
|
i32x4.max_u |
0xb9 |
:+1: |
|
---- avgr_s ---- |
0xba |
-- |
|
---- avgr_u ---- |
0xbb |
-- |
|
i64x2 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
---- |
0xc0 |
-- |
|
i64x2.neg |
0xc1 |
:+1: |
|
---- |
0xc2 |
-- |
|
---- |
0xc3 |
-- |
|
---- |
0xc4 |
-- |
|
---- |
0xc5 |
-- |
|
---- |
0xc6 |
-- |
|
---- |
0xc7 |
-- |
|
---- |
0xc8 |
-- |
|
---- |
0xc9 |
-- |
|
---- |
0xca |
-- |
|
i64x2.shl |
0xcb |
:+1: |
|
i64x2.shr_s |
0xcc |
:+1: |
|
i64x2.shr_u |
0xcd |
:+1: |
|
i64x2.add |
0xce |
:+1: |
|
---- |
0xcf |
-- |
|
---- |
0xd0 |
-- |
|
i64x2.sub |
0xd1 |
:+1: |
|
---- |
0xd2 |
-- |
|
---- |
0xd3 |
-- |
|
---- |
0xd4 |
-- |
|
i64x2.mul |
0xd5 |
:+1: |
|
---- |
0xd6 |
-- |
|
---- |
0xd7 |
-- |
|
f32x4 Op |
Opcode |
Old Backend Status |
VCode Status |
f32x4.ceil |
0xd8 |
:question: |
|
f32x4.floor |
0xd9 |
:question: |
|
f32x4.trunc |
0xda |
:question: |
|
f32x4.nearest |
0xdb |
:question: |
|
f32x4.abs |
0xe0 |
:+1: |
|
f32x4.neg |
0xe1 |
:+1: |
|
---- round ---- |
0xe2 |
-- |
|
f32x4.sqrt |
0xe3 |
:+1: |
|
f32x4.add |
0xe4 |
:+1: |
|
f32x4.sub |
0xe5 |
:+1: |
|
f32x4.mul |
0xe6 |
:+1: |
|
f32x4.div |
0xe7 |
:+1: |
|
f32x4.min |
0xe8 |
:+1: |
|
f32x4.max |
0xe9 |
:+1: |
|
f32x4.pmin |
0xea |
:question: |
|
f32x4.pmax |
0xeb |
:question: |
|
f64x2 Op |
Opcode |
Previous |
VCode Status |
f64x2.ceil |
0xdc |
:question: |
|
f64x2.floor |
0xdd |
:question: |
|
f64x2.trunc |
0xde |
:question: |
|
f64x2.nearest |
0xdf |
:question: |
|
f64x2.abs |
0xec |
:+1: |
|
f64x2.neg |
0xed |
:+1: |
|
---- round ---- |
0xee |
-- |
|
f64x2.sqrt |
0xef |
:+1: |
|
f64x2.add |
0xf0 |
:+1: |
|
f64x2.sub |
0xf1 |
:+1: |
|
f64x2.mul |
0xf2 |
:+1: |
|
f64x2.div |
0xf3 |
:+1: |
|
f64x2.min |
0xf4 |
:+1: |
|
f64x2.max |
0xf5 |
:+1: |
|
f64x2.pmin |
0xf6 |
:question: |
|
f64x2.pmax |
0xf7 |
:question: |
|
Conversion Op |
Opcode |
Previous |
VCode Status |
i32x4.trunc_sat_f32x4_s |
0xf8 |
:+1: |
@jlb6740 |
i32x4.trunc_sat_f32x4_u |
0xf9 |
:+1: |
@jlb6740 |
f32x4.convert_i32x4_s |
0xfa |
:+1: |
@jlb6740 |
f32x4.convert_i32x4_u |
0xfb |
:+1: |
@jlb6740 |
jlb6740 edited Issue #2272:
Status: Currently Not Valid (Initial Status WIP)
Last Update: 10/8/2020
https://gist.github.com/jlb6740/0a495404f6b3cc901e1b8e5ae8148020
Loads |
Opcode |
Old Backend Status |
VCode Status |
v128.load |
0x00 |
:+1: |
:+1: |
v128.load8x8_s |
0x01 |
:+1: |
-- |
v128.load8x8_u |
0x02 |
:+1: |
-- |
v128.load16x4_s |
0x03 |
:+1: |
-- |
v128.load16x4_u |
0x04 |
:+1: |
-- |
v128.load32x2_s |
0x05 |
:+1: |
-- |
v128.load32x2_u |
0x06 |
:+1: |
-- |
v128.load8_splat |
0x07 |
:+1: |
|
v128.load16_splat |
0x08 |
:+1: |
|
v128.load32_splat |
0x09 |
:+1: |
|
v128.load64_splat |
0x0a |
:+1: |
|
Stores |
Opcode |
Old Backend Status |
VCode Status |
v128.store |
0x0b |
:+1: |
|
Basic operation |
Opcode |
Old Backend Status |
VCode Status |
v128.const |
0x0c |
:+1: |
|
i8x16.shuffle |
0x0d |
:+1: |
|
i8x16.swizzle |
0x0e |
:+1: |
|
Splat operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.splat |
0x0f |
:+1:v |
|
i16x8.splat |
0x10 |
:+1: |
|
i32x4.splat |
0x11 |
:+1: |
|
i64x2.splat |
0x12 |
:+1: |
|
f32x4.splat |
0x13 |
:+1: |
|
f64x2.splat |
0x14 |
:+1: |
|
Lane operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.extract_lane_s |
0x15 |
:+1: |
|
i8x16.extract_lane_u |
0x16 |
:+1: |
|
i8x16.replace_lane |
0x17 |
:+1: |
|
i16x8.extract_lane_s |
0x18 |
:+1: |
|
i16x8.extract_lane_u |
0x19 |
:+1: |
|
i16x8.replace_lane |
0x1a |
:+1: |
|
i32x4.extract_lane |
0x1b |
:+1: |
|
i32x4.replace_lane |
0x1c |
:+1: |
|
i64x2.extract_lane |
0x1d |
:+1: |
|
i64x2.replace_lane |
0x1e |
:+1: |
|
f32x4.extract_lane |
0x1f |
:+1: |
|
f32x4.replace_lane |
0x20 |
:+1: |
|
f64x2.extract_lane |
0x21 |
:+1: |
|
f64x2.replace_lane |
0x22 |
:+1: |
|
Integer Cmp |
Opcode |
Old Backend Status |
VCode Status |
i8x16.eq |
0x23 |
:+1: |
|
i8x16.ne |
0x24 |
:+1: |
|
i8x16.lt_s |
0x25 |
:+1: |
|
i8x16.lt_u |
0x26 |
:+1: |
|
i8x16.gt_s |
0x27 |
:+1: |
|
i8x16.gt_u |
0x28 |
:+1: |
|
i8x16.le_s |
0x29 |
:+1: |
|
i8x16.le_u |
0x2a |
:+1: |
|
i8x16.ge_s |
0x2b |
:+1: |
|
i8x16.ge_u |
0x2c |
:+1: |
|
i16x8.eq |
0x2d |
:+1: |
|
i16x8.ne |
0x2e |
:+1: |
|
i16x8.lt_s |
0x2f |
:+1: |
|
i16x8.lt_u |
0x30 |
:+1: |
|
i16x8.gt_s |
0x31 |
:+1: |
|
i16x8.gt_u |
0x32 |
:+1: |
|
i16x8.le_s |
0x33 |
:+1: |
|
i16x8.le_u |
0x34 |
:+1: |
|
i16x8.ge_s |
0x35 |
:+1: |
|
i16x8.ge_u |
0x36 |
:+1: |
|
i32x4.eq |
0x37 |
:+1: |
|
i32x4.ne |
0x38 |
:+1: |
|
i32x4.lt_s |
0x39 |
:+1: |
|
i32x4.lt_u |
0x3a |
:+1: |
|
i32x4.gt_s |
0x3b |
:+1: |
|
i32x4.gt_u |
0x3c |
:+1: |
|
i32x4.le_s |
0x3d |
:+1: |
|
i32x4.le_u |
0x3e |
:+1: |
|
i32x4.ge_s |
0x3f |
:+1: |
|
i32x4.ge_u |
0x40 |
:+1: |
|
v128 Op |
Opcode |
Old Backend Status |
VCode Status |
v128.not |
0x4d |
:+1: |
|
v128.and |
0x4e |
:+1: |
|
v128.andnot |
0x4f |
:+1: |
|
v128.or |
0x50 |
:+1: |
|
v128.xor |
0x51 |
:+1: |
|
v128.bitselect |
0x52 |
:+1: |
|
i8x16 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i8x16.abs |
0x60 |
:+1: |
|
i8x16.neg |
0x61 |
:+1: |
|
i8x16.any_true |
0x62 |
:+1: |
|
i8x16.all_true |
0x63 |
:+1: |
|
i8x16.bitmask |
0x64 |
:question: |
|
i8x16.narrow_i16x8_s |
0x65 |
:+1: |
|
i8x16.narrow_i16x8_u |
0x66 |
:+1: |
|
---- widen ---- |
0x67 |
-- |
|
---- widen ---- |
0x68 |
-- |
|
---- widen ---- |
0x69 |
-- |
|
---- widen ---- |
0x6a |
-- |
|
i8x16.shl |
0x6b |
:+1: |
|
i8x16.shr_s |
0x6c |
:+1: |
|
i8x16.shr_u |
0x6d |
:+1: |
|
i8x16.add |
0x6e |
:+1: |
|
i8x16.add_sat_s |
0x6f |
:+1: |
|
i8x16.add_sat_u |
0x70 |
:+1: |
|
i8x16.sub |
0x71 |
:+1: |
|
i8x16.sub_sat_s |
0x72 |
:+1: |
|
i8x16.sub_sat_u |
0x73 |
:+1: |
|
---- dot ---- |
0x74 |
-- |
|
---- mul ---- |
0x75 |
:question: |
|
i8x16.min_s |
0x76 |
:+1: |
|
i8x16.min_u |
0x77 |
:+1: |
|
i8x16.max_s |
0x78 |
:+1: |
|
i8x16.max_u |
0x79 |
:+1: |
|
---- avgr_s ---- |
0x7a |
-- |
|
i8x16.avgr_u |
0x7b |
:+1: |
|
i16x8 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i16x8.abs |
0x80 |
:+1: |
|
i16x8.neg |
0x81 |
:+1: |
|
i16x8.any_true |
0x82 |
:+1: |
|
i16x8.all_true |
0x83 |
:+1: |
|
i16x8.bitmask |
0x84 |
:question: |
|
i16x8.narrow_i32x4_s |
0x85 |
:+1: |
|
i16x8.narrow_i32x4_u |
0x86 |
:+1: |
|
i16x8.widen_low_i8x16_s |
0x87 |
:+1: |
|
i16x8.widen_high_i8x16_s |
0x88 |
:+1: |
|
i16x8.widen_low_i8x16_u |
0x89 |
:+1: |
|
i16x8.widen_high_i8x16_u |
0x8a |
:+1: |
|
i16x8.shl |
0x8b |
:+1: |
|
i16x8.shr_s |
0x8c |
:+1: |
|
i16x8.shr_u |
0x8d |
:+1: |
|
i16x8.add |
0x8e |
:+1: |
|
i16x8.add_sat_s |
0x8f |
:+1: |
|
i16x8.add_sat_u |
0x90 |
:+1: |
|
i16x8.sub |
0x91 |
:+1: |
|
i16x8.sub_sat_s |
0x92 |
:+1: |
|
i16x8.sub_sat_u |
0x93 |
:+1: |
|
---- dot ---- |
0x94 |
-- |
|
i16x8.mul |
0x95 |
:+1: |
|
i16x8.min_s |
0x96 |
:+1: |
|
i16x8.min_u |
0x97 |
:+1: |
|
i16x8.max_s |
0x98 |
:+1: |
|
i16x8.max_u |
0x99 |
:+1: |
|
---- avgr_s ---- |
0x9a |
-- |
|
i16x8.avgr_u |
0x9b |
:+1: |
|
i32x4 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
-- |
-- |
-- |
|
i32x4.abs |
0xa0 |
:+1: |
|
i32x4.neg |
0xa1 |
:+1: |
|
i32x4.any_true |
0xa2 |
:+1: |
|
i32x4.all_true |
0xa3 |
:+1: |
|
i32x4.bitmask |
0xa4 |
:question: |
|
---- narrow ---- |
0xa5 |
-- |
|
---- narrow ---- |
0xa6 |
-- |
|
i32x4.widen_low_i16x8_s |
0xa7 |
:+1: |
|
i32x4.widen_high_i16x8_s |
0xa8 |
:+1: |
|
i32x4.widen_low_i16x8_u |
0xa9 |
:+1: |
|
i32x4.widen_high_i16x8_u |
0xaa |
:+1: |
|
i32x4.shl |
0xab |
:+1: |
|
i32x4.shr_s |
0xac |
:+1: |
|
i32x4.shr_u |
0xad |
:+1: |
|
i32x4.add |
0xae |
:+1: |
|
---- add_sat ---- |
0xaf |
-- |
|
---- add_sat ---- |
0xb0 |
-- |
|
i32x4.sub |
0xb1 |
:+1: |
|
---- sub_sat ---- |
0xb2 |
-- |
|
---- sub_sat ---- |
0xb3 |
-- |
|
---- dot ---- |
0xb4 |
-- |
|
i32x4.mul |
0xb5 |
:+1: |
|
i32x4.min_s |
0xb6 |
:+1: |
|
i32x4.min_u |
0xb7 |
:+1: |
|
i32x4.max_s |
0xb8 |
:+1: |
|
i32x4.max_u |
0xb9 |
:+1: |
|
---- avgr_s ---- |
0xba |
-- |
|
---- avgr_u ---- |
0xbb |
-- |
|
i64x2 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
---- |
0xc0 |
-- |
|
i64x2.neg |
0xc1 |
:+1: |
|
---- |
0xc2 |
-- |
|
---- |
0xc3 |
-- |
|
---- |
0xc4 |
-- |
|
---- |
0xc5 |
-- |
|
---- |
0xc6 |
-- |
|
---- |
0xc7 |
-- |
|
---- |
0xc8 |
-- |
|
---- |
0xc9 |
-- |
|
---- |
0xca |
-- |
|
i64x2.shl |
0xcb |
:+1: |
|
i64x2.shr_s |
0xcc |
:+1: |
|
i64x2.shr_u |
0xcd |
:+1: |
|
i64x2.add |
0xce |
:+1: |
|
---- |
0xcf |
-- |
|
---- |
0xd0 |
-- |
|
i64x2.sub |
0xd1 |
:+1: |
|
---- |
0xd2 |
-- |
|
---- |
0xd3 |
-- |
|
---- |
0xd4 |
-- |
|
i64x2.mul |
0xd5 |
:+1: |
|
---- |
0xd6 |
-- |
|
---- |
0xd7 |
-- |
|
f32x4 Op |
Opcode |
Old Backend Status |
VCode Status |
f32x4.ceil |
0xd8 |
:question: |
|
f32x4.floor |
0xd9 |
:question: |
|
f32x4.trunc |
0xda |
:question: |
|
f32x4.nearest |
0xdb |
:question: |
|
f32x4.abs |
0xe0 |
:+1: |
|
f32x4.neg |
0xe1 |
:+1: |
|
---- round ---- |
0xe2 |
-- |
|
f32x4.sqrt |
0xe3 |
:+1: |
|
f32x4.add |
0xe4 |
:+1: |
|
f32x4.sub |
0xe5 |
:+1: |
|
f32x4.mul |
0xe6 |
:+1: |
|
f32x4.div |
0xe7 |
:+1: |
|
f32x4.min |
0xe8 |
:+1: |
|
f32x4.max |
0xe9 |
:+1: |
|
f32x4.pmin |
0xea |
:question: |
|
f32x4.pmax |
0xeb |
:question: |
|
f64x2 Op |
Opcode |
Previous |
VCode Status |
f64x2.ceil |
0xdc |
:question: |
|
f64x2.floor |
0xdd |
:question: |
|
f64x2.trunc |
0xde |
:question: |
|
f64x2.nearest |
0xdf |
:question: |
|
f64x2.abs |
0xec |
:+1: |
|
f64x2.neg |
0xed |
:+1: |
|
---- round ---- |
0xee |
-- |
|
f64x2.sqrt |
0xef |
:+1: |
|
f64x2.add |
0xf0 |
:+1: |
|
f64x2.sub |
0xf1 |
:+1: |
|
f64x2.mul |
0xf2 |
:+1: |
|
f64x2.div |
0xf3 |
:+1: |
|
f64x2.min |
0xf4 |
:+1: |
|
f64x2.max |
0xf5 |
:+1: |
|
f64x2.pmin |
0xf6 |
:question: |
|
f64x2.pmax |
0xf7 |
:question: |
|
Conversion Op |
Opcode |
Previous |
VCode Status |
i32x4.trunc_sat_f32x4_s |
0xf8 |
:+1: |
@jlb6740 |
i32x4.trunc_sat_f32x4_u |
0xf9 |
:+1: |
@jlb6740 |
f32x4.convert_i32x4_s |
0xfa |
:+1: |
@jlb6740 |
f32x4.convert_i32x4_u |
0xfb |
:+1: |
@jlb6740 |
jlb6740 edited Issue #2272:
Status: Currently Not Valid (Initial Status WIP)
Last Update: 10/8/2020
https://gist.github.com/jlb6740/0a495404f6b3cc901e1b8e5ae8148020
Loads |
Opcode |
Old Backend Status |
VCode Status |
v128.load |
0x00 |
:+1: |
:+1: |
v128.load8x8_s |
0x01 |
:+1: |
-- |
v128.load8x8_u |
0x02 |
:+1: |
-- |
v128.load16x4_s |
0x03 |
:+1: |
-- |
v128.load16x4_u |
0x04 |
:+1: |
-- |
v128.load32x2_s |
0x05 |
:+1: |
-- |
v128.load32x2_u |
0x06 |
:+1: |
-- |
v128.load8_splat |
0x07 |
:+1: |
-- |
v128.load16_splat |
0x08 |
:+1: |
-- |
v128.load32_splat |
0x09 |
:+1: |
-- |
v128.load64_splat |
0x0a |
:+1: |
-- |
Stores |
Opcode |
Old Backend Status |
VCode Status |
v128.store |
0x0b |
:+1: |
:+1: |
Basic operation |
Opcode |
Old Backend Status |
VCode Status |
v128.const |
0x0c |
:+1: |
|
i8x16.shuffle |
0x0d |
:+1: |
|
i8x16.swizzle |
0x0e |
:+1: |
|
Splat operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.splat |
0x0f |
:+1:v |
|
i16x8.splat |
0x10 |
:+1: |
|
i32x4.splat |
0x11 |
:+1: |
|
i64x2.splat |
0x12 |
:+1: |
|
f32x4.splat |
0x13 |
:+1: |
|
f64x2.splat |
0x14 |
:+1: |
|
Lane operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.extract_lane_s |
0x15 |
:+1: |
|
i8x16.extract_lane_u |
0x16 |
:+1: |
|
i8x16.replace_lane |
0x17 |
:+1: |
|
i16x8.extract_lane_s |
0x18 |
:+1: |
|
i16x8.extract_lane_u |
0x19 |
:+1: |
|
i16x8.replace_lane |
0x1a |
:+1: |
|
i32x4.extract_lane |
0x1b |
:+1: |
|
i32x4.replace_lane |
0x1c |
:+1: |
|
i64x2.extract_lane |
0x1d |
:+1: |
|
i64x2.replace_lane |
0x1e |
:+1: |
|
f32x4.extract_lane |
0x1f |
:+1: |
|
f32x4.replace_lane |
0x20 |
:+1: |
|
f64x2.extract_lane |
0x21 |
:+1: |
|
f64x2.replace_lane |
0x22 |
:+1: |
|
Integer Cmp |
Opcode |
Old Backend Status |
VCode Status |
i8x16.eq |
0x23 |
:+1: |
|
i8x16.ne |
0x24 |
:+1: |
|
i8x16.lt_s |
0x25 |
:+1: |
|
i8x16.lt_u |
0x26 |
:+1: |
|
i8x16.gt_s |
0x27 |
:+1: |
|
i8x16.gt_u |
0x28 |
:+1: |
|
i8x16.le_s |
0x29 |
:+1: |
|
i8x16.le_u |
0x2a |
:+1: |
|
i8x16.ge_s |
0x2b |
:+1: |
|
i8x16.ge_u |
0x2c |
:+1: |
|
i16x8.eq |
0x2d |
:+1: |
|
i16x8.ne |
0x2e |
:+1: |
|
i16x8.lt_s |
0x2f |
:+1: |
|
i16x8.lt_u |
0x30 |
:+1: |
|
i16x8.gt_s |
0x31 |
:+1: |
|
i16x8.gt_u |
0x32 |
:+1: |
|
i16x8.le_s |
0x33 |
:+1: |
|
i16x8.le_u |
0x34 |
:+1: |
|
i16x8.ge_s |
0x35 |
:+1: |
|
i16x8.ge_u |
0x36 |
:+1: |
|
i32x4.eq |
0x37 |
:+1: |
|
i32x4.ne |
0x38 |
:+1: |
|
i32x4.lt_s |
0x39 |
:+1: |
|
i32x4.lt_u |
0x3a |
:+1: |
|
i32x4.gt_s |
0x3b |
:+1: |
|
i32x4.gt_u |
0x3c |
:+1: |
|
i32x4.le_s |
0x3d |
:+1: |
|
i32x4.le_u |
0x3e |
:+1: |
|
i32x4.ge_s |
0x3f |
:+1: |
|
i32x4.ge_u |
0x40 |
:+1: |
|
v128 Op |
Opcode |
Old Backend Status |
VCode Status |
v128.not |
0x4d |
:+1: |
|
v128.and |
0x4e |
:+1: |
|
v128.andnot |
0x4f |
:+1: |
|
v128.or |
0x50 |
:+1: |
|
v128.xor |
0x51 |
:+1: |
|
v128.bitselect |
0x52 |
:+1: |
|
i8x16 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i8x16.abs |
0x60 |
:+1: |
|
i8x16.neg |
0x61 |
:+1: |
|
i8x16.any_true |
0x62 |
:+1: |
|
i8x16.all_true |
0x63 |
:+1: |
|
i8x16.bitmask |
0x64 |
:question: |
|
i8x16.narrow_i16x8_s |
0x65 |
:+1: |
|
i8x16.narrow_i16x8_u |
0x66 |
:+1: |
|
---- widen ---- |
0x67 |
-- |
|
---- widen ---- |
0x68 |
-- |
|
---- widen ---- |
0x69 |
-- |
|
---- widen ---- |
0x6a |
-- |
|
i8x16.shl |
0x6b |
:+1: |
|
i8x16.shr_s |
0x6c |
:+1: |
|
i8x16.shr_u |
0x6d |
:+1: |
|
i8x16.add |
0x6e |
:+1: |
|
i8x16.add_sat_s |
0x6f |
:+1: |
|
i8x16.add_sat_u |
0x70 |
:+1: |
|
i8x16.sub |
0x71 |
:+1: |
|
i8x16.sub_sat_s |
0x72 |
:+1: |
|
i8x16.sub_sat_u |
0x73 |
:+1: |
|
---- dot ---- |
0x74 |
-- |
|
---- mul ---- |
0x75 |
:question: |
|
i8x16.min_s |
0x76 |
:+1: |
|
i8x16.min_u |
0x77 |
:+1: |
|
i8x16.max_s |
0x78 |
:+1: |
|
i8x16.max_u |
0x79 |
:+1: |
|
---- avgr_s ---- |
0x7a |
-- |
|
i8x16.avgr_u |
0x7b |
:+1: |
|
i16x8 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i16x8.abs |
0x80 |
:+1: |
|
i16x8.neg |
0x81 |
:+1: |
|
i16x8.any_true |
0x82 |
:+1: |
|
i16x8.all_true |
0x83 |
:+1: |
|
i16x8.bitmask |
0x84 |
:question: |
|
i16x8.narrow_i32x4_s |
0x85 |
:+1: |
|
i16x8.narrow_i32x4_u |
0x86 |
:+1: |
|
i16x8.widen_low_i8x16_s |
0x87 |
:+1: |
|
i16x8.widen_high_i8x16_s |
0x88 |
:+1: |
|
i16x8.widen_low_i8x16_u |
0x89 |
:+1: |
|
i16x8.widen_high_i8x16_u |
0x8a |
:+1: |
|
i16x8.shl |
0x8b |
:+1: |
|
i16x8.shr_s |
0x8c |
:+1: |
|
i16x8.shr_u |
0x8d |
:+1: |
|
i16x8.add |
0x8e |
:+1: |
|
i16x8.add_sat_s |
0x8f |
:+1: |
|
i16x8.add_sat_u |
0x90 |
:+1: |
|
i16x8.sub |
0x91 |
:+1: |
|
i16x8.sub_sat_s |
0x92 |
:+1: |
|
i16x8.sub_sat_u |
0x93 |
:+1: |
|
---- dot ---- |
0x94 |
-- |
|
i16x8.mul |
0x95 |
:+1: |
|
i16x8.min_s |
0x96 |
:+1: |
|
i16x8.min_u |
0x97 |
:+1: |
|
i16x8.max_s |
0x98 |
:+1: |
|
i16x8.max_u |
0x99 |
:+1: |
|
---- avgr_s ---- |
0x9a |
-- |
|
i16x8.avgr_u |
0x9b |
:+1: |
|
i32x4 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
-- |
-- |
-- |
|
i32x4.abs |
0xa0 |
:+1: |
|
i32x4.neg |
0xa1 |
:+1: |
|
i32x4.any_true |
0xa2 |
:+1: |
|
i32x4.all_true |
0xa3 |
:+1: |
|
i32x4.bitmask |
0xa4 |
:question: |
|
---- narrow ---- |
0xa5 |
-- |
|
---- narrow ---- |
0xa6 |
-- |
|
i32x4.widen_low_i16x8_s |
0xa7 |
:+1: |
|
i32x4.widen_high_i16x8_s |
0xa8 |
:+1: |
|
i32x4.widen_low_i16x8_u |
0xa9 |
:+1: |
|
i32x4.widen_high_i16x8_u |
0xaa |
:+1: |
|
i32x4.shl |
0xab |
:+1: |
|
i32x4.shr_s |
0xac |
:+1: |
|
i32x4.shr_u |
0xad |
:+1: |
|
i32x4.add |
0xae |
:+1: |
|
---- add_sat ---- |
0xaf |
-- |
|
---- add_sat ---- |
0xb0 |
-- |
|
i32x4.sub |
0xb1 |
:+1: |
|
---- sub_sat ---- |
0xb2 |
-- |
|
---- sub_sat ---- |
0xb3 |
-- |
|
---- dot ---- |
0xb4 |
-- |
|
i32x4.mul |
0xb5 |
:+1: |
|
i32x4.min_s |
0xb6 |
:+1: |
|
i32x4.min_u |
0xb7 |
:+1: |
|
i32x4.max_s |
0xb8 |
:+1: |
|
i32x4.max_u |
0xb9 |
:+1: |
|
---- avgr_s ---- |
0xba |
-- |
|
---- avgr_u ---- |
0xbb |
-- |
|
i64x2 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
---- |
0xc0 |
-- |
|
i64x2.neg |
0xc1 |
:+1: |
|
---- |
0xc2 |
-- |
|
---- |
0xc3 |
-- |
|
---- |
0xc4 |
-- |
|
---- |
0xc5 |
-- |
|
---- |
0xc6 |
-- |
|
---- |
0xc7 |
-- |
|
---- |
0xc8 |
-- |
|
---- |
0xc9 |
-- |
|
---- |
0xca |
-- |
|
i64x2.shl |
0xcb |
:+1: |
|
i64x2.shr_s |
0xcc |
:+1: |
|
i64x2.shr_u |
0xcd |
:+1: |
|
i64x2.add |
0xce |
:+1: |
|
---- |
0xcf |
-- |
|
---- |
0xd0 |
-- |
|
i64x2.sub |
0xd1 |
:+1: |
|
---- |
0xd2 |
-- |
|
---- |
0xd3 |
-- |
|
---- |
0xd4 |
-- |
|
i64x2.mul |
0xd5 |
:+1: |
|
---- |
0xd6 |
-- |
|
---- |
0xd7 |
-- |
|
f32x4 Op |
Opcode |
Old Backend Status |
VCode Status |
f32x4.ceil |
0xd8 |
:question: |
|
f32x4.floor |
0xd9 |
:question: |
|
f32x4.trunc |
0xda |
:question: |
|
f32x4.nearest |
0xdb |
:question: |
|
f32x4.abs |
0xe0 |
:+1: |
|
f32x4.neg |
0xe1 |
:+1: |
|
---- round ---- |
0xe2 |
-- |
|
f32x4.sqrt |
0xe3 |
:+1: |
|
f32x4.add |
0xe4 |
:+1: |
|
f32x4.sub |
0xe5 |
:+1: |
|
f32x4.mul |
0xe6 |
:+1: |
|
f32x4.div |
0xe7 |
:+1: |
|
f32x4.min |
0xe8 |
:+1: |
|
f32x4.max |
0xe9 |
:+1: |
|
f32x4.pmin |
0xea |
:question: |
|
f32x4.pmax |
0xeb |
:question: |
|
f64x2 Op |
Opcode |
Previous |
VCode Status |
f64x2.ceil |
0xdc |
:question: |
|
f64x2.floor |
0xdd |
:question: |
|
f64x2.trunc |
0xde |
:question: |
|
f64x2.nearest |
0xdf |
:question: |
|
f64x2.abs |
0xec |
:+1: |
|
f64x2.neg |
0xed |
:+1: |
|
---- round ---- |
0xee |
-- |
|
f64x2.sqrt |
0xef |
:+1: |
|
f64x2.add |
0xf0 |
:+1: |
|
f64x2.sub |
0xf1 |
:+1: |
|
f64x2.mul |
0xf2 |
:+1: |
|
f64x2.div |
0xf3 |
:+1: |
|
f64x2.min |
0xf4 |
:+1: |
|
f64x2.max |
0xf5 |
:+1: |
|
f64x2.pmin |
0xf6 |
:question: |
|
f64x2.pmax |
0xf7 |
:question: |
|
Conversion Op |
Opcode |
Previous |
VCode Status |
i32x4.trunc_sat_f32x4_s |
0xf8 |
:+1: |
@jlb6740 |
i32x4.trunc_sat_f32x4_u |
0xf9 |
:+1: |
@jlb6740 |
f32x4.convert_i32x4_s |
0xfa |
:+1: |
@jlb6740 |
f32x4.convert_i32x4_u |
0xfb |
:+1: |
@jlb6740 |
jlb6740 edited Issue #2272:
Status: Currently Not Valid (Initial Status WIP)
Last Update: 10/8/2020
https://gist.github.com/jlb6740/0a495404f6b3cc901e1b8e5ae8148020
Loads |
Opcode |
Old Backend Status |
VCode Status |
v128.load |
0x00 |
:+1: |
:+1: |
v128.load8x8_s |
0x01 |
:+1: |
-- |
v128.load8x8_u |
0x02 |
:+1: |
-- |
v128.load16x4_s |
0x03 |
:+1: |
-- |
v128.load16x4_u |
0x04 |
:+1: |
-- |
v128.load32x2_s |
0x05 |
:+1: |
-- |
v128.load32x2_u |
0x06 |
:+1: |
-- |
v128.load8_splat |
0x07 |
:+1: |
-- |
v128.load16_splat |
0x08 |
:+1: |
-- |
v128.load32_splat |
0x09 |
:+1: |
-- |
v128.load64_splat |
0x0a |
:+1: |
-- |
Stores |
Opcode |
Old Backend Status |
VCode Status |
v128.store |
0x0b |
:+1: |
:+1: |
Basic operation |
Opcode |
Old Backend Status |
VCode Status |
v128.const |
0x0c |
:+1: |
|
i8x16.shuffle |
0x0d |
:+1: |
|
i8x16.swizzle |
0x0e |
:+1: |
|
Splat operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.splat |
0x0f |
:+1:v |
|
i16x8.splat |
0x10 |
:+1: |
|
i32x4.splat |
0x11 |
:+1: |
|
i64x2.splat |
0x12 |
:+1: |
|
f32x4.splat |
0x13 |
:+1: |
|
f64x2.splat |
0x14 |
:+1: |
|
Lane operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.extract_lane_s |
0x15 |
:+1: |
|
i8x16.extract_lane_u |
0x16 |
:+1: |
|
i8x16.replace_lane |
0x17 |
:+1: |
|
i16x8.extract_lane_s |
0x18 |
:+1: |
|
i16x8.extract_lane_u |
0x19 |
:+1: |
|
i16x8.replace_lane |
0x1a |
:+1: |
|
i32x4.extract_lane |
0x1b |
:+1: |
|
i32x4.replace_lane |
0x1c |
:+1: |
|
i64x2.extract_lane |
0x1d |
:+1: |
|
i64x2.replace_lane |
0x1e |
:+1: |
|
f32x4.extract_lane |
0x1f |
:+1: |
|
f32x4.replace_lane |
0x20 |
:+1: |
|
f64x2.extract_lane |
0x21 |
:+1: |
|
f64x2.replace_lane |
0x22 |
:+1: |
|
Integer Cmp |
Opcode |
Old Backend Status |
VCode Status |
i8x16.eq |
0x23 |
:+1: |
|
i8x16.ne |
0x24 |
:+1: |
|
i8x16.lt_s |
0x25 |
:+1: |
|
i8x16.lt_u |
0x26 |
:+1: |
|
i8x16.gt_s |
0x27 |
:+1: |
|
i8x16.gt_u |
0x28 |
:+1: |
|
i8x16.le_s |
0x29 |
:+1: |
|
i8x16.le_u |
0x2a |
:+1: |
|
i8x16.ge_s |
0x2b |
:+1: |
|
i8x16.ge_u |
0x2c |
:+1: |
|
i16x8.eq |
0x2d |
:+1: |
|
i16x8.ne |
0x2e |
:+1: |
|
i16x8.lt_s |
0x2f |
:+1: |
|
i16x8.lt_u |
0x30 |
:+1: |
|
i16x8.gt_s |
0x31 |
:+1: |
|
i16x8.gt_u |
0x32 |
:+1: |
|
i16x8.le_s |
0x33 |
:+1: |
|
i16x8.le_u |
0x34 |
:+1: |
|
i16x8.ge_s |
0x35 |
:+1: |
|
i16x8.ge_u |
0x36 |
:+1: |
|
i32x4.eq |
0x37 |
:+1: |
|
i32x4.ne |
0x38 |
:+1: |
|
i32x4.lt_s |
0x39 |
:+1: |
|
i32x4.lt_u |
0x3a |
:+1: |
|
i32x4.gt_s |
0x3b |
:+1: |
|
i32x4.gt_u |
0x3c |
:+1: |
|
i32x4.le_s |
0x3d |
:+1: |
|
i32x4.le_u |
0x3e |
:+1: |
|
i32x4.ge_s |
0x3f |
:+1: |
|
i32x4.ge_u |
0x40 |
:+1: |
|
v128 Op |
Opcode |
Old Backend Status |
VCode Status |
v128.not |
0x4d |
:+1: |
|
v128.and |
0x4e |
:+1: |
|
v128.andnot |
0x4f |
:+1: |
|
v128.or |
0x50 |
:+1: |
|
v128.xor |
0x51 |
:+1: |
|
v128.bitselect |
0x52 |
:+1: |
|
i8x16 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i8x16.abs |
0x60 |
:+1: |
|
i8x16.neg |
0x61 |
:+1: |
|
i8x16.any_true |
0x62 |
:+1: |
|
i8x16.all_true |
0x63 |
:+1: |
|
i8x16.bitmask |
0x64 |
:question: |
|
i8x16.narrow_i16x8_s |
0x65 |
:+1: |
|
i8x16.narrow_i16x8_u |
0x66 |
:+1: |
|
---- widen ---- |
0x67 |
-- |
|
---- widen ---- |
0x68 |
-- |
|
---- widen ---- |
0x69 |
-- |
|
---- widen ---- |
0x6a |
-- |
|
i8x16.shl |
0x6b |
:+1: |
|
i8x16.shr_s |
0x6c |
:+1: |
|
i8x16.shr_u |
0x6d |
:+1: |
|
i8x16.add |
0x6e |
:+1: |
|
i8x16.add_sat_s |
0x6f |
:+1: |
|
i8x16.add_sat_u |
0x70 |
:+1: |
|
i8x16.sub |
0x71 |
:+1: |
|
i8x16.sub_sat_s |
0x72 |
:+1: |
|
i8x16.sub_sat_u |
0x73 |
:+1: |
|
---- dot ---- |
0x74 |
-- |
|
---- mul ---- |
0x75 |
:question: |
|
i8x16.min_s |
0x76 |
:+1: |
|
i8x16.min_u |
0x77 |
:+1: |
|
i8x16.max_s |
0x78 |
:+1: |
|
i8x16.max_u |
0x79 |
:+1: |
|
---- avgr_s ---- |
0x7a |
-- |
|
i8x16.avgr_u |
0x7b |
:+1: |
|
i16x8 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i16x8.abs |
0x80 |
:+1: |
|
i16x8.neg |
0x81 |
:+1: |
|
i16x8.any_true |
0x82 |
:+1: |
|
i16x8.all_true |
0x83 |
:+1: |
|
i16x8.bitmask |
0x84 |
:question: |
|
i16x8.narrow_i32x4_s |
0x85 |
:+1: |
|
i16x8.narrow_i32x4_u |
0x86 |
:+1: |
|
i16x8.widen_low_i8x16_s |
0x87 |
:+1: |
|
i16x8.widen_high_i8x16_s |
0x88 |
:+1: |
|
i16x8.widen_low_i8x16_u |
0x89 |
:+1: |
|
i16x8.widen_high_i8x16_u |
0x8a |
:+1: |
|
i16x8.shl |
0x8b |
:+1: |
|
i16x8.shr_s |
0x8c |
:+1: |
|
i16x8.shr_u |
0x8d |
:+1: |
|
i16x8.add |
0x8e |
:+1: |
|
i16x8.add_sat_s |
0x8f |
:+1: |
|
i16x8.add_sat_u |
0x90 |
:+1: |
|
i16x8.sub |
0x91 |
:+1: |
|
i16x8.sub_sat_s |
0x92 |
:+1: |
|
i16x8.sub_sat_u |
0x93 |
:+1: |
|
---- dot ---- |
0x94 |
-- |
|
i16x8.mul |
0x95 |
:+1: |
|
i16x8.min_s |
0x96 |
:+1: |
|
i16x8.min_u |
0x97 |
:+1: |
|
i16x8.max_s |
0x98 |
:+1: |
|
i16x8.max_u |
0x99 |
:+1: |
|
---- avgr_s ---- |
0x9a |
-- |
|
i16x8.avgr_u |
0x9b |
:+1: |
|
i32x4 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
-- |
-- |
-- |
|
i32x4.abs |
0xa0 |
:+1: |
|
i32x4.neg |
0xa1 |
:+1: |
|
i32x4.any_true |
0xa2 |
:+1: |
|
i32x4.all_true |
0xa3 |
:+1: |
|
i32x4.bitmask |
0xa4 |
:question: |
|
---- narrow ---- |
0xa5 |
-- |
|
---- narrow ---- |
0xa6 |
-- |
|
i32x4.widen_low_i16x8_s |
0xa7 |
:+1: |
|
i32x4.widen_high_i16x8_s |
0xa8 |
:+1: |
|
i32x4.widen_low_i16x8_u |
0xa9 |
:+1: |
|
i32x4.widen_high_i16x8_u |
0xaa |
:+1: |
|
i32x4.shl |
0xab |
:+1: |
|
i32x4.shr_s |
0xac |
:+1: |
|
i32x4.shr_u |
0xad |
:+1: |
|
i32x4.add |
0xae |
:+1: |
|
---- add_sat ---- |
0xaf |
-- |
|
---- add_sat ---- |
0xb0 |
-- |
|
i32x4.sub |
0xb1 |
:+1: |
|
---- sub_sat ---- |
0xb2 |
-- |
|
---- sub_sat ---- |
0xb3 |
-- |
|
---- dot ---- |
0xb4 |
-- |
|
i32x4.mul |
0xb5 |
:+1: |
|
i32x4.min_s |
0xb6 |
:+1: |
|
i32x4.min_u |
0xb7 |
:+1: |
|
i32x4.max_s |
0xb8 |
:+1: |
|
i32x4.max_u |
0xb9 |
:+1: |
|
---- avgr_s ---- |
0xba |
-- |
|
---- avgr_u ---- |
0xbb |
-- |
|
i64x2 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
---- |
0xc0 |
-- |
|
i64x2.neg |
0xc1 |
:+1: |
|
---- |
0xc2 |
-- |
|
---- |
0xc3 |
-- |
|
---- |
0xc4 |
-- |
|
---- |
0xc5 |
-- |
|
---- |
0xc6 |
-- |
|
---- |
0xc7 |
-- |
|
---- |
0xc8 |
-- |
|
---- |
0xc9 |
-- |
|
---- |
0xca |
-- |
|
i64x2.shl |
0xcb |
:+1: |
|
i64x2.shr_s |
0xcc |
:+1: |
|
i64x2.shr_u |
0xcd |
:+1: |
|
i64x2.add |
0xce |
:+1: |
|
---- |
0xcf |
-- |
|
---- |
0xd0 |
-- |
|
i64x2.sub |
0xd1 |
:+1: |
|
---- |
0xd2 |
-- |
|
---- |
0xd3 |
-- |
|
---- |
0xd4 |
-- |
|
i64x2.mul |
0xd5 |
:+1: |
|
---- |
0xd6 |
-- |
|
---- |
0xd7 |
-- |
|
f32x4 Op |
Opcode |
Old Backend Status |
VCode Status |
f32x4.ceil |
0xd8 |
:question: |
|
f32x4.floor |
0xd9 |
:question: |
|
f32x4.trunc |
0xda |
:question: |
|
f32x4.nearest |
0xdb |
:question: |
|
f32x4.abs |
0xe0 |
:+1: |
|
f32x4.neg |
0xe1 |
:+1: |
|
---- round ---- |
0xe2 |
-- |
|
f32x4.sqrt |
0xe3 |
:+1: |
|
f32x4.add |
0xe4 |
:+1: |
|
f32x4.sub |
0xe5 |
:+1: |
|
f32x4.mul |
0xe6 |
:+1: |
|
f32x4.div |
0xe7 |
:+1: |
|
f32x4.min |
0xe8 |
:+1: |
|
f32x4.max |
0xe9 |
:+1: |
|
f32x4.pmin |
0xea |
:question: |
|
f32x4.pmax |
0xeb |
:question: |
|
f64x2 Op |
Opcode |
Previous |
VCode Status |
f64x2.ceil |
0xdc |
:question: |
|
f64x2.floor |
0xdd |
:question: |
|
f64x2.trunc |
0xde |
:question: |
|
f64x2.nearest |
0xdf |
:question: |
|
f64x2.abs |
0xec |
:+1: |
|
f64x2.neg |
0xed |
:+1: |
|
---- round ---- |
0xee |
-- |
|
f64x2.sqrt |
0xef |
:+1: |
|
f64x2.add |
0xf0 |
:+1: |
|
f64x2.sub |
0xf1 |
:+1: |
|
f64x2.mul |
0xf2 |
:+1: |
|
f64x2.div |
0xf3 |
:+1: |
|
f64x2.min |
0xf4 |
:+1: |
|
f64x2.max |
0xf5 |
:+1: |
|
f64x2.pmin |
0xf6 |
:question: |
|
f64x2.pmax |
0xf7 |
:question: |
|
Conversion Op |
Opcode |
Previous |
VCode Status |
i32x4.trunc_sat_f32x4_s |
0xf8 |
:+1: |
@jlb6740 |
i32x4.trunc_sat_f32x4_u |
0xf9 |
:+1: |
@jlb6740 |
f32x4.convert_i32x4_s |
0xfa |
:+1: |
@jlb6740 |
f32x4.convert_i32x4_u |
0xfb |
:+1: |
@jlb6740 |
jlb6740 edited Issue #2272:
Status: Currently Not Valid (Initial Status WIP)
Last Update: 10/12/2020
https://gist.github.com/jlb6740/0a495404f6b3cc901e1b8e5ae8148020
Loads |
Opcode |
Old Backend Status |
VCode Status |
v128.load |
0x00 |
:+1: |
:+1: |
v128.load8x8_s |
0x01 |
:+1: |
-- |
v128.load8x8_u |
0x02 |
:+1: |
-- |
v128.load16x4_s |
0x03 |
:+1: |
-- |
v128.load16x4_u |
0x04 |
:+1: |
-- |
v128.load32x2_s |
0x05 |
:+1: |
-- |
v128.load32x2_u |
0x06 |
:+1: |
-- |
v128.load8_splat |
0x07 |
:+1: |
-- |
v128.load16_splat |
0x08 |
:+1: |
-- |
v128.load32_splat |
0x09 |
:+1: |
-- |
v128.load64_splat |
0x0a |
:+1: |
-- |
Stores |
Opcode |
Old Backend Status |
VCode Status |
v128.store |
0x0b |
:+1: |
:+1: |
Basic operation |
Opcode |
Old Backend Status |
VCode Status |
v128.const |
0x0c |
:+1: |
|
i8x16.shuffle |
0x0d |
:+1: |
|
i8x16.swizzle |
0x0e |
:+1: |
|
Splat operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.splat |
0x0f |
:+1:v |
|
i16x8.splat |
0x10 |
:+1: |
|
i32x4.splat |
0x11 |
:+1: |
|
i64x2.splat |
0x12 |
:+1: |
|
f32x4.splat |
0x13 |
:+1: |
|
f64x2.splat |
0x14 |
:+1: |
|
Lane operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.extract_lane_s |
0x15 |
:+1: |
|
i8x16.extract_lane_u |
0x16 |
:+1: |
|
i8x16.replace_lane |
0x17 |
:+1: |
|
i16x8.extract_lane_s |
0x18 |
:+1: |
|
i16x8.extract_lane_u |
0x19 |
:+1: |
|
i16x8.replace_lane |
0x1a |
:+1: |
|
i32x4.extract_lane |
0x1b |
:+1: |
|
i32x4.replace_lane |
0x1c |
:+1: |
|
i64x2.extract_lane |
0x1d |
:+1: |
|
i64x2.replace_lane |
0x1e |
:+1: |
|
f32x4.extract_lane |
0x1f |
:+1: |
|
f32x4.replace_lane |
0x20 |
:+1: |
|
f64x2.extract_lane |
0x21 |
:+1: |
|
f64x2.replace_lane |
0x22 |
:+1: |
|
Integer Cmp |
Opcode |
Old Backend Status |
VCode Status |
i8x16.eq |
0x23 |
:+1: |
|
i8x16.ne |
0x24 |
:+1: |
|
i8x16.lt_s |
0x25 |
:+1: |
|
i8x16.lt_u |
0x26 |
:+1: |
|
i8x16.gt_s |
0x27 |
:+1: |
|
i8x16.gt_u |
0x28 |
:+1: |
|
i8x16.le_s |
0x29 |
:+1: |
|
i8x16.le_u |
0x2a |
:+1: |
|
i8x16.ge_s |
0x2b |
:+1: |
|
i8x16.ge_u |
0x2c |
:+1: |
|
i16x8.eq |
0x2d |
:+1: |
|
i16x8.ne |
0x2e |
:+1: |
|
i16x8.lt_s |
0x2f |
:+1: |
|
i16x8.lt_u |
0x30 |
:+1: |
|
i16x8.gt_s |
0x31 |
:+1: |
|
i16x8.gt_u |
0x32 |
:+1: |
|
i16x8.le_s |
0x33 |
:+1: |
|
i16x8.le_u |
0x34 |
:+1: |
|
i16x8.ge_s |
0x35 |
:+1: |
|
i16x8.ge_u |
0x36 |
:+1: |
|
i32x4.eq |
0x37 |
:+1: |
|
i32x4.ne |
0x38 |
:+1: |
|
i32x4.lt_s |
0x39 |
:+1: |
|
i32x4.lt_u |
0x3a |
:+1: |
|
i32x4.gt_s |
0x3b |
:+1: |
|
i32x4.gt_u |
0x3c |
:+1: |
|
i32x4.le_s |
0x3d |
:+1: |
|
i32x4.le_u |
0x3e |
:+1: |
|
i32x4.ge_s |
0x3f |
:+1: |
|
i32x4.ge_u |
0x40 |
:+1: |
|
v128 Op |
Opcode |
Old Backend Status |
VCode Status |
v128.not |
0x4d |
:+1: |
|
v128.and |
0x4e |
:+1: |
|
v128.andnot |
0x4f |
:+1: |
|
v128.or |
0x50 |
:+1: |
|
v128.xor |
0x51 |
:+1: |
|
v128.bitselect |
0x52 |
:+1: |
|
i8x16 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i8x16.abs |
0x60 |
:+1: |
|
i8x16.neg |
0x61 |
:+1: |
|
i8x16.any_true |
0x62 |
:+1: |
|
i8x16.all_true |
0x63 |
:+1: |
|
i8x16.bitmask |
0x64 |
:question: |
|
i8x16.narrow_i16x8_s |
0x65 |
:+1: |
|
i8x16.narrow_i16x8_u |
0x66 |
:+1: |
|
---- widen ---- |
0x67 |
-- |
|
---- widen ---- |
0x68 |
-- |
|
---- widen ---- |
0x69 |
-- |
|
---- widen ---- |
0x6a |
-- |
|
i8x16.shl |
0x6b |
:+1: |
|
i8x16.shr_s |
0x6c |
:+1: |
|
i8x16.shr_u |
0x6d |
:+1: |
|
i8x16.add |
0x6e |
:+1: |
|
i8x16.add_sat_s |
0x6f |
:+1: |
|
i8x16.add_sat_u |
0x70 |
:+1: |
|
i8x16.sub |
0x71 |
:+1: |
|
i8x16.sub_sat_s |
0x72 |
:+1: |
|
i8x16.sub_sat_u |
0x73 |
:+1: |
|
---- dot ---- |
0x74 |
-- |
|
---- mul ---- |
0x75 |
:question: |
|
i8x16.min_s |
0x76 |
:+1: |
|
i8x16.min_u |
0x77 |
:+1: |
|
i8x16.max_s |
0x78 |
:+1: |
|
i8x16.max_u |
0x79 |
:+1: |
|
---- avgr_s ---- |
0x7a |
-- |
|
i8x16.avgr_u |
0x7b |
:+1: |
|
i16x8 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i16x8.abs |
0x80 |
:+1: |
|
i16x8.neg |
0x81 |
:+1: |
|
i16x8.any_true |
0x82 |
:+1: |
|
i16x8.all_true |
0x83 |
:+1: |
|
i16x8.bitmask |
0x84 |
:question: |
|
i16x8.narrow_i32x4_s |
0x85 |
:+1: |
|
i16x8.narrow_i32x4_u |
0x86 |
:+1: |
|
i16x8.widen_low_i8x16_s |
0x87 |
:+1: |
|
i16x8.widen_high_i8x16_s |
0x88 |
:+1: |
|
i16x8.widen_low_i8x16_u |
0x89 |
:+1: |
|
i16x8.widen_high_i8x16_u |
0x8a |
:+1: |
|
i16x8.shl |
0x8b |
:+1: |
|
i16x8.shr_s |
0x8c |
:+1: |
|
i16x8.shr_u |
0x8d |
:+1: |
|
i16x8.add |
0x8e |
:+1: |
|
i16x8.add_sat_s |
0x8f |
:+1: |
|
i16x8.add_sat_u |
0x90 |
:+1: |
|
i16x8.sub |
0x91 |
:+1: |
|
i16x8.sub_sat_s |
0x92 |
:+1: |
|
i16x8.sub_sat_u |
0x93 |
:+1: |
|
---- dot ---- |
0x94 |
-- |
|
i16x8.mul |
0x95 |
:+1: |
|
i16x8.min_s |
0x96 |
:+1: |
|
i16x8.min_u |
0x97 |
:+1: |
|
i16x8.max_s |
0x98 |
:+1: |
|
i16x8.max_u |
0x99 |
:+1: |
|
---- avgr_s ---- |
0x9a |
-- |
|
i16x8.avgr_u |
0x9b |
:+1: |
|
i32x4 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
-- |
-- |
-- |
|
i32x4.abs |
0xa0 |
:+1: |
|
i32x4.neg |
0xa1 |
:+1: |
|
i32x4.any_true |
0xa2 |
:+1: |
|
i32x4.all_true |
0xa3 |
:+1: |
|
i32x4.bitmask |
0xa4 |
:question: |
|
---- narrow ---- |
0xa5 |
-- |
|
---- narrow ---- |
0xa6 |
-- |
|
i32x4.widen_low_i16x8_s |
0xa7 |
:+1: |
|
i32x4.widen_high_i16x8_s |
0xa8 |
:+1: |
|
i32x4.widen_low_i16x8_u |
0xa9 |
:+1: |
|
i32x4.widen_high_i16x8_u |
0xaa |
:+1: |
|
i32x4.shl |
0xab |
:+1: |
|
i32x4.shr_s |
0xac |
:+1: |
|
i32x4.shr_u |
0xad |
:+1: |
|
i32x4.add |
0xae |
:+1: |
|
---- add_sat ---- |
0xaf |
-- |
|
---- add_sat ---- |
0xb0 |
-- |
|
i32x4.sub |
0xb1 |
:+1: |
|
---- sub_sat ---- |
0xb2 |
-- |
|
---- sub_sat ---- |
0xb3 |
-- |
|
---- dot ---- |
0xb4 |
-- |
|
i32x4.mul |
0xb5 |
:+1: |
|
i32x4.min_s |
0xb6 |
:+1: |
|
i32x4.min_u |
0xb7 |
:+1: |
|
i32x4.max_s |
0xb8 |
:+1: |
|
i32x4.max_u |
0xb9 |
:+1: |
|
---- avgr_s ---- |
0xba |
-- |
|
---- avgr_u ---- |
0xbb |
-- |
|
i64x2 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
---- |
0xc0 |
-- |
|
i64x2.neg |
0xc1 |
:+1: |
|
---- |
0xc2 |
-- |
|
---- |
0xc3 |
-- |
|
---- |
0xc4 |
-- |
|
---- |
0xc5 |
-- |
|
---- |
0xc6 |
-- |
|
---- |
0xc7 |
-- |
|
---- |
0xc8 |
-- |
|
---- |
0xc9 |
-- |
|
---- |
0xca |
-- |
|
i64x2.shl |
0xcb |
:+1: |
|
i64x2.shr_s |
0xcc |
:+1: |
|
i64x2.shr_u |
0xcd |
:+1: |
|
i64x2.add |
0xce |
:+1: |
|
---- |
0xcf |
-- |
|
---- |
0xd0 |
-- |
|
i64x2.sub |
0xd1 |
:+1: |
|
---- |
0xd2 |
-- |
|
---- |
0xd3 |
-- |
|
---- |
0xd4 |
-- |
|
i64x2.mul |
0xd5 |
:+1: |
|
---- |
0xd6 |
-- |
|
---- |
0xd7 |
-- |
|
f32x4 Op |
Opcode |
Old Backend Status |
VCode Status |
f32x4.ceil |
0xd8 |
:question: |
|
f32x4.floor |
0xd9 |
:question: |
|
f32x4.trunc |
0xda |
:question: |
|
f32x4.nearest |
0xdb |
:question: |
|
f32x4.abs |
0xe0 |
:+1: |
|
f32x4.neg |
0xe1 |
:+1: |
|
---- round ---- |
0xe2 |
-- |
|
f32x4.sqrt |
0xe3 |
:+1: |
|
f32x4.add |
0xe4 |
:+1: |
|
f32x4.sub |
0xe5 |
:+1: |
|
f32x4.mul |
0xe6 |
:+1: |
|
f32x4.div |
0xe7 |
:+1: |
|
f32x4.min |
0xe8 |
:+1: |
|
f32x4.max |
0xe9 |
:+1: |
|
f32x4.pmin |
0xea |
:question: |
|
f32x4.pmax |
0xeb |
:question: |
|
f64x2 Op |
Opcode |
Previous |
VCode Status |
f64x2.ceil |
0xdc |
:question: |
|
f64x2.floor |
0xdd |
:question: |
|
f64x2.trunc |
0xde |
:question: |
|
f64x2.nearest |
0xdf |
:question: |
|
f64x2.abs |
0xec |
:+1: |
|
f64x2.neg |
0xed |
:+1: |
|
---- round ---- |
0xee |
-- |
|
f64x2.sqrt |
0xef |
:+1: |
|
f64x2.add |
0xf0 |
:+1: |
|
f64x2.sub |
0xf1 |
:+1: |
|
f64x2.mul |
0xf2 |
:+1: |
|
f64x2.div |
0xf3 |
:+1: |
|
f64x2.min |
0xf4 |
:+1: |
|
f64x2.max |
0xf5 |
:+1: |
|
f64x2.pmin |
0xf6 |
:question: |
|
f64x2.pmax |
0xf7 |
:question: |
|
Conversion Op |
Opcode |
Previous |
VCode Status |
i32x4.trunc_sat_f32x4_s |
0xf8 |
:+1: |
@jlb6740 |
i32x4.trunc_sat_f32x4_u |
0xf9 |
:+1: |
@jlb6740 |
f32x4.convert_i32x4_s |
0xfa |
:+1: |
@jlb6740 |
f32x4.convert_i32x4_u |
0xfb |
:+1: |
@jlb6740 |
abrown edited Issue #2272:
Status: Currently Not Valid (Initial Status WIP)
Last Update: 10/12/2020
https://gist.github.com/jlb6740/0a495404f6b3cc901e1b8e5ae8148020
Loads |
Opcode |
Old Backend Status |
VCode Status |
v128.load |
0x00 |
:+1: |
:+1: |
v128.load8x8_s |
0x01 |
:+1: |
-- |
v128.load8x8_u |
0x02 |
:+1: |
-- |
v128.load16x4_s |
0x03 |
:+1: |
-- |
v128.load16x4_u |
0x04 |
:+1: |
-- |
v128.load32x2_s |
0x05 |
:+1: |
-- |
v128.load32x2_u |
0x06 |
:+1: |
-- |
v128.load8_splat |
0x07 |
:+1: |
-- |
v128.load16_splat |
0x08 |
:+1: |
-- |
v128.load32_splat |
0x09 |
:+1: |
-- |
v128.load64_splat |
0x0a |
:+1: |
-- |
Stores |
Opcode |
Old Backend Status |
VCode Status |
v128.store |
0x0b |
:+1: |
:+1: |
Basic operation |
Opcode |
Old Backend Status |
VCode Status |
v128.const |
0x0c |
:+1: |
:+1: |
i8x16.shuffle |
0x0d |
:+1: |
:+1: |
i8x16.swizzle |
0x0e |
:+1: |
:+1: |
Splat operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.splat |
0x0f |
:+1: |
:+1: |
i16x8.splat |
0x10 |
:+1: |
:+1: |
i32x4.splat |
0x11 |
:+1: |
:+1: |
i64x2.splat |
0x12 |
:+1: |
:+1: |
f32x4.splat |
0x13 |
:+1: |
:+1: |
f64x2.splat |
0x14 |
:+1: |
:+1: |
Lane operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.extract_lane_s |
0x15 |
:+1: |
:+1: |
i8x16.extract_lane_u |
0x16 |
:+1: |
:+1: |
i8x16.replace_lane |
0x17 |
:+1: |
:+1: |
i16x8.extract_lane_s |
0x18 |
:+1: |
:+1: |
i16x8.extract_lane_u |
0x19 |
:+1: |
:+1: |
i16x8.replace_lane |
0x1a |
:+1: |
:+1: |
i32x4.extract_lane |
0x1b |
:+1: |
:+1: |
i32x4.replace_lane |
0x1c |
:+1: |
:+1: |
i64x2.extract_lane |
0x1d |
:+1: |
:+1: |
i64x2.replace_lane |
0x1e |
:+1: |
:+1: |
f32x4.extract_lane |
0x1f |
:+1: |
:+1: |
f32x4.replace_lane |
0x20 |
:+1: |
:+1: |
f64x2.extract_lane |
0x21 |
:+1: |
:+1: |
f64x2.replace_lane |
0x22 |
:+1: |
:+1: |
Integer Cmp |
Opcode |
Old Backend Status |
VCode Status |
i8x16.eq |
0x23 |
:+1: |
:+1: |
i8x16.ne |
0x24 |
:+1: |
:+1: |
i8x16.lt_s |
0x25 |
:+1: |
:+1: |
i8x16.lt_u |
0x26 |
:+1: |
:+1: |
i8x16.gt_s |
0x27 |
:+1: |
:+1: |
i8x16.gt_u |
0x28 |
:+1: |
:+1: |
i8x16.le_s |
0x29 |
:+1: |
:+1: |
i8x16.le_u |
0x2a |
:+1: |
:+1: |
i8x16.ge_s |
0x2b |
:+1: |
:+1: |
i8x16.ge_u |
0x2c |
:+1: |
:+1: |
i16x8.eq |
0x2d |
:+1: |
:+1: |
i16x8.ne |
0x2e |
:+1: |
:+1: |
i16x8.lt_s |
0x2f |
:+1: |
:+1: |
i16x8.lt_u |
0x30 |
:+1: |
:+1: |
i16x8.gt_s |
0x31 |
:+1: |
:+1: |
i16x8.gt_u |
0x32 |
:+1: |
:+1: |
i16x8.le_s |
0x33 |
:+1: |
:+1: |
i16x8.le_u |
0x34 |
:+1: |
:+1: |
i16x8.ge_s |
0x35 |
:+1: |
:+1: |
i16x8.ge_u |
0x36 |
:+1: |
:+1: |
i32x4.eq |
0x37 |
:+1: |
:+1: |
i32x4.ne |
0x38 |
:+1: |
:+1: |
i32x4.lt_s |
0x39 |
:+1: |
:+1: |
i32x4.lt_u |
0x3a |
:+1: |
:+1: |
i32x4.gt_s |
0x3b |
:+1: |
:+1: |
i32x4.gt_u |
0x3c |
:+1: |
:+1: |
i32x4.le_s |
0x3d |
:+1: |
:+1: |
i32x4.le_u |
0x3e |
:+1: |
:+1: |
i32x4.ge_s |
0x3f |
:+1: |
:+1: |
i32x4.ge_u |
0x40 |
:+1: |
:+1: |
Float Cmp |
Opcode |
Old Backend Status |
VCode Status |
f32x4.eq |
0x41 |
:+1: |
:+1: |
f32x4.ne |
0x42 |
:+1: |
:+1: |
f32x4.lt |
0x43 |
:+1: |
:+1: |
f32x4.gt |
0x44 |
:+1: |
:+1: |
f32x4.le |
0x45 |
:+1: |
:+1: |
f32x4.ge |
0x46 |
:+1: |
:+1: |
f64x2.eq |
0x47 |
:+1: |
:+1: |
f64x2.ne |
0x48 |
:+1: |
:+1: |
f64x2.lt |
0x49 |
:+1: |
:+1: |
f64x2.gt |
0x4a |
:+1: |
:+1: |
f64x2.le |
0x4b |
:+1: |
:+1: |
f64x2.ge |
0x4c |
:+1: |
:+1: |
v128 Op |
Opcode |
Old Backend Status |
VCode Status |
v128.not |
0x4d |
:+1: |
:+1: |
v128.and |
0x4e |
:+1: |
:+1: |
v128.andnot |
0x4f |
:+1: |
:+1: |
v128.or |
0x50 |
:+1: |
:+1: |
v128.xor |
0x51 |
:+1: |
:+1: |
v128.bitselect |
0x52 |
:+1: |
:+1: |
i8x16 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i8x16.abs |
0x60 |
:+1: |
|
i8x16.neg |
0x61 |
:+1: |
|
i8x16.any_true |
0x62 |
:+1: |
:+1: |
i8x16.all_true |
0x63 |
:+1: |
:+1: |
i8x16.bitmask |
0x64 |
:question: |
|
i8x16.narrow_i16x8_s |
0x65 |
:+1: |
|
i8x16.narrow_i16x8_u |
0x66 |
:+1: |
|
---- widen ---- |
0x67 |
-- |
|
---- widen ---- |
0x68 |
-- |
|
---- widen ---- |
0x69 |
-- |
|
---- widen ---- |
0x6a |
-- |
|
i8x16.shl |
0x6b |
:+1: |
|
i8x16.shr_s |
0x6c |
:+1: |
|
i8x16.shr_u |
0x6d |
:+1: |
|
i8x16.add |
0x6e |
:+1: |
:+1: |
i8x16.add_sat_s |
0x6f |
:+1: |
:+1: |
i8x16.add_sat_u |
0x70 |
:+1: |
:+1: |
i8x16.sub |
0x71 |
:+1: |
:+1: |
i8x16.sub_sat_s |
0x72 |
:+1: |
:+1: |
i8x16.sub_sat_u |
0x73 |
:+1: |
:+1: |
---- dot ---- |
0x74 |
-- |
|
---- mul ---- |
0x75 |
:question: |
|
i8x16.min_s |
0x76 |
:+1: |
:+1: |
i8x16.min_u |
0x77 |
:+1: |
:+1: |
i8x16.max_s |
0x78 |
:+1: |
:+1: |
i8x16.max_u |
0x79 |
:+1: |
:+1: |
---- avgr_s ---- |
0x7a |
-- |
|
i8x16.avgr_u |
0x7b |
:+1: |
:+1: |
i16x8 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i16x8.abs |
0x80 |
:+1: |
|
i16x8.neg |
0x81 |
:+1: |
|
i16x8.any_true |
0x82 |
:+1: |
|
i16x8.all_true |
0x83 |
:+1: |
|
i16x8.bitmask |
0x84 |
:question: |
|
i16x8.narrow_i32x4_s |
0x85 |
:+1: |
|
i16x8.narrow_i32x4_u |
0x86 |
:+1: |
|
i16x8.widen_low_i8x16_s |
0x87 |
:+1: |
|
i16x8.widen_high_i8x16_s |
0x88 |
:+1: |
|
i16x8.widen_low_i8x16_u |
0x89 |
:+1: |
|
i16x8.widen_high_i8x16_u |
0x8a |
:+1: |
|
i16x8.shl |
0x8b |
:+1: |
|
i16x8.shr_s |
0x8c |
:+1: |
|
i16x8.shr_u |
0x8d |
:+1: |
|
i16x8.add |
0x8e |
:+1: |
|
i16x8.add_sat_s |
0x8f |
:+1: |
|
i16x8.add_sat_u |
0x90 |
:+1: |
|
i16x8.sub |
0x91 |
:+1: |
|
i16x8.sub_sat_s |
0x92 |
:+1: |
|
i16x8.sub_sat_u |
0x93 |
:+1: |
|
---- dot ---- |
0x94 |
-- |
|
i16x8.mul |
0x95 |
:+1: |
|
i16x8.min_s |
0x96 |
:+1: |
|
i16x8.min_u |
0x97 |
:+1: |
|
i16x8.max_s |
0x98 |
:+1: |
|
i16x8.max_u |
0x99 |
:+1: |
|
---- avgr_s ---- |
0x9a |
-- |
|
i16x8.avgr_u |
0x9b |
:+1: |
|
i32x4 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
-- |
-- |
-- |
|
i32x4.abs |
0xa0 |
:+1: |
|
i32x4.neg |
0xa1 |
:+1: |
|
i32x4.any_true |
0xa2 |
:+1: |
|
i32x4.all_true |
0xa3 |
:+1: |
|
i32x4.bitmask |
0xa4 |
:question: |
|
---- narrow ---- |
0xa5 |
-- |
|
---- narrow ---- |
0xa6 |
-- |
|
i32x4.widen_low_i16x8_s |
0xa7 |
:+1: |
|
i32x4.widen_high_i16x8_s |
0xa8 |
:+1: |
|
i32x4.widen_low_i16x8_u |
0xa9 |
:+1: |
|
i32x4.widen_high_i16x8_u |
0xaa |
:+1: |
|
i32x4.shl |
0xab |
:+1: |
|
i32x4.shr_s |
0xac |
:+1: |
|
i32x4.shr_u |
0xad |
:+1: |
|
i32x4.add |
0xae |
:+1: |
|
---- add_sat ---- |
0xaf |
-- |
|
---- add_sat ---- |
0xb0 |
-- |
|
i32x4.sub |
0xb1 |
:+1: |
|
---- sub_sat ---- |
0xb2 |
-- |
|
---- sub_sat ---- |
0xb3 |
-- |
|
---- dot ---- |
0xb4 |
-- |
|
i32x4.mul |
0xb5 |
:+1: |
|
i32x4.min_s |
0xb6 |
:+1: |
|
i32x4.min_u |
0xb7 |
:+1: |
|
i32x4.max_s |
0xb8 |
:+1: |
|
i32x4.max_u |
0xb9 |
:+1: |
|
---- avgr_s ---- |
0xba |
-- |
|
---- avgr_u ---- |
0xbb |
-- |
|
i64x2 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
---- |
0xc0 |
-- |
|
i64x2.neg |
0xc1 |
:+1: |
|
---- |
0xc2 |
-- |
|
---- |
0xc3 |
-- |
|
---- |
0xc4 |
-- |
|
---- |
0xc5 |
-- |
|
---- |
0xc6 |
-- |
|
---- |
0xc7 |
-- |
|
---- |
0xc8 |
-- |
|
---- |
0xc9 |
-- |
|
---- |
0xca |
-- |
|
i64x2.shl |
0xcb |
:+1: |
|
i64x2.shr_s |
0xcc |
:+1: |
|
i64x2.shr_u |
0xcd |
:+1: |
|
i64x2.add |
0xce |
:+1: |
|
---- |
0xcf |
-- |
|
---- |
0xd0 |
-- |
|
i64x2.sub |
0xd1 |
:+1: |
|
---- |
0xd2 |
-- |
|
---- |
0xd3 |
-- |
|
---- |
0xd4 |
-- |
|
i64x2.mul |
0xd5 |
:+1: |
|
---- |
0xd6 |
-- |
|
---- |
0xd7 |
-- |
|
f32x4 Op |
Opcode |
Old Backend Status |
VCode Status |
f32x4.ceil |
0xd8 |
:question: |
|
f32x4.floor |
0xd9 |
:question: |
|
f32x4.trunc |
0xda |
:question: |
|
f32x4.nearest |
0xdb |
:question: |
|
f32x4.abs |
0xe0 |
:+1: |
|
f32x4.neg |
0xe1 |
:+1: |
|
---- round ---- |
0xe2 |
-- |
|
f32x4.sqrt |
0xe3 |
:+1: |
|
f32x4.add |
0xe4 |
:+1: |
|
f32x4.sub |
0xe5 |
:+1: |
|
f32x4.mul |
0xe6 |
:+1: |
|
f32x4.div |
0xe7 |
:+1: |
|
f32x4.min |
0xe8 |
:+1: |
|
f32x4.max |
0xe9 |
:+1: |
|
f32x4.pmin |
0xea |
:question: |
|
f32x4.pmax |
0xeb |
:question: |
|
f64x2 Op |
Opcode |
Previous |
VCode Status |
f64x2.ceil |
0xdc |
:question: |
|
f64x2.floor |
0xdd |
:question: |
|
f64x2.trunc |
0xde |
:question: |
|
f64x2.nearest |
0xdf |
:question: |
|
f64x2.abs |
0xec |
:+1: |
|
f64x2.neg |
0xed |
:+1: |
|
---- round ---- |
0xee |
-- |
|
f64x2.sqrt |
0xef |
:+1: |
|
f64x2.add |
0xf0 |
:+1: |
|
f64x2.sub |
0xf1 |
:+1: |
|
f64x2.mul |
0xf2 |
:+1: |
|
f64x2.div |
0xf3 |
:+1: |
|
f64x2.min |
0xf4 |
:+1: |
|
f64x2.max |
0xf5 |
:+1: |
|
f64x2.pmin |
0xf6 |
:question: |
|
f64x2.pmax |
0xf7 |
:question: |
|
Conversion Op |
Opcode |
Previous |
VCode Status |
i32x4.trunc_sat_f32x4_s |
0xf8 |
:+1: |
@jlb6740 |
i32x4.trunc_sat_f32x4_u |
0xf9 |
:+1: |
@jlb6740 |
f32x4.convert_i32x4_s |
0xfa |
:+1: |
@jlb6740 |
f32x4.convert_i32x4_u |
0xfb |
:+1: |
@jlb6740 |
abrown edited Issue #2272:
Status: Currently Not Valid (Initial Status WIP)
Last Update: 10/12/2020
https://gist.github.com/jlb6740/0a495404f6b3cc901e1b8e5ae8148020
Loads |
Opcode |
Old Backend Status |
VCode Status |
v128.load |
0x00 |
:+1: |
:+1: |
v128.load8x8_s |
0x01 |
:+1: |
-- |
v128.load8x8_u |
0x02 |
:+1: |
-- |
v128.load16x4_s |
0x03 |
:+1: |
-- |
v128.load16x4_u |
0x04 |
:+1: |
-- |
v128.load32x2_s |
0x05 |
:+1: |
-- |
v128.load32x2_u |
0x06 |
:+1: |
-- |
v128.load8_splat |
0x07 |
:+1: |
-- |
v128.load16_splat |
0x08 |
:+1: |
-- |
v128.load32_splat |
0x09 |
:+1: |
-- |
v128.load64_splat |
0x0a |
:+1: |
-- |
Stores |
Opcode |
Old Backend Status |
VCode Status |
v128.store |
0x0b |
:+1: |
:+1: |
Basic operation |
Opcode |
Old Backend Status |
VCode Status |
v128.const |
0x0c |
:+1: |
:+1: |
i8x16.shuffle |
0x0d |
:+1: |
:+1: |
i8x16.swizzle |
0x0e |
:+1: |
:+1: |
Splat operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.splat |
0x0f |
:+1: |
:+1: |
i16x8.splat |
0x10 |
:+1: |
:+1: |
i32x4.splat |
0x11 |
:+1: |
:+1: |
i64x2.splat |
0x12 |
:+1: |
:+1: |
f32x4.splat |
0x13 |
:+1: |
:+1: |
f64x2.splat |
0x14 |
:+1: |
:+1: |
Lane operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.extract_lane_s |
0x15 |
:+1: |
:+1: |
i8x16.extract_lane_u |
0x16 |
:+1: |
:+1: |
i8x16.replace_lane |
0x17 |
:+1: |
:+1: |
i16x8.extract_lane_s |
0x18 |
:+1: |
:+1: |
i16x8.extract_lane_u |
0x19 |
:+1: |
:+1: |
i16x8.replace_lane |
0x1a |
:+1: |
:+1: |
i32x4.extract_lane |
0x1b |
:+1: |
:+1: |
i32x4.replace_lane |
0x1c |
:+1: |
:+1: |
i64x2.extract_lane |
0x1d |
:+1: |
:+1: |
i64x2.replace_lane |
0x1e |
:+1: |
:+1: |
f32x4.extract_lane |
0x1f |
:+1: |
:+1: |
f32x4.replace_lane |
0x20 |
:+1: |
:+1: |
f64x2.extract_lane |
0x21 |
:+1: |
:+1: |
f64x2.replace_lane |
0x22 |
:+1: |
:+1: |
Integer Cmp |
Opcode |
Old Backend Status |
VCode Status |
i8x16.eq |
0x23 |
:+1: |
:+1: |
i8x16.ne |
0x24 |
:+1: |
:+1: |
i8x16.lt_s |
0x25 |
:+1: |
:+1: |
i8x16.lt_u |
0x26 |
:+1: |
:+1: |
i8x16.gt_s |
0x27 |
:+1: |
:+1: |
i8x16.gt_u |
0x28 |
:+1: |
:+1: |
i8x16.le_s |
0x29 |
:+1: |
:+1: |
i8x16.le_u |
0x2a |
:+1: |
:+1: |
i8x16.ge_s |
0x2b |
:+1: |
:+1: |
i8x16.ge_u |
0x2c |
:+1: |
:+1: |
i16x8.eq |
0x2d |
:+1: |
:+1: |
i16x8.ne |
0x2e |
:+1: |
:+1: |
i16x8.lt_s |
0x2f |
:+1: |
:+1: |
i16x8.lt_u |
0x30 |
:+1: |
:+1: |
i16x8.gt_s |
0x31 |
:+1: |
:+1: |
i16x8.gt_u |
0x32 |
:+1: |
:+1: |
i16x8.le_s |
0x33 |
:+1: |
:+1: |
i16x8.le_u |
0x34 |
:+1: |
:+1: |
i16x8.ge_s |
0x35 |
:+1: |
:+1: |
i16x8.ge_u |
0x36 |
:+1: |
:+1: |
i32x4.eq |
0x37 |
:+1: |
:+1: |
i32x4.ne |
0x38 |
:+1: |
:+1: |
i32x4.lt_s |
0x39 |
:+1: |
:+1: |
i32x4.lt_u |
0x3a |
:+1: |
:+1: |
i32x4.gt_s |
0x3b |
:+1: |
:+1: |
i32x4.gt_u |
0x3c |
:+1: |
:+1: |
i32x4.le_s |
0x3d |
:+1: |
:+1: |
i32x4.le_u |
0x3e |
:+1: |
:+1: |
i32x4.ge_s |
0x3f |
:+1: |
:+1: |
i32x4.ge_u |
0x40 |
:+1: |
:+1: |
Float Cmp |
Opcode |
Old Backend Status |
VCode Status |
f32x4.eq |
0x41 |
:+1: |
:+1: |
f32x4.ne |
0x42 |
:+1: |
:+1: |
f32x4.lt |
0x43 |
:+1: |
:+1: |
f32x4.gt |
0x44 |
:+1: |
:+1: |
f32x4.le |
0x45 |
:+1: |
:+1: |
f32x4.ge |
0x46 |
:+1: |
:+1: |
f64x2.eq |
0x47 |
:+1: |
:+1: |
f64x2.ne |
0x48 |
:+1: |
:+1: |
f64x2.lt |
0x49 |
:+1: |
:+1: |
f64x2.gt |
0x4a |
:+1: |
:+1: |
f64x2.le |
0x4b |
:+1: |
:+1: |
f64x2.ge |
0x4c |
:+1: |
:+1: |
v128 Op |
Opcode |
Old Backend Status |
VCode Status |
v128.not |
0x4d |
:+1: |
:+1: |
v128.and |
0x4e |
:+1: |
:+1: |
v128.andnot |
0x4f |
:+1: |
:+1: |
v128.or |
0x50 |
:+1: |
:+1: |
v128.xor |
0x51 |
:+1: |
:+1: |
v128.bitselect |
0x52 |
:+1: |
:+1: |
i8x16 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i8x16.abs |
0x60 |
:+1: |
:+1: |
i8x16.neg |
0x61 |
:+1: |
:+1: |
i8x16.any_true |
0x62 |
:+1: |
:+1: |
i8x16.all_true |
0x63 |
:+1: |
:+1: |
i8x16.bitmask |
0x64 |
:question: |
|
i8x16.narrow_i16x8_s |
0x65 |
:+1: |
|
i8x16.narrow_i16x8_u |
0x66 |
:+1: |
|
---- widen ---- |
0x67 |
-- |
|
---- widen ---- |
0x68 |
-- |
|
---- widen ---- |
0x69 |
-- |
|
---- widen ---- |
0x6a |
-- |
|
i8x16.shl |
0x6b |
:+1: |
|
i8x16.shr_s |
0x6c |
:+1: |
|
i8x16.shr_u |
0x6d |
:+1: |
|
i8x16.add |
0x6e |
:+1: |
:+1: |
i8x16.add_sat_s |
0x6f |
:+1: |
:+1: |
i8x16.add_sat_u |
0x70 |
:+1: |
:+1: |
i8x16.sub |
0x71 |
:+1: |
:+1: |
i8x16.sub_sat_s |
0x72 |
:+1: |
:+1: |
i8x16.sub_sat_u |
0x73 |
:+1: |
:+1: |
---- dot ---- |
0x74 |
-- |
|
---- mul ---- |
0x75 |
:question: |
|
i8x16.min_s |
0x76 |
:+1: |
:+1: |
i8x16.min_u |
0x77 |
:+1: |
:+1: |
i8x16.max_s |
0x78 |
:+1: |
:+1: |
i8x16.max_u |
0x79 |
:+1: |
:+1: |
---- avgr_s ---- |
0x7a |
-- |
|
i8x16.avgr_u |
0x7b |
:+1: |
:+1: |
i16x8 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i16x8.abs |
0x80 |
:+1: |
:+1: |
i16x8.neg |
0x81 |
:+1: |
:+1: |
i16x8.any_true |
0x82 |
:+1: |
:+1: |
i16x8.all_true |
0x83 |
:+1: |
:+1: |
i16x8.bitmask |
0x84 |
:question: |
|
i16x8.narrow_i32x4_s |
0x85 |
:+1: |
|
i16x8.narrow_i32x4_u |
0x86 |
:+1: |
|
i16x8.widen_low_i8x16_s |
0x87 |
:+1: |
|
i16x8.widen_high_i8x16_s |
0x88 |
:+1: |
|
i16x8.widen_low_i8x16_u |
0x89 |
:+1: |
|
i16x8.widen_high_i8x16_u |
0x8a |
:+1: |
|
i16x8.shl |
0x8b |
:+1: |
|
i16x8.shr_s |
0x8c |
:+1: |
|
i16x8.shr_u |
0x8d |
:+1: |
|
i16x8.add |
0x8e |
:+1: |
:+1: |
i16x8.add_sat_s |
0x8f |
:+1: |
:+1: |
i16x8.add_sat_u |
0x90 |
:+1: |
:+1: |
i16x8.sub |
0x91 |
:+1: |
:+1: |
i16x8.sub_sat_s |
0x92 |
:+1: |
:+1: |
i16x8.sub_sat_u |
0x93 |
:+1: |
:+1: |
---- dot ---- |
0x94 |
-- |
|
i16x8.mul |
0x95 |
:+1: |
:+1: |
i16x8.min_s |
0x96 |
:+1: |
:+1: |
i16x8.min_u |
0x97 |
:+1: |
:+1: |
i16x8.max_s |
0x98 |
:+1: |
:+1: |
i16x8.max_u |
0x99 |
:+1: |
:+1: |
---- avgr_s ---- |
0x9a |
-- |
|
i16x8.avgr_u |
0x9b |
:+1: |
:+1: |
i32x4 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i32x4.abs |
0xa0 |
:+1: |
:+1: |
i32x4.neg |
0xa1 |
:+1: |
:+1: |
i32x4.any_true |
0xa2 |
:+1: |
:+1: |
i32x4.all_true |
0xa3 |
:+1: |
:+1: |
i32x4.bitmask |
0xa4 |
:question: |
|
---- narrow ---- |
0xa5 |
-- |
|
---- narrow ---- |
0xa6 |
-- |
|
i32x4.widen_low_i16x8_s |
0xa7 |
:+1: |
|
i32x4.widen_high_i16x8_s |
0xa8 |
:+1: |
|
i32x4.widen_low_i16x8_u |
0xa9 |
:+1: |
|
i32x4.widen_high_i16x8_u |
0xaa |
:+1: |
|
i32x4.shl |
0xab |
:+1: |
|
i32x4.shr_s |
0xac |
:+1: |
|
i32x4.shr_u |
0xad |
:+1: |
|
i32x4.add |
0xae |
:+1: |
:+1: |
---- add_sat ---- |
0xaf |
-- |
|
---- add_sat ---- |
0xb0 |
-- |
|
i32x4.sub |
0xb1 |
:+1: |
:+1: |
---- sub_sat ---- |
0xb2 |
-- |
|
---- sub_sat ---- |
0xb3 |
-- |
|
---- dot ---- |
0xb4 |
-- |
|
i32x4.mul |
0xb5 |
:+1: |
:+1: |
i32x4.min_s |
0xb6 |
:+1: |
:+1: |
i32x4.min_u |
0xb7 |
:+1: |
:+1: |
i32x4.max_s |
0xb8 |
:+1: |
:+1: |
i32x4.max_u |
0xb9 |
:+1: |
:+1: |
---- avgr_s ---- |
0xba |
-- |
|
---- avgr_u ---- |
0xbb |
-- |
|
i64x2 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
---- |
0xc0 |
-- |
|
i64x2.neg |
0xc1 |
:+1: |
|
---- |
0xc2 |
-- |
|
---- |
0xc3 |
-- |
|
---- |
0xc4 |
-- |
|
---- |
0xc5 |
-- |
|
---- |
0xc6 |
-- |
|
---- |
0xc7 |
-- |
|
---- |
0xc8 |
-- |
|
---- |
0xc9 |
-- |
|
---- |
0xca |
-- |
|
i64x2.shl |
0xcb |
:+1: |
|
i64x2.shr_s |
0xcc |
:+1: |
|
i64x2.shr_u |
0xcd |
:+1: |
|
i64x2.add |
0xce |
:+1: |
:+1: |
---- |
0xcf |
-- |
|
---- |
0xd0 |
-- |
|
i64x2.sub |
0xd1 |
:+1: |
:+1: |
---- |
0xd2 |
-- |
|
---- |
0xd3 |
-- |
|
---- |
0xd4 |
-- |
|
i64x2.mul |
0xd5 |
:+1: |
:+1: |
---- |
0xd6 |
-- |
|
---- |
0xd7 |
-- |
|
f32x4 Op |
Opcode |
Old Backend Status |
VCode Status |
f32x4.ceil |
0xd8 |
:question: |
|
f32x4.floor |
0xd9 |
:question: |
|
f32x4.trunc |
0xda |
:question: |
|
f32x4.nearest |
0xdb |
:question: |
|
f32x4.abs |
0xe0 |
:+1: |
:+1: |
f32x4.neg |
0xe1 |
:+1: |
:+1: |
---- round ---- |
0xe2 |
-- |
|
f32x4.sqrt |
0xe3 |
:+1: |
:+1: |
f32x4.add |
0xe4 |
:+1: |
:+1: |
f32x4.sub |
0xe5 |
:+1: |
:+1: |
f32x4.mul |
0xe6 |
:+1: |
:+1: |
f32x4.div |
0xe7 |
:+1: |
:+1: |
f32x4.min |
0xe8 |
:+1: |
:+1: |
f32x4.max |
0xe9 |
:+1: |
:+1: |
f32x4.pmin |
0xea |
:question: |
|
f32x4.pmax |
0xeb |
:question: |
|
f64x2 Op |
Opcode |
Previous |
VCode Status |
f64x2.ceil |
0xdc |
:question: |
|
f64x2.floor |
0xdd |
:question: |
|
f64x2.trunc |
0xde |
:question: |
|
f64x2.nearest |
0xdf |
:question: |
|
f64x2.abs |
0xec |
:+1: |
:+1: |
f64x2.neg |
0xed |
:+1: |
:+1: |
---- round ---- |
0xee |
-- |
|
f64x2.sqrt |
0xef |
:+1: |
:+1: |
f64x2.add |
0xf0 |
:+1: |
:+1: |
f64x2.sub |
0xf1 |
:+1: |
:+1: |
f64x2.mul |
0xf2 |
:+1: |
:+1: |
f64x2.div |
0xf3 |
:+1: |
:+1: |
f64x2.min |
0xf4 |
:+1: |
:+1: |
f64x2.max |
0xf5 |
:+1: |
:+1: |
f64x2.pmin |
0xf6 |
:question: |
|
f64x2.pmax |
0xf7 |
:question: |
|
Conversion Op |
Opcode |
Previous |
VCode Status |
i32x4.trunc_sat_f32x4_s |
0xf8 |
:+1: |
@jlb6740 |
i32x4.trunc_sat_f32x4_u |
0xf9 |
:+1: |
@jlb6740 |
f32x4.convert_i32x4_s |
0xfa |
:+1: |
@jlb6740 |
f32x4.convert_i32x4_u |
0xfb |
:+1: |
@jlb6740 |
abrown edited Issue #2272:
Status: Currently Not Valid (Initial Status WIP)
Last Update: 10/12/2020
https://gist.github.com/jlb6740/0a495404f6b3cc901e1b8e5ae8148020
Loads |
Opcode |
Old Backend Status |
VCode Status |
v128.load |
0x00 |
:+1: |
:+1: |
v128.load8x8_s |
0x01 |
:+1: |
-- |
v128.load8x8_u |
0x02 |
:+1: |
-- |
v128.load16x4_s |
0x03 |
:+1: |
-- |
v128.load16x4_u |
0x04 |
:+1: |
-- |
v128.load32x2_s |
0x05 |
:+1: |
-- |
v128.load32x2_u |
0x06 |
:+1: |
-- |
v128.load8_splat |
0x07 |
:+1: |
-- |
v128.load16_splat |
0x08 |
:+1: |
-- |
v128.load32_splat |
0x09 |
:+1: |
-- |
v128.load64_splat |
0x0a |
:+1: |
-- |
Stores |
Opcode |
Old Backend Status |
VCode Status |
v128.store |
0x0b |
:+1: |
:+1: |
Basic operation |
Opcode |
Old Backend Status |
VCode Status |
v128.const |
0x0c |
:+1: |
:+1: |
i8x16.shuffle |
0x0d |
:+1: |
:+1: |
i8x16.swizzle |
0x0e |
:+1: |
:+1: |
Splat operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.splat |
0x0f |
:+1: |
:+1: |
i16x8.splat |
0x10 |
:+1: |
:+1: |
i32x4.splat |
0x11 |
:+1: |
:+1: |
i64x2.splat |
0x12 |
:+1: |
:+1: |
f32x4.splat |
0x13 |
:+1: |
:+1: |
f64x2.splat |
0x14 |
:+1: |
:+1: |
Lane operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.extract_lane_s |
0x15 |
:+1: |
:+1: |
i8x16.extract_lane_u |
0x16 |
:+1: |
:+1: |
i8x16.replace_lane |
0x17 |
:+1: |
:+1: |
i16x8.extract_lane_s |
0x18 |
:+1: |
:+1: |
i16x8.extract_lane_u |
0x19 |
:+1: |
:+1: |
i16x8.replace_lane |
0x1a |
:+1: |
:+1: |
i32x4.extract_lane |
0x1b |
:+1: |
:+1: |
i32x4.replace_lane |
0x1c |
:+1: |
:+1: |
i64x2.extract_lane |
0x1d |
:+1: |
:+1: |
i64x2.replace_lane |
0x1e |
:+1: |
:+1: |
f32x4.extract_lane |
0x1f |
:+1: |
:+1: |
f32x4.replace_lane |
0x20 |
:+1: |
:+1: |
f64x2.extract_lane |
0x21 |
:+1: |
:+1: |
f64x2.replace_lane |
0x22 |
:+1: |
:+1: |
Integer Cmp |
Opcode |
Old Backend Status |
VCode Status |
i8x16.eq |
0x23 |
:+1: |
:+1: |
i8x16.ne |
0x24 |
:+1: |
:+1: |
i8x16.lt_s |
0x25 |
:+1: |
:+1: |
i8x16.lt_u |
0x26 |
:+1: |
:+1: |
i8x16.gt_s |
0x27 |
:+1: |
:+1: |
i8x16.gt_u |
0x28 |
:+1: |
:+1: |
i8x16.le_s |
0x29 |
:+1: |
:+1: |
i8x16.le_u |
0x2a |
:+1: |
:+1: |
i8x16.ge_s |
0x2b |
:+1: |
:+1: |
i8x16.ge_u |
0x2c |
:+1: |
:+1: |
i16x8.eq |
0x2d |
:+1: |
:+1: |
i16x8.ne |
0x2e |
:+1: |
:+1: |
i16x8.lt_s |
0x2f |
:+1: |
:+1: |
i16x8.lt_u |
0x30 |
:+1: |
:+1: |
i16x8.gt_s |
0x31 |
:+1: |
:+1: |
i16x8.gt_u |
0x32 |
:+1: |
:+1: |
i16x8.le_s |
0x33 |
:+1: |
:+1: |
i16x8.le_u |
0x34 |
:+1: |
:+1: |
i16x8.ge_s |
0x35 |
:+1: |
:+1: |
i16x8.ge_u |
0x36 |
:+1: |
:+1: |
i32x4.eq |
0x37 |
:+1: |
:+1: |
i32x4.ne |
0x38 |
:+1: |
:+1: |
i32x4.lt_s |
0x39 |
:+1: |
:+1: |
i32x4.lt_u |
0x3a |
:+1: |
:+1: |
i32x4.gt_s |
0x3b |
:+1: |
:+1: |
i32x4.gt_u |
0x3c |
:+1: |
:+1: |
i32x4.le_s |
0x3d |
:+1: |
:+1: |
i32x4.le_u |
0x3e |
:+1: |
:+1: |
i32x4.ge_s |
0x3f |
:+1: |
:+1: |
i32x4.ge_u |
0x40 |
:+1: |
:+1: |
Float Cmp |
Opcode |
Old Backend Status |
VCode Status |
f32x4.eq |
0x41 |
:+1: |
:+1: |
f32x4.ne |
0x42 |
:+1: |
:+1: |
f32x4.lt |
0x43 |
:+1: |
:+1: |
f32x4.gt |
0x44 |
:+1: |
:+1: |
f32x4.le |
0x45 |
:+1: |
:+1: |
f32x4.ge |
0x46 |
:+1: |
:+1: |
f64x2.eq |
0x47 |
:+1: |
:+1: |
f64x2.ne |
0x48 |
:+1: |
:+1: |
f64x2.lt |
0x49 |
:+1: |
:+1: |
f64x2.gt |
0x4a |
:+1: |
:+1: |
f64x2.le |
0x4b |
:+1: |
:+1: |
f64x2.ge |
0x4c |
:+1: |
:+1: |
v128 Op |
Opcode |
Old Backend Status |
VCode Status |
v128.not |
0x4d |
:+1: |
:+1: |
v128.and |
0x4e |
:+1: |
:+1: |
v128.andnot |
0x4f |
:+1: |
:+1: |
v128.or |
0x50 |
:+1: |
:+1: |
v128.xor |
0x51 |
:+1: |
:+1: |
v128.bitselect |
0x52 |
:+1: |
:+1: |
i8x16 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i8x16.abs |
0x60 |
:+1: |
:+1: |
i8x16.neg |
0x61 |
:+1: |
:+1: |
i8x16.any_true |
0x62 |
:+1: |
:+1: |
i8x16.all_true |
0x63 |
:+1: |
:+1: |
i8x16.bitmask |
0x64 |
:question: |
|
i8x16.narrow_i16x8_s |
0x65 |
:+1: |
|
i8x16.narrow_i16x8_u |
0x66 |
:+1: |
|
---- widen ---- |
0x67 |
-- |
|
---- widen ---- |
0x68 |
-- |
|
---- widen ---- |
0x69 |
-- |
|
---- widen ---- |
0x6a |
-- |
|
i8x16.shl |
0x6b |
:+1: |
|
i8x16.shr_s |
0x6c |
:+1: |
|
i8x16.shr_u |
0x6d |
:+1: |
|
i8x16.add |
0x6e |
:+1: |
:+1: |
i8x16.add_sat_s |
0x6f |
:+1: |
:+1: |
i8x16.add_sat_u |
0x70 |
:+1: |
:+1: |
i8x16.sub |
0x71 |
:+1: |
:+1: |
i8x16.sub_sat_s |
0x72 |
:+1: |
:+1: |
i8x16.sub_sat_u |
0x73 |
:+1: |
:+1: |
---- dot ---- |
0x74 |
-- |
|
---- mul ---- |
0x75 |
:question: |
|
i8x16.min_s |
0x76 |
:+1: |
:+1: |
i8x16.min_u |
0x77 |
:+1: |
:+1: |
i8x16.max_s |
0x78 |
:+1: |
:+1: |
i8x16.max_u |
0x79 |
:+1: |
:+1: |
---- avgr_s ---- |
0x7a |
-- |
|
i8x16.avgr_u |
0x7b |
:+1: |
:+1: |
i16x8 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i16x8.abs |
0x80 |
:+1: |
:+1: |
i16x8.neg |
0x81 |
:+1: |
:+1: |
i16x8.any_true |
0x82 |
:+1: |
:+1: |
i16x8.all_true |
0x83 |
:+1: |
:+1: |
i16x8.bitmask |
0x84 |
:question: |
|
i16x8.narrow_i32x4_s |
0x85 |
:+1: |
|
i16x8.narrow_i32x4_u |
0x86 |
:+1: |
|
i16x8.widen_low_i8x16_s |
0x87 |
:+1: |
|
i16x8.widen_high_i8x16_s |
0x88 |
:+1: |
|
i16x8.widen_low_i8x16_u |
0x89 |
:+1: |
|
i16x8.widen_high_i8x16_u |
0x8a |
:+1: |
|
i16x8.shl |
0x8b |
:+1: |
|
i16x8.shr_s |
0x8c |
:+1: |
|
i16x8.shr_u |
0x8d |
:+1: |
|
i16x8.add |
0x8e |
:+1: |
:+1: |
i16x8.add_sat_s |
0x8f |
:+1: |
:+1: |
i16x8.add_sat_u |
0x90 |
:+1: |
:+1: |
i16x8.sub |
0x91 |
:+1: |
:+1: |
i16x8.sub_sat_s |
0x92 |
:+1: |
:+1: |
i16x8.sub_sat_u |
0x93 |
:+1: |
:+1: |
---- dot ---- |
0x94 |
-- |
|
i16x8.mul |
0x95 |
:+1: |
:+1: |
i16x8.min_s |
0x96 |
:+1: |
:+1: |
i16x8.min_u |
0x97 |
:+1: |
:+1: |
i16x8.max_s |
0x98 |
:+1: |
:+1: |
i16x8.max_u |
0x99 |
:+1: |
:+1: |
---- avgr_s ---- |
0x9a |
-- |
|
i16x8.avgr_u |
0x9b |
:+1: |
:+1: |
i32x4 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i32x4.abs |
0xa0 |
:+1: |
:+1: |
i32x4.neg |
0xa1 |
:+1: |
:+1: |
i32x4.any_true |
0xa2 |
:+1: |
:+1: |
i32x4.all_true |
0xa3 |
:+1: |
:+1: |
i32x4.bitmask |
0xa4 |
:question: |
|
---- narrow ---- |
0xa5 |
-- |
|
---- narrow ---- |
0xa6 |
-- |
|
i32x4.widen_low_i16x8_s |
0xa7 |
:+1: |
|
i32x4.widen_high_i16x8_s |
0xa8 |
:+1: |
|
i32x4.widen_low_i16x8_u |
0xa9 |
:+1: |
|
i32x4.widen_high_i16x8_u |
0xaa |
:+1: |
|
i32x4.shl |
0xab |
:+1: |
|
i32x4.shr_s |
0xac |
:+1: |
|
i32x4.shr_u |
0xad |
:+1: |
|
i32x4.add |
0xae |
:+1: |
:+1: |
---- add_sat ---- |
0xaf |
-- |
|
---- add_sat ---- |
0xb0 |
-- |
|
i32x4.sub |
0xb1 |
:+1: |
:+1: |
---- sub_sat ---- |
0xb2 |
-- |
|
---- sub_sat ---- |
0xb3 |
-- |
|
---- dot ---- |
0xb4 |
-- |
|
i32x4.mul |
0xb5 |
:+1: |
:+1: |
i32x4.min_s |
0xb6 |
:+1: |
:+1: |
i32x4.min_u |
0xb7 |
:+1: |
:+1: |
i32x4.max_s |
0xb8 |
:+1: |
:+1: |
i32x4.max_u |
0xb9 |
:+1: |
:+1: |
---- avgr_s ---- |
0xba |
-- |
|
---- avgr_u ---- |
0xbb |
-- |
|
i64x2 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
---- |
0xc0 |
-- |
|
i64x2.neg |
0xc1 |
:+1: |
|
---- |
0xc2 |
-- |
|
---- |
0xc3 |
-- |
|
---- |
0xc4 |
-- |
|
---- |
0xc5 |
-- |
|
---- |
0xc6 |
-- |
|
---- |
0xc7 |
-- |
|
---- |
0xc8 |
-- |
|
---- |
0xc9 |
-- |
|
---- |
0xca |
-- |
|
i64x2.shl |
0xcb |
:+1: |
|
i64x2.shr_s |
0xcc |
:+1: |
|
i64x2.shr_u |
0xcd |
:+1: |
|
i64x2.add |
0xce |
:+1: |
:+1: |
---- |
0xcf |
-- |
|
---- |
0xd0 |
-- |
|
i64x2.sub |
0xd1 |
:+1: |
:+1: |
---- |
0xd2 |
-- |
|
---- |
0xd3 |
-- |
|
---- |
0xd4 |
-- |
|
i64x2.mul |
0xd5 |
:+1: |
:+1: |
---- |
0xd6 |
-- |
|
---- |
0xd7 |
-- |
|
f32x4 Op |
Opcode |
Old Backend Status |
VCode Status |
f32x4.ceil |
0xd8 |
:question: |
|
f32x4.floor |
0xd9 |
:question: |
|
f32x4.trunc |
0xda |
:question: |
|
f32x4.nearest |
0xdb |
:question: |
|
f32x4.abs |
0xe0 |
:+1: |
:+1: |
f32x4.neg |
0xe1 |
:+1: |
:+1: |
---- round ---- |
0xe2 |
-- |
|
f32x4.sqrt |
0xe3 |
:+1: |
:+1: |
f32x4.add |
0xe4 |
:+1: |
:+1: |
f32x4.sub |
0xe5 |
:+1: |
:+1: |
f32x4.mul |
0xe6 |
:+1: |
:+1: |
f32x4.div |
0xe7 |
:+1: |
:+1: |
f32x4.min |
0xe8 |
:+1: |
:+1: |
f32x4.max |
0xe9 |
:+1: |
:+1: |
f32x4.pmin |
0xea |
:question: |
|
f32x4.pmax |
0xeb |
:question: |
|
f64x2 Op |
Opcode |
Old Backend Status |
VCode Status |
f64x2.ceil |
0xdc |
:question: |
|
f64x2.floor |
0xdd |
:question: |
|
f64x2.trunc |
0xde |
:question: |
|
f64x2.nearest |
0xdf |
:question: |
|
f64x2.abs |
0xec |
:+1: |
:+1: |
f64x2.neg |
0xed |
:+1: |
:+1: |
---- round ---- |
0xee |
-- |
|
f64x2.sqrt |
0xef |
:+1: |
:+1: |
f64x2.add |
0xf0 |
:+1: |
:+1: |
f64x2.sub |
0xf1 |
:+1: |
:+1: |
f64x2.mul |
0xf2 |
:+1: |
:+1: |
f64x2.div |
0xf3 |
:+1: |
:+1: |
f64x2.min |
0xf4 |
:+1: |
:+1: |
f64x2.max |
0xf5 |
:+1: |
:+1: |
f64x2.pmin |
0xf6 |
:question: |
|
f64x2.pmax |
0xf7 |
:question: |
|
Conversion Op |
Opcode |
Old Backend Status |
VCode Status |
i32x4.trunc_sat_f32x4_s |
0xf8 |
:+1: |
@jlb6740 |
i32x4.trunc_sat_f32x4_u |
0xf9 |
:+1: |
@jlb6740 |
f32x4.convert_i32x4_s |
0xfa |
:+1: |
@jlb6740 |
f32x4.convert_i32x4_u |
0xfb |
:+1: |
@jlb6740 |
abrown edited Issue #2272:
Status: Currently Not Valid (Initial Status WIP)
Last Update: 10/12/2020
https://gist.github.com/jlb6740/0a495404f6b3cc901e1b8e5ae8148020
Loads |
Opcode |
Old Backend Status |
VCode Status |
v128.load |
0x00 |
:+1: |
:+1: |
v128.load8x8_s |
0x01 |
:+1: |
-- |
v128.load8x8_u |
0x02 |
:+1: |
-- |
v128.load16x4_s |
0x03 |
:+1: |
-- |
v128.load16x4_u |
0x04 |
:+1: |
-- |
v128.load32x2_s |
0x05 |
:+1: |
-- |
v128.load32x2_u |
0x06 |
:+1: |
-- |
v128.load8_splat |
0x07 |
:+1: |
-- |
v128.load16_splat |
0x08 |
:+1: |
-- |
v128.load32_splat |
0x09 |
:+1: |
-- |
v128.load64_splat |
0x0a |
:+1: |
-- |
Stores |
Opcode |
Old Backend Status |
VCode Status |
v128.store |
0x0b |
:+1: |
:+1: |
Basic operation |
Opcode |
Old Backend Status |
VCode Status |
v128.const |
0x0c |
:+1: |
:+1: |
i8x16.shuffle |
0x0d |
:+1: |
:+1: |
i8x16.swizzle |
0x0e |
:+1: |
:+1: |
Splat operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.splat |
0x0f |
:+1: |
:+1: |
i16x8.splat |
0x10 |
:+1: |
:+1: |
i32x4.splat |
0x11 |
:+1: |
:+1: |
i64x2.splat |
0x12 |
:+1: |
:+1: |
f32x4.splat |
0x13 |
:+1: |
:+1: |
f64x2.splat |
0x14 |
:+1: |
:+1: |
Lane operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.extract_lane_s |
0x15 |
:+1: |
:+1: |
i8x16.extract_lane_u |
0x16 |
:+1: |
:+1: |
i8x16.replace_lane |
0x17 |
:+1: |
:+1: |
i16x8.extract_lane_s |
0x18 |
:+1: |
:+1: |
i16x8.extract_lane_u |
0x19 |
:+1: |
:+1: |
i16x8.replace_lane |
0x1a |
:+1: |
:+1: |
i32x4.extract_lane |
0x1b |
:+1: |
:+1: |
i32x4.replace_lane |
0x1c |
:+1: |
:+1: |
i64x2.extract_lane |
0x1d |
:+1: |
:+1: |
i64x2.replace_lane |
0x1e |
:+1: |
:+1: |
f32x4.extract_lane |
0x1f |
:+1: |
:+1: |
f32x4.replace_lane |
0x20 |
:+1: |
:+1: |
f64x2.extract_lane |
0x21 |
:+1: |
:+1: |
f64x2.replace_lane |
0x22 |
:+1: |
:+1: |
Integer Cmp |
Opcode |
Old Backend Status |
VCode Status |
i8x16.eq |
0x23 |
:+1: |
:+1: |
i8x16.ne |
0x24 |
:+1: |
:+1: |
i8x16.lt_s |
0x25 |
:+1: |
:+1: |
i8x16.lt_u |
0x26 |
:+1: |
:+1: |
i8x16.gt_s |
0x27 |
:+1: |
:+1: |
i8x16.gt_u |
0x28 |
:+1: |
:+1: |
i8x16.le_s |
0x29 |
:+1: |
:+1: |
i8x16.le_u |
0x2a |
:+1: |
:+1: |
i8x16.ge_s |
0x2b |
:+1: |
:+1: |
i8x16.ge_u |
0x2c |
:+1: |
:+1: |
i16x8.eq |
0x2d |
:+1: |
:+1: |
i16x8.ne |
0x2e |
:+1: |
:+1: |
i16x8.lt_s |
0x2f |
:+1: |
:+1: |
i16x8.lt_u |
0x30 |
:+1: |
:+1: |
i16x8.gt_s |
0x31 |
:+1: |
:+1: |
i16x8.gt_u |
0x32 |
:+1: |
:+1: |
i16x8.le_s |
0x33 |
:+1: |
:+1: |
i16x8.le_u |
0x34 |
:+1: |
:+1: |
i16x8.ge_s |
0x35 |
:+1: |
:+1: |
i16x8.ge_u |
0x36 |
:+1: |
:+1: |
i32x4.eq |
0x37 |
:+1: |
:+1: |
i32x4.ne |
0x38 |
:+1: |
:+1: |
i32x4.lt_s |
0x39 |
:+1: |
:+1: |
i32x4.lt_u |
0x3a |
:+1: |
:+1: |
i32x4.gt_s |
0x3b |
:+1: |
:+1: |
i32x4.gt_u |
0x3c |
:+1: |
:+1: |
i32x4.le_s |
0x3d |
:+1: |
:+1: |
i32x4.le_u |
0x3e |
:+1: |
:+1: |
i32x4.ge_s |
0x3f |
:+1: |
:+1: |
i32x4.ge_u |
0x40 |
:+1: |
:+1: |
Float Cmp |
Opcode |
Old Backend Status |
VCode Status |
f32x4.eq |
0x41 |
:+1: |
:+1: |
f32x4.ne |
0x42 |
:+1: |
:+1: |
f32x4.lt |
0x43 |
:+1: |
:+1: |
f32x4.gt |
0x44 |
:+1: |
:+1: |
f32x4.le |
0x45 |
:+1: |
:+1: |
f32x4.ge |
0x46 |
:+1: |
:+1: |
f64x2.eq |
0x47 |
:+1: |
:+1: |
f64x2.ne |
0x48 |
:+1: |
:+1: |
f64x2.lt |
0x49 |
:+1: |
:+1: |
f64x2.gt |
0x4a |
:+1: |
:+1: |
f64x2.le |
0x4b |
:+1: |
:+1: |
f64x2.ge |
0x4c |
:+1: |
:+1: |
v128 Op |
Opcode |
Old Backend Status |
VCode Status |
v128.not |
0x4d |
:+1: |
:+1: |
v128.and |
0x4e |
:+1: |
:+1: |
v128.andnot |
0x4f |
:+1: |
:+1: |
v128.or |
0x50 |
:+1: |
:+1: |
v128.xor |
0x51 |
:+1: |
:+1: |
v128.bitselect |
0x52 |
:+1: |
:+1: |
i8x16 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i8x16.abs |
0x60 |
:+1: |
:+1: |
i8x16.neg |
0x61 |
:+1: |
:+1: |
i8x16.any_true |
0x62 |
:+1: |
:+1: |
i8x16.all_true |
0x63 |
:+1: |
:+1: |
i8x16.bitmask |
0x64 |
:question: |
|
i8x16.narrow_i16x8_s |
0x65 |
:+1: |
|
i8x16.narrow_i16x8_u |
0x66 |
:+1: |
|
---- widen ---- |
0x67 |
-- |
|
---- widen ---- |
0x68 |
-- |
|
---- widen ---- |
0x69 |
-- |
|
---- widen ---- |
0x6a |
-- |
|
i8x16.shl |
0x6b |
:+1: |
@abrown |
i8x16.shr_s |
0x6c |
:+1: |
@abrown |
i8x16.shr_u |
0x6d |
:+1: |
@abrown |
i8x16.add |
0x6e |
:+1: |
:+1: |
i8x16.add_sat_s |
0x6f |
:+1: |
:+1: |
i8x16.add_sat_u |
0x70 |
:+1: |
:+1: |
i8x16.sub |
0x71 |
:+1: |
:+1: |
i8x16.sub_sat_s |
0x72 |
:+1: |
:+1: |
i8x16.sub_sat_u |
0x73 |
:+1: |
:+1: |
---- dot ---- |
0x74 |
-- |
|
---- mul ---- |
0x75 |
:question: |
|
i8x16.min_s |
0x76 |
:+1: |
:+1: |
i8x16.min_u |
0x77 |
:+1: |
:+1: |
i8x16.max_s |
0x78 |
:+1: |
:+1: |
i8x16.max_u |
0x79 |
:+1: |
:+1: |
---- avgr_s ---- |
0x7a |
-- |
|
i8x16.avgr_u |
0x7b |
:+1: |
:+1: |
i16x8 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i16x8.abs |
0x80 |
:+1: |
:+1: |
i16x8.neg |
0x81 |
:+1: |
:+1: |
i16x8.any_true |
0x82 |
:+1: |
:+1: |
i16x8.all_true |
0x83 |
:+1: |
:+1: |
i16x8.bitmask |
0x84 |
:question: |
|
i16x8.narrow_i32x4_s |
0x85 |
:+1: |
|
i16x8.narrow_i32x4_u |
0x86 |
:+1: |
|
i16x8.widen_low_i8x16_s |
0x87 |
:+1: |
|
i16x8.widen_high_i8x16_s |
0x88 |
:+1: |
|
i16x8.widen_low_i8x16_u |
0x89 |
:+1: |
|
i16x8.widen_high_i8x16_u |
0x8a |
:+1: |
|
i16x8.shl |
0x8b |
:+1: |
@abrown |
i16x8.shr_s |
0x8c |
:+1: |
@abrown |
i16x8.shr_u |
0x8d |
:+1: |
@abrown |
i16x8.add |
0x8e |
:+1: |
:+1: |
i16x8.add_sat_s |
0x8f |
:+1: |
:+1: |
i16x8.add_sat_u |
0x90 |
:+1: |
:+1: |
i16x8.sub |
0x91 |
:+1: |
:+1: |
i16x8.sub_sat_s |
0x92 |
:+1: |
:+1: |
i16x8.sub_sat_u |
0x93 |
:+1: |
:+1: |
---- dot ---- |
0x94 |
-- |
|
i16x8.mul |
0x95 |
:+1: |
:+1: |
i16x8.min_s |
0x96 |
:+1: |
:+1: |
i16x8.min_u |
0x97 |
:+1: |
:+1: |
i16x8.max_s |
0x98 |
:+1: |
:+1: |
i16x8.max_u |
0x99 |
:+1: |
:+1: |
---- avgr_s ---- |
0x9a |
-- |
|
i16x8.avgr_u |
0x9b |
:+1: |
:+1: |
i32x4 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i32x4.abs |
0xa0 |
:+1: |
:+1: |
i32x4.neg |
0xa1 |
:+1: |
:+1: |
i32x4.any_true |
0xa2 |
:+1: |
:+1: |
i32x4.all_true |
0xa3 |
:+1: |
:+1: |
i32x4.bitmask |
0xa4 |
:question: |
|
---- narrow ---- |
0xa5 |
-- |
|
---- narrow ---- |
0xa6 |
-- |
|
i32x4.widen_low_i16x8_s |
0xa7 |
:+1: |
|
i32x4.widen_high_i16x8_s |
0xa8 |
:+1: |
|
i32x4.widen_low_i16x8_u |
0xa9 |
:+1: |
|
i32x4.widen_high_i16x8_u |
0xaa |
:+1: |
|
i32x4.shl |
0xab |
:+1: |
@abrown |
i32x4.shr_s |
0xac |
:+1: |
@abrown |
i32x4.shr_u |
0xad |
:+1: |
@abrown |
i32x4.add |
0xae |
:+1: |
:+1: |
---- add_sat ---- |
0xaf |
-- |
|
---- add_sat ---- |
0xb0 |
-- |
|
i32x4.sub |
0xb1 |
:+1: |
:+1: |
---- sub_sat ---- |
0xb2 |
-- |
|
---- sub_sat ---- |
0xb3 |
-- |
|
---- dot ---- |
0xb4 |
-- |
|
i32x4.mul |
0xb5 |
:+1: |
:+1: |
i32x4.min_s |
0xb6 |
:+1: |
:+1: |
i32x4.min_u |
0xb7 |
:+1: |
:+1: |
i32x4.max_s |
0xb8 |
:+1: |
:+1: |
i32x4.max_u |
0xb9 |
:+1: |
:+1: |
---- avgr_s ---- |
0xba |
-- |
|
---- avgr_u ---- |
0xbb |
-- |
|
i64x2 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
---- |
0xc0 |
-- |
|
i64x2.neg |
0xc1 |
:+1: |
|
---- |
0xc2 |
-- |
|
---- |
0xc3 |
-- |
|
---- |
0xc4 |
-- |
|
---- |
0xc5 |
-- |
|
---- |
0xc6 |
-- |
|
---- |
0xc7 |
-- |
|
---- |
0xc8 |
-- |
|
---- |
0xc9 |
-- |
|
---- |
0xca |
-- |
|
i64x2.shl |
0xcb |
:+1: |
@abrown |
i64x2.shr_s |
0xcc |
:+1: |
@abrown |
i64x2.shr_u |
0xcd |
:+1: |
@abrown |
i64x2.add |
0xce |
:+1: |
:+1: |
---- |
0xcf |
-- |
|
---- |
0xd0 |
-- |
|
i64x2.sub |
0xd1 |
:+1: |
:+1: |
---- |
0xd2 |
-- |
|
---- |
0xd3 |
-- |
|
---- |
0xd4 |
-- |
|
i64x2.mul |
0xd5 |
:+1: |
:+1: |
---- |
0xd6 |
-- |
|
---- |
0xd7 |
-- |
|
f32x4 Op |
Opcode |
Old Backend Status |
VCode Status |
f32x4.ceil |
0xd8 |
:question: |
|
f32x4.floor |
0xd9 |
:question: |
|
f32x4.trunc |
0xda |
:question: |
|
f32x4.nearest |
0xdb |
:question: |
|
f32x4.abs |
0xe0 |
:+1: |
:+1: |
f32x4.neg |
0xe1 |
:+1: |
:+1: |
---- round ---- |
0xe2 |
-- |
|
f32x4.sqrt |
0xe3 |
:+1: |
:+1: |
f32x4.add |
0xe4 |
:+1: |
:+1: |
f32x4.sub |
0xe5 |
:+1: |
:+1: |
f32x4.mul |
0xe6 |
:+1: |
:+1: |
f32x4.div |
0xe7 |
:+1: |
:+1: |
f32x4.min |
0xe8 |
:+1: |
:+1: |
f32x4.max |
0xe9 |
:+1: |
:+1: |
f32x4.pmin |
0xea |
:question: |
|
f32x4.pmax |
0xeb |
:question: |
|
f64x2 Op |
Opcode |
Old Backend Status |
VCode Status |
f64x2.ceil |
0xdc |
:question: |
|
f64x2.floor |
0xdd |
:question: |
|
f64x2.trunc |
0xde |
:question: |
|
f64x2.nearest |
0xdf |
:question: |
|
f64x2.abs |
0xec |
:+1: |
:+1: |
f64x2.neg |
0xed |
:+1: |
:+1: |
---- round ---- |
0xee |
-- |
|
f64x2.sqrt |
0xef |
:+1: |
:+1: |
f64x2.add |
0xf0 |
:+1: |
:+1: |
f64x2.sub |
0xf1 |
:+1: |
:+1: |
f64x2.mul |
0xf2 |
:+1: |
:+1: |
f64x2.div |
0xf3 |
:+1: |
:+1: |
f64x2.min |
0xf4 |
:+1: |
:+1: |
f64x2.max |
0xf5 |
:+1: |
:+1: |
f64x2.pmin |
0xf6 |
:question: |
|
f64x2.pmax |
0xf7 |
:question: |
|
Conversion Op |
Opcode |
Old Backend Status |
VCode Status |
i32x4.trunc_sat_f32x4_s |
0xf8 |
:+1: |
@jlb6740 |
i32x4.trunc_sat_f32x4_u |
0xf9 |
:+1: |
@jlb6740 |
f32x4.convert_i32x4_s |
0xfa |
:+1: |
@jlb6740 |
f32x4.convert_i32x4_u |
0xfb |
:+1: |
@jlb6740 |
jlb6740 edited Issue #2272:
Last Update: 10/13/2020
Loads |
Opcode |
Old Backend Status |
VCode Status |
v128.load |
0x00 |
:+1: |
:+1: |
v128.load8x8_s |
0x01 |
:+1: |
-- |
v128.load8x8_u |
0x02 |
:+1: |
-- |
v128.load16x4_s |
0x03 |
:+1: |
-- |
v128.load16x4_u |
0x04 |
:+1: |
-- |
v128.load32x2_s |
0x05 |
:+1: |
-- |
v128.load32x2_u |
0x06 |
:+1: |
-- |
v128.load8_splat |
0x07 |
:+1: |
-- |
v128.load16_splat |
0x08 |
:+1: |
-- |
v128.load32_splat |
0x09 |
:+1: |
-- |
v128.load64_splat |
0x0a |
:+1: |
-- |
Stores |
Opcode |
Old Backend Status |
VCode Status |
v128.store |
0x0b |
:+1: |
:+1: |
Basic operation |
Opcode |
Old Backend Status |
VCode Status |
v128.const |
0x0c |
:+1: |
:+1: |
i8x16.shuffle |
0x0d |
:+1: |
:+1: |
i8x16.swizzle |
0x0e |
:+1: |
:+1: |
Splat operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.splat |
0x0f |
:+1: |
:+1: |
i16x8.splat |
0x10 |
:+1: |
:+1: |
i32x4.splat |
0x11 |
:+1: |
:+1: |
i64x2.splat |
0x12 |
:+1: |
:+1: |
f32x4.splat |
0x13 |
:+1: |
:+1: |
f64x2.splat |
0x14 |
:+1: |
:+1: |
Lane operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.extract_lane_s |
0x15 |
:+1: |
:+1: |
i8x16.extract_lane_u |
0x16 |
:+1: |
:+1: |
i8x16.replace_lane |
0x17 |
:+1: |
:+1: |
i16x8.extract_lane_s |
0x18 |
:+1: |
:+1: |
i16x8.extract_lane_u |
0x19 |
:+1: |
:+1: |
i16x8.replace_lane |
0x1a |
:+1: |
:+1: |
i32x4.extract_lane |
0x1b |
:+1: |
:+1: |
i32x4.replace_lane |
0x1c |
:+1: |
:+1: |
i64x2.extract_lane |
0x1d |
:+1: |
:+1: |
i64x2.replace_lane |
0x1e |
:+1: |
:+1: |
f32x4.extract_lane |
0x1f |
:+1: |
:+1: |
f32x4.replace_lane |
0x20 |
:+1: |
:+1: |
f64x2.extract_lane |
0x21 |
:+1: |
:+1: |
f64x2.replace_lane |
0x22 |
:+1: |
:+1: |
Integer Cmp |
Opcode |
Old Backend Status |
VCode Status |
i8x16.eq |
0x23 |
:+1: |
:+1: |
i8x16.ne |
0x24 |
:+1: |
:+1: |
i8x16.lt_s |
0x25 |
:+1: |
:+1: |
i8x16.lt_u |
0x26 |
:+1: |
:+1: |
i8x16.gt_s |
0x27 |
:+1: |
:+1: |
i8x16.gt_u |
0x28 |
:+1: |
:+1: |
i8x16.le_s |
0x29 |
:+1: |
:+1: |
i8x16.le_u |
0x2a |
:+1: |
:+1: |
i8x16.ge_s |
0x2b |
:+1: |
:+1: |
i8x16.ge_u |
0x2c |
:+1: |
:+1: |
i16x8.eq |
0x2d |
:+1: |
:+1: |
i16x8.ne |
0x2e |
:+1: |
:+1: |
i16x8.lt_s |
0x2f |
:+1: |
:+1: |
i16x8.lt_u |
0x30 |
:+1: |
:+1: |
i16x8.gt_s |
0x31 |
:+1: |
:+1: |
i16x8.gt_u |
0x32 |
:+1: |
:+1: |
i16x8.le_s |
0x33 |
:+1: |
:+1: |
i16x8.le_u |
0x34 |
:+1: |
:+1: |
i16x8.ge_s |
0x35 |
:+1: |
:+1: |
i16x8.ge_u |
0x36 |
:+1: |
:+1: |
i32x4.eq |
0x37 |
:+1: |
:+1: |
i32x4.ne |
0x38 |
:+1: |
:+1: |
i32x4.lt_s |
0x39 |
:+1: |
:+1: |
i32x4.lt_u |
0x3a |
:+1: |
:+1: |
i32x4.gt_s |
0x3b |
:+1: |
:+1: |
i32x4.gt_u |
0x3c |
:+1: |
:+1: |
i32x4.le_s |
0x3d |
:+1: |
:+1: |
i32x4.le_u |
0x3e |
:+1: |
:+1: |
i32x4.ge_s |
0x3f |
:+1: |
:+1: |
i32x4.ge_u |
0x40 |
:+1: |
:+1: |
Float Cmp |
Opcode |
Old Backend Status |
VCode Status |
f32x4.eq |
0x41 |
:+1: |
:+1: |
f32x4.ne |
0x42 |
:+1: |
:+1: |
f32x4.lt |
0x43 |
:+1: |
:+1: |
f32x4.gt |
0x44 |
:+1: |
:+1: |
f32x4.le |
0x45 |
:+1: |
:+1: |
f32x4.ge |
0x46 |
:+1: |
:+1: |
f64x2.eq |
0x47 |
:+1: |
:+1: |
f64x2.ne |
0x48 |
:+1: |
:+1: |
f64x2.lt |
0x49 |
:+1: |
:+1: |
f64x2.gt |
0x4a |
:+1: |
:+1: |
f64x2.le |
0x4b |
:+1: |
:+1: |
f64x2.ge |
0x4c |
:+1: |
:+1: |
v128 Op |
Opcode |
Old Backend Status |
VCode Status |
v128.not |
0x4d |
:+1: |
:+1: |
v128.and |
0x4e |
:+1: |
:+1: |
v128.andnot |
0x4f |
:+1: |
:+1: |
v128.or |
0x50 |
:+1: |
:+1: |
v128.xor |
0x51 |
:+1: |
:+1: |
v128.bitselect |
0x52 |
:+1: |
:+1: |
i8x16 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i8x16.abs |
0x60 |
:+1: |
:+1: |
i8x16.neg |
0x61 |
:+1: |
:+1: |
i8x16.any_true |
0x62 |
:+1: |
:+1: |
i8x16.all_true |
0x63 |
:+1: |
:+1: |
i8x16.bitmask |
0x64 |
:question: |
|
i8x16.narrow_i16x8_s |
0x65 |
:+1: |
|
i8x16.narrow_i16x8_u |
0x66 |
:+1: |
|
---- widen ---- |
0x67 |
-- |
|
---- widen ---- |
0x68 |
-- |
|
---- widen ---- |
0x69 |
-- |
|
---- widen ---- |
0x6a |
-- |
|
i8x16.shl |
0x6b |
:+1: |
@abrown |
i8x16.shr_s |
0x6c |
:+1: |
@abrown |
i8x16.shr_u |
0x6d |
:+1: |
@abrown |
i8x16.add |
0x6e |
:+1: |
:+1: |
i8x16.add_sat_s |
0x6f |
:+1: |
:+1: |
i8x16.add_sat_u |
0x70 |
:+1: |
:+1: |
i8x16.sub |
0x71 |
:+1: |
:+1: |
i8x16.sub_sat_s |
0x72 |
:+1: |
:+1: |
i8x16.sub_sat_u |
0x73 |
:+1: |
:+1: |
---- dot ---- |
0x74 |
-- |
|
---- mul ---- |
0x75 |
:question: |
|
i8x16.min_s |
0x76 |
:+1: |
:+1: |
i8x16.min_u |
0x77 |
:+1: |
:+1: |
i8x16.max_s |
0x78 |
:+1: |
:+1: |
i8x16.max_u |
0x79 |
:+1: |
:+1: |
---- avgr_s ---- |
0x7a |
-- |
|
i8x16.avgr_u |
0x7b |
:+1: |
:+1: |
i16x8 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i16x8.abs |
0x80 |
:+1: |
:+1: |
i16x8.neg |
0x81 |
:+1: |
:+1: |
i16x8.any_true |
0x82 |
:+1: |
:+1: |
i16x8.all_true |
0x83 |
:+1: |
:+1: |
i16x8.bitmask |
0x84 |
:question: |
|
i16x8.narrow_i32x4_s |
0x85 |
:+1: |
|
i16x8.narrow_i32x4_u |
0x86 |
:+1: |
|
i16x8.widen_low_i8x16_s |
0x87 |
:+1: |
|
i16x8.widen_high_i8x16_s |
0x88 |
:+1: |
|
i16x8.widen_low_i8x16_u |
0x89 |
:+1: |
|
i16x8.widen_high_i8x16_u |
0x8a |
:+1: |
|
i16x8.shl |
0x8b |
:+1: |
@abrown |
i16x8.shr_s |
0x8c |
:+1: |
@abrown |
i16x8.shr_u |
0x8d |
:+1: |
@abrown |
i16x8.add |
0x8e |
:+1: |
:+1: |
i16x8.add_sat_s |
0x8f |
:+1: |
:+1: |
i16x8.add_sat_u |
0x90 |
:+1: |
:+1: |
i16x8.sub |
0x91 |
:+1: |
:+1: |
i16x8.sub_sat_s |
0x92 |
:+1: |
:+1: |
i16x8.sub_sat_u |
0x93 |
:+1: |
:+1: |
---- dot ---- |
0x94 |
-- |
|
i16x8.mul |
0x95 |
:+1: |
:+1: |
i16x8.min_s |
0x96 |
:+1: |
:+1: |
i16x8.min_u |
0x97 |
:+1: |
:+1: |
i16x8.max_s |
0x98 |
:+1: |
:+1: |
i16x8.max_u |
0x99 |
:+1: |
:+1: |
---- avgr_s ---- |
0x9a |
-- |
|
i16x8.avgr_u |
0x9b |
:+1: |
:+1: |
i32x4 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i32x4.abs |
0xa0 |
:+1: |
:+1: |
i32x4.neg |
0xa1 |
:+1: |
:+1: |
i32x4.any_true |
0xa2 |
:+1: |
:+1: |
i32x4.all_true |
0xa3 |
:+1: |
:+1: |
i32x4.bitmask |
0xa4 |
:question: |
|
---- narrow ---- |
0xa5 |
-- |
|
---- narrow ---- |
0xa6 |
-- |
|
i32x4.widen_low_i16x8_s |
0xa7 |
:+1: |
|
i32x4.widen_high_i16x8_s |
0xa8 |
:+1: |
|
i32x4.widen_low_i16x8_u |
0xa9 |
:+1: |
|
i32x4.widen_high_i16x8_u |
0xaa |
:+1: |
|
i32x4.shl |
0xab |
:+1: |
@abrown |
i32x4.shr_s |
0xac |
:+1: |
@abrown |
i32x4.shr_u |
0xad |
:+1: |
@abrown |
i32x4.add |
0xae |
:+1: |
:+1: |
---- add_sat ---- |
0xaf |
-- |
|
---- add_sat ---- |
0xb0 |
-- |
|
i32x4.sub |
0xb1 |
:+1: |
:+1: |
---- sub_sat ---- |
0xb2 |
-- |
|
---- sub_sat ---- |
0xb3 |
-- |
|
---- dot ---- |
0xb4 |
-- |
|
i32x4.mul |
0xb5 |
:+1: |
:+1: |
i32x4.min_s |
0xb6 |
:+1: |
:+1: |
i32x4.min_u |
0xb7 |
:+1: |
:+1: |
i32x4.max_s |
0xb8 |
:+1: |
:+1: |
i32x4.max_u |
0xb9 |
:+1: |
:+1: |
---- avgr_s ---- |
0xba |
-- |
|
---- avgr_u ---- |
0xbb |
-- |
|
i64x2 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
---- |
0xc0 |
-- |
|
i64x2.neg |
0xc1 |
:+1: |
|
---- |
0xc2 |
-- |
|
---- |
0xc3 |
-- |
|
---- |
0xc4 |
-- |
|
---- |
0xc5 |
-- |
|
---- |
0xc6 |
-- |
|
---- |
0xc7 |
-- |
|
---- |
0xc8 |
-- |
|
---- |
0xc9 |
-- |
|
---- |
0xca |
-- |
|
i64x2.shl |
0xcb |
:+1: |
@abrown |
i64x2.shr_s |
0xcc |
:+1: |
@abrown |
i64x2.shr_u |
0xcd |
:+1: |
@abrown |
i64x2.add |
0xce |
:+1: |
:+1: |
---- |
0xcf |
-- |
|
---- |
0xd0 |
-- |
|
i64x2.sub |
0xd1 |
:+1: |
:+1: |
---- |
0xd2 |
-- |
|
---- |
0xd3 |
-- |
|
---- |
0xd4 |
-- |
|
i64x2.mul |
0xd5 |
:+1: |
:+1: |
---- |
0xd6 |
-- |
|
---- |
0xd7 |
-- |
|
f32x4 Op |
Opcode |
Old Backend Status |
VCode Status |
f32x4.ceil |
0xd8 |
:question: |
|
f32x4.floor |
0xd9 |
:question: |
|
f32x4.trunc |
0xda |
:question: |
|
f32x4.nearest |
0xdb |
:question: |
|
f32x4.abs |
0xe0 |
:+1: |
:+1: |
f32x4.neg |
0xe1 |
:+1: |
:+1: |
---- round ---- |
0xe2 |
-- |
|
f32x4.sqrt |
0xe3 |
:+1: |
:+1: |
f32x4.add |
0xe4 |
:+1: |
:+1: |
f32x4.sub |
0xe5 |
:+1: |
:+1: |
f32x4.mul |
0xe6 |
:+1: |
:+1: |
f32x4.div |
0xe7 |
:+1: |
:+1: |
f32x4.min |
0xe8 |
:+1: |
:+1: |
f32x4.max |
0xe9 |
:+1: |
:+1: |
f32x4.pmin |
0xea |
:question: |
|
f32x4.pmax |
0xeb |
:question: |
|
f64x2 Op |
Opcode |
Old Backend Status |
VCode Status |
f64x2.ceil |
0xdc |
:question: |
|
f64x2.floor |
0xdd |
:question: |
|
f64x2.trunc |
0xde |
:question: |
|
f64x2.nearest |
0xdf |
:question: |
|
f64x2.abs |
0xec |
:+1: |
:+1: |
f64x2.neg |
0xed |
:+1: |
:+1: |
---- round ---- |
0xee |
-- |
|
f64x2.sqrt |
0xef |
:+1: |
:+1: |
f64x2.add |
0xf0 |
:+1: |
:+1: |
f64x2.sub |
0xf1 |
:+1: |
:+1: |
f64x2.mul |
0xf2 |
:+1: |
:+1: |
f64x2.div |
0xf3 |
:+1: |
:+1: |
f64x2.min |
0xf4 |
:+1: |
:+1: |
f64x2.max |
0xf5 |
:+1: |
:+1: |
f64x2.pmin |
0xf6 |
:question: |
|
f64x2.pmax |
0xf7 |
:question: |
|
Conversion Op |
Opcode |
Old Backend Status |
VCode Status |
i32x4.trunc_sat_f32x4_s |
0xf8 |
:+1: |
@jlb6740 |
i32x4.trunc_sat_f32x4_u |
0xf9 |
:+1: |
@jlb6740 |
f32x4.convert_i32x4_s |
0xfa |
:+1: |
@jlb6740 |
f32x4.convert_i32x4_u |
0xfb |
:+1: |
@jlb6740 |
jlb6740 edited Issue #2272:
Last Update: 10/13/2020
Loads |
Opcode |
Old Backend Status |
VCode Status |
v128.load |
0x00 |
:+1: |
:+1: |
v128.load8x8_s |
0x01 |
:+1: |
-- |
v128.load8x8_u |
0x02 |
:+1: |
-- |
v128.load16x4_s |
0x03 |
:+1: |
-- |
v128.load16x4_u |
0x04 |
:+1: |
-- |
v128.load32x2_s |
0x05 |
:+1: |
-- |
v128.load32x2_u |
0x06 |
:+1: |
-- |
v128.load8_splat |
0x07 |
:+1: |
-- |
v128.load16_splat |
0x08 |
:+1: |
-- |
v128.load32_splat |
0x09 |
:+1: |
-- |
v128.load64_splat |
0x0a |
:+1: |
-- |
Stores |
Opcode |
Old Backend Status |
VCode Status |
v128.store |
0x0b |
:+1: |
:+1: |
Basic operation |
Opcode |
Old Backend Status |
VCode Status |
v128.const |
0x0c |
:+1: |
:+1: |
i8x16.shuffle |
0x0d |
:+1: |
:+1: |
i8x16.swizzle |
0x0e |
:+1: |
:+1: |
Splat operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.splat |
0x0f |
:+1: |
:+1: |
i16x8.splat |
0x10 |
:+1: |
:+1: |
i32x4.splat |
0x11 |
:+1: |
:+1: |
i64x2.splat |
0x12 |
:+1: |
:+1: |
f32x4.splat |
0x13 |
:+1: |
:+1: |
f64x2.splat |
0x14 |
:+1: |
:+1: |
Lane operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.extract_lane_s |
0x15 |
:+1: |
:+1: |
i8x16.extract_lane_u |
0x16 |
:+1: |
:+1: |
i8x16.replace_lane |
0x17 |
:+1: |
:+1: |
i16x8.extract_lane_s |
0x18 |
:+1: |
:+1: |
i16x8.extract_lane_u |
0x19 |
:+1: |
:+1: |
i16x8.replace_lane |
0x1a |
:+1: |
:+1: |
i32x4.extract_lane |
0x1b |
:+1: |
:+1: |
i32x4.replace_lane |
0x1c |
:+1: |
:+1: |
i64x2.extract_lane |
0x1d |
:+1: |
:+1: |
i64x2.replace_lane |
0x1e |
:+1: |
:+1: |
f32x4.extract_lane |
0x1f |
:+1: |
:+1: |
f32x4.replace_lane |
0x20 |
:+1: |
:+1: |
f64x2.extract_lane |
0x21 |
:+1: |
:+1: |
f64x2.replace_lane |
0x22 |
:+1: |
:+1: |
Integer Cmp |
Opcode |
Old Backend Status |
VCode Status |
i8x16.eq |
0x23 |
:+1: |
:+1: |
i8x16.ne |
0x24 |
:+1: |
:+1: |
i8x16.lt_s |
0x25 |
:+1: |
:+1: |
i8x16.lt_u |
0x26 |
:+1: |
:+1: |
i8x16.gt_s |
0x27 |
:+1: |
:+1: |
i8x16.gt_u |
0x28 |
:+1: |
:+1: |
i8x16.le_s |
0x29 |
:+1: |
:+1: |
i8x16.le_u |
0x2a |
:+1: |
:+1: |
i8x16.ge_s |
0x2b |
:+1: |
:+1: |
i8x16.ge_u |
0x2c |
:+1: |
:+1: |
i16x8.eq |
0x2d |
:+1: |
:+1: |
i16x8.ne |
0x2e |
:+1: |
:+1: |
i16x8.lt_s |
0x2f |
:+1: |
:+1: |
i16x8.lt_u |
0x30 |
:+1: |
:+1: |
i16x8.gt_s |
0x31 |
:+1: |
:+1: |
i16x8.gt_u |
0x32 |
:+1: |
:+1: |
i16x8.le_s |
0x33 |
:+1: |
:+1: |
i16x8.le_u |
0x34 |
:+1: |
:+1: |
i16x8.ge_s |
0x35 |
:+1: |
:+1: |
i16x8.ge_u |
0x36 |
:+1: |
:+1: |
i32x4.eq |
0x37 |
:+1: |
:+1: |
i32x4.ne |
0x38 |
:+1: |
:+1: |
i32x4.lt_s |
0x39 |
:+1: |
:+1: |
i32x4.lt_u |
0x3a |
:+1: |
:+1: |
i32x4.gt_s |
0x3b |
:+1: |
:+1: |
i32x4.gt_u |
0x3c |
:+1: |
:+1: |
i32x4.le_s |
0x3d |
:+1: |
:+1: |
i32x4.le_u |
0x3e |
:+1: |
:+1: |
i32x4.ge_s |
0x3f |
:+1: |
:+1: |
i32x4.ge_u |
0x40 |
:+1: |
:+1: |
Float Cmp |
Opcode |
Old Backend Status |
VCode Status |
f32x4.eq |
0x41 |
:+1: |
:+1: |
f32x4.ne |
0x42 |
:+1: |
:+1: |
f32x4.lt |
0x43 |
:+1: |
:+1: |
f32x4.gt |
0x44 |
:+1: |
:+1: |
f32x4.le |
0x45 |
:+1: |
:+1: |
f32x4.ge |
0x46 |
:+1: |
:+1: |
f64x2.eq |
0x47 |
:+1: |
:+1: |
f64x2.ne |
0x48 |
:+1: |
:+1: |
f64x2.lt |
0x49 |
:+1: |
:+1: |
f64x2.gt |
0x4a |
:+1: |
:+1: |
f64x2.le |
0x4b |
:+1: |
:+1: |
f64x2.ge |
0x4c |
:+1: |
:+1: |
v128 Op |
Opcode |
Old Backend Status |
VCode Status |
v128.not |
0x4d |
:+1: |
:+1: |
v128.and |
0x4e |
:+1: |
:+1: |
v128.andnot |
0x4f |
:+1: |
:+1: |
v128.or |
0x50 |
:+1: |
:+1: |
v128.xor |
0x51 |
:+1: |
:+1: |
v128.bitselect |
0x52 |
:+1: |
:+1: |
i8x16 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i8x16.abs |
0x60 |
:+1: |
:+1: |
i8x16.neg |
0x61 |
:+1: |
:+1: |
i8x16.any_true |
0x62 |
:+1: |
:+1: |
i8x16.all_true |
0x63 |
:+1: |
:+1: |
i8x16.bitmask |
0x64 |
:question: |
|
i8x16.narrow_i16x8_s |
0x65 |
:+1: |
|
i8x16.narrow_i16x8_u |
0x66 |
:+1: |
|
---- widen ---- |
0x67 |
-- |
|
---- widen ---- |
0x68 |
-- |
|
---- widen ---- |
0x69 |
-- |
|
---- widen ---- |
0x6a |
-- |
|
i8x16.shl |
0x6b |
:+1: |
@abrown |
i8x16.shr_s |
0x6c |
:+1: |
@abrown |
i8x16.shr_u |
0x6d |
:+1: |
@abrown |
i8x16.add |
0x6e |
:+1: |
:+1: |
i8x16.add_sat_s |
0x6f |
:+1: |
:+1: |
i8x16.add_sat_u |
0x70 |
:+1: |
:+1: |
i8x16.sub |
0x71 |
:+1: |
:+1: |
i8x16.sub_sat_s |
0x72 |
:+1: |
:+1: |
i8x16.sub_sat_u |
0x73 |
:+1: |
:+1: |
---- dot ---- |
0x74 |
-- |
|
---- mul ---- |
0x75 |
:question: |
|
i8x16.min_s |
0x76 |
:+1: |
:+1: |
i8x16.min_u |
0x77 |
:+1: |
:+1: |
i8x16.max_s |
0x78 |
:+1: |
:+1: |
i8x16.max_u |
0x79 |
:+1: |
:+1: |
---- avgr_s ---- |
0x7a |
-- |
|
i8x16.avgr_u |
0x7b |
:+1: |
:+1: |
i16x8 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i16x8.abs |
0x80 |
:+1: |
:+1: |
i16x8.neg |
0x81 |
:+1: |
:+1: |
i16x8.any_true |
0x82 |
:+1: |
:+1: |
i16x8.all_true |
0x83 |
:+1: |
:+1: |
i16x8.bitmask |
0x84 |
:question: |
|
i16x8.narrow_i32x4_s |
0x85 |
:+1: |
|
i16x8.narrow_i32x4_u |
0x86 |
:+1: |
|
i16x8.widen_low_i8x16_s |
0x87 |
:+1: |
|
i16x8.widen_high_i8x16_s |
0x88 |
:+1: |
|
i16x8.widen_low_i8x16_u |
0x89 |
:+1: |
|
i16x8.widen_high_i8x16_u |
0x8a |
:+1: |
|
i16x8.shl |
0x8b |
:+1: |
@abrown |
i16x8.shr_s |
0x8c |
:+1: |
@abrown |
i16x8.shr_u |
0x8d |
:+1: |
@abrown |
i16x8.add |
0x8e |
:+1: |
:+1: |
i16x8.add_sat_s |
0x8f |
:+1: |
:+1: |
i16x8.add_sat_u |
0x90 |
:+1: |
:+1: |
i16x8.sub |
0x91 |
:+1: |
:+1: |
i16x8.sub_sat_s |
0x92 |
:+1: |
:+1: |
i16x8.sub_sat_u |
0x93 |
:+1: |
:+1: |
---- dot ---- |
0x94 |
-- |
|
i16x8.mul |
0x95 |
:+1: |
:+1: |
i16x8.min_s |
0x96 |
:+1: |
:+1: |
i16x8.min_u |
0x97 |
:+1: |
:+1: |
i16x8.max_s |
0x98 |
:+1: |
:+1: |
i16x8.max_u |
0x99 |
:+1: |
:+1: |
---- avgr_s ---- |
0x9a |
-- |
|
i16x8.avgr_u |
0x9b |
:+1: |
:+1: |
i32x4 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i32x4.abs |
0xa0 |
:+1: |
:+1: |
i32x4.neg |
0xa1 |
:+1: |
:+1: |
i32x4.any_true |
0xa2 |
:+1: |
:+1: |
i32x4.all_true |
0xa3 |
:+1: |
:+1: |
i32x4.bitmask |
0xa4 |
:question: |
|
---- narrow ---- |
0xa5 |
-- |
|
---- narrow ---- |
0xa6 |
-- |
|
i32x4.widen_low_i16x8_s |
0xa7 |
:+1: |
|
i32x4.widen_high_i16x8_s |
0xa8 |
:+1: |
|
i32x4.widen_low_i16x8_u |
0xa9 |
:+1: |
|
i32x4.widen_high_i16x8_u |
0xaa |
:+1: |
|
i32x4.shl |
0xab |
:+1: |
@abrown |
i32x4.shr_s |
0xac |
:+1: |
@abrown |
i32x4.shr_u |
0xad |
:+1: |
@abrown |
i32x4.add |
0xae |
:+1: |
:+1: |
---- add_sat ---- |
0xaf |
-- |
|
---- add_sat ---- |
0xb0 |
-- |
|
i32x4.sub |
0xb1 |
:+1: |
:+1: |
---- sub_sat ---- |
0xb2 |
-- |
|
---- sub_sat ---- |
0xb3 |
-- |
|
---- dot ---- |
0xb4 |
-- |
|
i32x4.mul |
0xb5 |
:+1: |
:+1: |
i32x4.min_s |
0xb6 |
:+1: |
:+1: |
i32x4.min_u |
0xb7 |
:+1: |
:+1: |
i32x4.max_s |
0xb8 |
:+1: |
:+1: |
i32x4.max_u |
0xb9 |
:+1: |
:+1: |
---- avgr_s ---- |
0xba |
-- |
|
---- avgr_u ---- |
0xbb |
-- |
|
i64x2 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
---- |
0xc0 |
-- |
|
i64x2.neg |
0xc1 |
:+1: |
|
---- |
0xc2 |
-- |
|
---- |
0xc3 |
-- |
|
---- |
0xc4 |
-- |
|
---- |
0xc5 |
-- |
|
---- |
0xc6 |
-- |
|
---- |
0xc7 |
-- |
|
---- |
0xc8 |
-- |
|
---- |
0xc9 |
-- |
|
---- |
0xca |
-- |
|
i64x2.shl |
0xcb |
:+1: |
@abrown |
i64x2.shr_s |
0xcc |
:+1: |
@abrown |
i64x2.shr_u |
0xcd |
:+1: |
@abrown |
i64x2.add |
0xce |
:+1: |
:+1: |
---- |
0xcf |
-- |
|
---- |
0xd0 |
-- |
|
i64x2.sub |
0xd1 |
:+1: |
:+1: |
---- |
0xd2 |
-- |
|
---- |
0xd3 |
-- |
|
---- |
0xd4 |
-- |
|
i64x2.mul |
0xd5 |
:+1: |
:+1: |
---- |
0xd6 |
-- |
|
---- |
0xd7 |
-- |
|
f32x4 Op |
Opcode |
Old Backend Status |
VCode Status |
f32x4.ceil |
0xd8 |
:question: |
|
f32x4.floor |
0xd9 |
:question: |
|
f32x4.trunc |
0xda |
:question: |
|
f32x4.nearest |
0xdb |
:question: |
|
f32x4.abs |
0xe0 |
:+1: |
:+1: |
f32x4.neg |
0xe1 |
:+1: |
:+1: |
---- round ---- |
0xe2 |
-- |
|
f32x4.sqrt |
0xe3 |
:+1: |
:+1: |
f32x4.add |
0xe4 |
:+1: |
:+1: |
f32x4.sub |
0xe5 |
:+1: |
:+1: |
f32x4.mul |
0xe6 |
:+1: |
:+1: |
f32x4.div |
0xe7 |
:+1: |
:+1: |
f32x4.min |
0xe8 |
:+1: |
:+1: |
f32x4.max |
0xe9 |
:+1: |
:+1: |
f32x4.pmin |
0xea |
:question: |
|
f32x4.pmax |
0xeb |
:question: |
|
f64x2 Op |
Opcode |
Old Backend Status |
VCode Status |
f64x2.ceil |
0xdc |
:question: |
|
f64x2.floor |
0xdd |
:question: |
|
f64x2.trunc |
0xde |
:question: |
|
f64x2.nearest |
0xdf |
:question: |
|
f64x2.abs |
0xec |
:+1: |
:+1: |
f64x2.neg |
0xed |
:+1: |
:+1: |
---- round ---- |
0xee |
-- |
|
f64x2.sqrt |
0xef |
:+1: |
:+1: |
f64x2.add |
0xf0 |
:+1: |
:+1: |
f64x2.sub |
0xf1 |
:+1: |
:+1: |
f64x2.mul |
0xf2 |
:+1: |
:+1: |
f64x2.div |
0xf3 |
:+1: |
:+1: |
f64x2.min |
0xf4 |
:+1: |
:+1: |
f64x2.max |
0xf5 |
:+1: |
:+1: |
f64x2.pmin |
0xf6 |
:question: |
|
f64x2.pmax |
0xf7 |
:question: |
|
Conversion Op |
Opcode |
Old Backend Status |
VCode Status |
i32x4.trunc_sat_f32x4_s |
0xf8 |
:+1: |
@jlb6740 |
i32x4.trunc_sat_f32x4_u |
0xf9 |
:+1: |
@jlb6740 |
f32x4.convert_i32x4_s |
0xfa |
:+1: |
@jlb6740 |
f32x4.convert_i32x4_u |
0xfb |
:question: |
@jlb6740 |
jlb6740 edited Issue #2272:
Last Update: 10/13/2020
Loads |
Opcode |
Old Backend Status |
VCode Status |
v128.load |
0x00 |
:+1: |
:+1: |
v128.load8x8_s |
0x01 |
:+1: |
-- |
v128.load8x8_u |
0x02 |
:+1: |
-- |
v128.load16x4_s |
0x03 |
:+1: |
-- |
v128.load16x4_u |
0x04 |
:+1: |
-- |
v128.load32x2_s |
0x05 |
:+1: |
-- |
v128.load32x2_u |
0x06 |
:+1: |
-- |
v128.load8_splat |
0x07 |
:+1: |
-- |
v128.load16_splat |
0x08 |
:+1: |
-- |
v128.load32_splat |
0x09 |
:+1: |
-- |
v128.load64_splat |
0x0a |
:+1: |
-- |
Stores |
Opcode |
Old Backend Status |
VCode Status |
v128.store |
0x0b |
:+1: |
:+1: |
Basic operation |
Opcode |
Old Backend Status |
VCode Status |
v128.const |
0x0c |
:+1: |
:+1: |
i8x16.shuffle |
0x0d |
:+1: |
:+1: |
i8x16.swizzle |
0x0e |
:+1: |
:+1: |
Splat operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.splat |
0x0f |
:+1: |
:+1: |
i16x8.splat |
0x10 |
:+1: |
:+1: |
i32x4.splat |
0x11 |
:+1: |
:+1: |
i64x2.splat |
0x12 |
:+1: |
:+1: |
f32x4.splat |
0x13 |
:+1: |
:+1: |
f64x2.splat |
0x14 |
:+1: |
:+1: |
Lane operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.extract_lane_s |
0x15 |
:+1: |
:+1: |
i8x16.extract_lane_u |
0x16 |
:+1: |
:+1: |
i8x16.replace_lane |
0x17 |
:+1: |
:+1: |
i16x8.extract_lane_s |
0x18 |
:+1: |
:+1: |
i16x8.extract_lane_u |
0x19 |
:+1: |
:+1: |
i16x8.replace_lane |
0x1a |
:+1: |
:+1: |
i32x4.extract_lane |
0x1b |
:+1: |
:+1: |
i32x4.replace_lane |
0x1c |
:+1: |
:+1: |
i64x2.extract_lane |
0x1d |
:+1: |
:+1: |
i64x2.replace_lane |
0x1e |
:+1: |
:+1: |
f32x4.extract_lane |
0x1f |
:+1: |
:+1: |
f32x4.replace_lane |
0x20 |
:+1: |
:+1: |
f64x2.extract_lane |
0x21 |
:+1: |
:+1: |
f64x2.replace_lane |
0x22 |
:+1: |
:+1: |
Integer Cmp |
Opcode |
Old Backend Status |
VCode Status |
i8x16.eq |
0x23 |
:+1: |
:+1: |
i8x16.ne |
0x24 |
:+1: |
:+1: |
i8x16.lt_s |
0x25 |
:+1: |
:+1: |
i8x16.lt_u |
0x26 |
:+1: |
:+1: |
i8x16.gt_s |
0x27 |
:+1: |
:+1: |
i8x16.gt_u |
0x28 |
:+1: |
:+1: |
i8x16.le_s |
0x29 |
:+1: |
:+1: |
i8x16.le_u |
0x2a |
:+1: |
:+1: |
i8x16.ge_s |
0x2b |
:+1: |
:+1: |
i8x16.ge_u |
0x2c |
:+1: |
:+1: |
i16x8.eq |
0x2d |
:+1: |
:+1: |
i16x8.ne |
0x2e |
:+1: |
:+1: |
i16x8.lt_s |
0x2f |
:+1: |
:+1: |
i16x8.lt_u |
0x30 |
:+1: |
:+1: |
i16x8.gt_s |
0x31 |
:+1: |
:+1: |
i16x8.gt_u |
0x32 |
:+1: |
:+1: |
i16x8.le_s |
0x33 |
:+1: |
:+1: |
i16x8.le_u |
0x34 |
:+1: |
:+1: |
i16x8.ge_s |
0x35 |
:+1: |
:+1: |
i16x8.ge_u |
0x36 |
:+1: |
:+1: |
i32x4.eq |
0x37 |
:+1: |
:+1: |
i32x4.ne |
0x38 |
:+1: |
:+1: |
i32x4.lt_s |
0x39 |
:+1: |
:+1: |
i32x4.lt_u |
0x3a |
:+1: |
:+1: |
i32x4.gt_s |
0x3b |
:+1: |
:+1: |
i32x4.gt_u |
0x3c |
:+1: |
:+1: |
i32x4.le_s |
0x3d |
:+1: |
:+1: |
i32x4.le_u |
0x3e |
:+1: |
:+1: |
i32x4.ge_s |
0x3f |
:+1: |
:+1: |
i32x4.ge_u |
0x40 |
:+1: |
:+1: |
Float Cmp |
Opcode |
Old Backend Status |
VCode Status |
f32x4.eq |
0x41 |
:+1: |
:+1: |
f32x4.ne |
0x42 |
:+1: |
:+1: |
f32x4.lt |
0x43 |
:+1: |
:+1: |
f32x4.gt |
0x44 |
:+1: |
:+1: |
f32x4.le |
0x45 |
:+1: |
:+1: |
f32x4.ge |
0x46 |
:+1: |
:+1: |
f64x2.eq |
0x47 |
:+1: |
:+1: |
f64x2.ne |
0x48 |
:+1: |
:+1: |
f64x2.lt |
0x49 |
:+1: |
:+1: |
f64x2.gt |
0x4a |
:+1: |
:+1: |
f64x2.le |
0x4b |
:+1: |
:+1: |
f64x2.ge |
0x4c |
:+1: |
:+1: |
v128 Op |
Opcode |
Old Backend Status |
VCode Status |
v128.not |
0x4d |
:+1: |
:+1: |
v128.and |
0x4e |
:+1: |
:+1: |
v128.andnot |
0x4f |
:+1: |
:+1: |
v128.or |
0x50 |
:+1: |
:+1: |
v128.xor |
0x51 |
:+1: |
:+1: |
v128.bitselect |
0x52 |
:+1: |
:+1: |
i8x16 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i8x16.abs |
0x60 |
:+1: |
:+1: |
i8x16.neg |
0x61 |
:+1: |
:+1: |
i8x16.any_true |
0x62 |
:+1: |
:+1: |
i8x16.all_true |
0x63 |
:+1: |
:+1: |
i8x16.bitmask |
0x64 |
:question: |
|
i8x16.narrow_i16x8_s |
0x65 |
:+1: |
|
i8x16.narrow_i16x8_u |
0x66 |
:+1: |
|
---- widen ---- |
0x67 |
-- |
|
---- widen ---- |
0x68 |
-- |
|
---- widen ---- |
0x69 |
-- |
|
---- widen ---- |
0x6a |
-- |
|
i8x16.shl |
0x6b |
:+1: |
@abrown |
i8x16.shr_s |
0x6c |
:+1: |
@abrown |
i8x16.shr_u |
0x6d |
:+1: |
@abrown |
i8x16.add |
0x6e |
:+1: |
:+1: |
i8x16.add_sat_s |
0x6f |
:+1: |
:+1: |
i8x16.add_sat_u |
0x70 |
:+1: |
:+1: |
i8x16.sub |
0x71 |
:+1: |
:+1: |
i8x16.sub_sat_s |
0x72 |
:+1: |
:+1: |
i8x16.sub_sat_u |
0x73 |
:+1: |
:+1: |
---- dot ---- |
0x74 |
-- |
|
---- mul ---- |
0x75 |
:question: |
|
i8x16.min_s |
0x76 |
:+1: |
:+1: |
i8x16.min_u |
0x77 |
:+1: |
:+1: |
i8x16.max_s |
0x78 |
:+1: |
:+1: |
i8x16.max_u |
0x79 |
:+1: |
:+1: |
---- avgr_s ---- |
0x7a |
-- |
|
i8x16.avgr_u |
0x7b |
:+1: |
:+1: |
i16x8 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i16x8.abs |
0x80 |
:+1: |
:+1: |
i16x8.neg |
0x81 |
:+1: |
:+1: |
i16x8.any_true |
0x82 |
:+1: |
:+1: |
i16x8.all_true |
0x83 |
:+1: |
:+1: |
i16x8.bitmask |
0x84 |
:question: |
|
i16x8.narrow_i32x4_s |
0x85 |
:+1: |
|
i16x8.narrow_i32x4_u |
0x86 |
:+1: |
|
i16x8.widen_low_i8x16_s |
0x87 |
:+1: |
|
i16x8.widen_high_i8x16_s |
0x88 |
:+1: |
|
i16x8.widen_low_i8x16_u |
0x89 |
:+1: |
|
i16x8.widen_high_i8x16_u |
0x8a |
:+1: |
|
i16x8.shl |
0x8b |
:+1: |
@abrown |
i16x8.shr_s |
0x8c |
:+1: |
@abrown |
i16x8.shr_u |
0x8d |
:+1: |
@abrown |
i16x8.add |
0x8e |
:+1: |
:+1: |
i16x8.add_sat_s |
0x8f |
:+1: |
:+1: |
i16x8.add_sat_u |
0x90 |
:+1: |
:+1: |
i16x8.sub |
0x91 |
:+1: |
:+1: |
i16x8.sub_sat_s |
0x92 |
:+1: |
:+1: |
i16x8.sub_sat_u |
0x93 |
:+1: |
:+1: |
---- dot ---- |
0x94 |
-- |
|
i16x8.mul |
0x95 |
:+1: |
:+1: |
i16x8.min_s |
0x96 |
:+1: |
:+1: |
i16x8.min_u |
0x97 |
:+1: |
:+1: |
i16x8.max_s |
0x98 |
:+1: |
:+1: |
i16x8.max_u |
0x99 |
:+1: |
:+1: |
---- avgr_s ---- |
0x9a |
-- |
|
i16x8.avgr_u |
0x9b |
:+1: |
:+1: |
i32x4 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i32x4.abs |
0xa0 |
:+1: |
:+1: |
i32x4.neg |
0xa1 |
:+1: |
:+1: |
i32x4.any_true |
0xa2 |
:+1: |
:+1: |
i32x4.all_true |
0xa3 |
:+1: |
:+1: |
i32x4.bitmask |
0xa4 |
:question: |
|
---- narrow ---- |
0xa5 |
-- |
|
---- narrow ---- |
0xa6 |
-- |
|
i32x4.widen_low_i16x8_s |
0xa7 |
:+1: |
|
i32x4.widen_high_i16x8_s |
0xa8 |
:+1: |
|
i32x4.widen_low_i16x8_u |
0xa9 |
:+1: |
|
i32x4.widen_high_i16x8_u |
0xaa |
:+1: |
|
i32x4.shl |
0xab |
:+1: |
@abrown |
i32x4.shr_s |
0xac |
:+1: |
@abrown |
i32x4.shr_u |
0xad |
:+1: |
@abrown |
i32x4.add |
0xae |
:+1: |
:+1: |
---- add_sat ---- |
0xaf |
-- |
|
---- add_sat ---- |
0xb0 |
-- |
|
i32x4.sub |
0xb1 |
:+1: |
:+1: |
---- sub_sat ---- |
0xb2 |
-- |
|
---- sub_sat ---- |
0xb3 |
-- |
|
---- dot ---- |
0xb4 |
-- |
|
i32x4.mul |
0xb5 |
:+1: |
:+1: |
i32x4.min_s |
0xb6 |
:+1: |
:+1: |
i32x4.min_u |
0xb7 |
:+1: |
:+1: |
i32x4.max_s |
0xb8 |
:+1: |
:+1: |
i32x4.max_u |
0xb9 |
:+1: |
:+1: |
---- avgr_s ---- |
0xba |
-- |
|
---- avgr_u ---- |
0xbb |
-- |
|
i64x2 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
---- |
0xc0 |
-- |
|
i64x2.neg |
0xc1 |
:+1: |
|
---- |
0xc2 |
-- |
|
---- |
0xc3 |
-- |
|
---- |
0xc4 |
-- |
|
---- |
0xc5 |
-- |
|
---- |
0xc6 |
-- |
|
---- |
0xc7 |
-- |
|
---- |
0xc8 |
-- |
|
---- |
0xc9 |
-- |
|
---- |
0xca |
-- |
|
i64x2.shl |
0xcb |
:+1: |
@abrown |
i64x2.shr_s |
0xcc |
:+1: |
@abrown |
i64x2.shr_u |
0xcd |
:+1: |
@abrown |
i64x2.add |
0xce |
:+1: |
:+1: |
---- |
0xcf |
-- |
|
---- |
0xd0 |
-- |
|
i64x2.sub |
0xd1 |
:+1: |
:+1: |
---- |
0xd2 |
-- |
|
---- |
0xd3 |
-- |
|
---- |
0xd4 |
-- |
|
i64x2.mul |
0xd5 |
:+1: |
:+1: |
---- |
0xd6 |
-- |
|
---- |
0xd7 |
-- |
|
f32x4 Op |
Opcode |
Old Backend Status |
VCode Status |
f32x4.ceil |
0xd8 |
:question: |
|
f32x4.floor |
0xd9 |
:question: |
|
f32x4.trunc |
0xda |
:question: |
|
f32x4.nearest |
0xdb |
:question: |
|
f32x4.abs |
0xe0 |
:+1: |
:+1: |
f32x4.neg |
0xe1 |
:+1: |
:+1: |
---- round ---- |
0xe2 |
-- |
|
f32x4.sqrt |
0xe3 |
:+1: |
:+1: |
f32x4.add |
0xe4 |
:+1: |
:+1: |
f32x4.sub |
0xe5 |
:+1: |
:+1: |
f32x4.mul |
0xe6 |
:+1: |
:+1: |
f32x4.div |
0xe7 |
:+1: |
:+1: |
f32x4.min |
0xe8 |
:+1: |
:+1: |
f32x4.max |
0xe9 |
:+1: |
:+1: |
f32x4.pmin |
0xea |
:question: |
|
f32x4.pmax |
0xeb |
:question: |
|
f64x2 Op |
Opcode |
Old Backend Status |
VCode Status |
f64x2.ceil |
0xdc |
:question: |
|
f64x2.floor |
0xdd |
:question: |
|
f64x2.trunc |
0xde |
:question: |
|
f64x2.nearest |
0xdf |
:question: |
|
f64x2.abs |
0xec |
:+1: |
:+1: |
f64x2.neg |
0xed |
:+1: |
:+1: |
---- round ---- |
0xee |
-- |
|
f64x2.sqrt |
0xef |
:+1: |
:+1: |
f64x2.add |
0xf0 |
:+1: |
:+1: |
f64x2.sub |
0xf1 |
:+1: |
:+1: |
f64x2.mul |
0xf2 |
:+1: |
:+1: |
f64x2.div |
0xf3 |
:+1: |
:+1: |
f64x2.min |
0xf4 |
:+1: |
:+1: |
f64x2.max |
0xf5 |
:+1: |
:+1: |
f64x2.pmin |
0xf6 |
:question: |
|
f64x2.pmax |
0xf7 |
:question: |
|
Conversion Op |
Opcode |
Old Backend Status |
VCode Status |
i32x4.trunc_sat_f32x4_s |
0xf8 |
:question: |
@jlb6740 |
i32x4.trunc_sat_f32x4_u |
0xf9 |
:question: |
@jlb6740 |
f32x4.convert_i32x4_s |
0xfa |
:+1: |
@jlb6740 |
f32x4.convert_i32x4_u |
0xfb |
:question: |
@jlb6740 |
jlb6740 edited Issue #2272:
Last Update: 10/13/2020
Loads |
Opcode |
Old Backend Status |
VCode Status |
v128.load |
0x00 |
:+1: |
:+1: |
v128.load8x8_s |
0x01 |
:+1: |
-- |
v128.load8x8_u |
0x02 |
:+1: |
-- |
v128.load16x4_s |
0x03 |
:+1: |
-- |
v128.load16x4_u |
0x04 |
:+1: |
-- |
v128.load32x2_s |
0x05 |
:+1: |
-- |
v128.load32x2_u |
0x06 |
:+1: |
-- |
v128.load8_splat |
0x07 |
:+1: |
-- |
v128.load16_splat |
0x08 |
:+1: |
-- |
v128.load32_splat |
0x09 |
:+1: |
-- |
v128.load64_splat |
0x0a |
:+1: |
-- |
Stores |
Opcode |
Old Backend Status |
VCode Status |
v128.store |
0x0b |
:+1: |
:+1: |
Basic operation |
Opcode |
Old Backend Status |
VCode Status |
v128.const |
0x0c |
:+1: |
:+1: |
i8x16.shuffle |
0x0d |
:+1: |
:+1: |
i8x16.swizzle |
0x0e |
:+1: |
:+1: |
Splat operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.splat |
0x0f |
:+1: |
:+1: |
i16x8.splat |
0x10 |
:+1: |
:+1: |
i32x4.splat |
0x11 |
:+1: |
:+1: |
i64x2.splat |
0x12 |
:+1: |
:+1: |
f32x4.splat |
0x13 |
:+1: |
:+1: |
f64x2.splat |
0x14 |
:+1: |
:+1: |
Lane operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.extract_lane_s |
0x15 |
:+1: |
:+1: |
i8x16.extract_lane_u |
0x16 |
:+1: |
:+1: |
i8x16.replace_lane |
0x17 |
:+1: |
:+1: |
i16x8.extract_lane_s |
0x18 |
:+1: |
:+1: |
i16x8.extract_lane_u |
0x19 |
:+1: |
:+1: |
i16x8.replace_lane |
0x1a |
:+1: |
:+1: |
i32x4.extract_lane |
0x1b |
:+1: |
:+1: |
i32x4.replace_lane |
0x1c |
:+1: |
:+1: |
i64x2.extract_lane |
0x1d |
:+1: |
:+1: |
i64x2.replace_lane |
0x1e |
:+1: |
:+1: |
f32x4.extract_lane |
0x1f |
:+1: |
:+1: |
f32x4.replace_lane |
0x20 |
:+1: |
:+1: |
f64x2.extract_lane |
0x21 |
:+1: |
:+1: |
f64x2.replace_lane |
0x22 |
:+1: |
:+1: |
Integer Cmp |
Opcode |
Old Backend Status |
VCode Status |
i8x16.eq |
0x23 |
:+1: |
:+1: |
i8x16.ne |
0x24 |
:+1: |
:+1: |
i8x16.lt_s |
0x25 |
:+1: |
:+1: |
i8x16.lt_u |
0x26 |
:+1: |
:+1: |
i8x16.gt_s |
0x27 |
:+1: |
:+1: |
i8x16.gt_u |
0x28 |
:+1: |
:+1: |
i8x16.le_s |
0x29 |
:+1: |
:+1: |
i8x16.le_u |
0x2a |
:+1: |
:+1: |
i8x16.ge_s |
0x2b |
:+1: |
:+1: |
i8x16.ge_u |
0x2c |
:+1: |
:+1: |
i16x8.eq |
0x2d |
:+1: |
:+1: |
i16x8.ne |
0x2e |
:+1: |
:+1: |
i16x8.lt_s |
0x2f |
:+1: |
:+1: |
i16x8.lt_u |
0x30 |
:+1: |
:+1: |
i16x8.gt_s |
0x31 |
:+1: |
:+1: |
i16x8.gt_u |
0x32 |
:+1: |
:+1: |
i16x8.le_s |
0x33 |
:+1: |
:+1: |
i16x8.le_u |
0x34 |
:+1: |
:+1: |
i16x8.ge_s |
0x35 |
:+1: |
:+1: |
i16x8.ge_u |
0x36 |
:+1: |
:+1: |
i32x4.eq |
0x37 |
:+1: |
:+1: |
i32x4.ne |
0x38 |
:+1: |
:+1: |
i32x4.lt_s |
0x39 |
:+1: |
:+1: |
i32x4.lt_u |
0x3a |
:+1: |
:+1: |
i32x4.gt_s |
0x3b |
:+1: |
:+1: |
i32x4.gt_u |
0x3c |
:+1: |
:+1: |
i32x4.le_s |
0x3d |
:+1: |
:+1: |
i32x4.le_u |
0x3e |
:+1: |
:+1: |
i32x4.ge_s |
0x3f |
:+1: |
:+1: |
i32x4.ge_u |
0x40 |
:+1: |
:+1: |
Float Cmp |
Opcode |
Old Backend Status |
VCode Status |
f32x4.eq |
0x41 |
:+1: |
:+1: |
f32x4.ne |
0x42 |
:+1: |
:+1: |
f32x4.lt |
0x43 |
:+1: |
:+1: |
f32x4.gt |
0x44 |
:+1: |
:+1: |
f32x4.le |
0x45 |
:+1: |
:+1: |
f32x4.ge |
0x46 |
:+1: |
:+1: |
f64x2.eq |
0x47 |
:+1: |
:+1: |
f64x2.ne |
0x48 |
:+1: |
:+1: |
f64x2.lt |
0x49 |
:+1: |
:+1: |
f64x2.gt |
0x4a |
:+1: |
:+1: |
f64x2.le |
0x4b |
:+1: |
:+1: |
f64x2.ge |
0x4c |
:+1: |
:+1: |
v128 Op |
Opcode |
Old Backend Status |
VCode Status |
v128.not |
0x4d |
:+1: |
:+1: |
v128.and |
0x4e |
:+1: |
:+1: |
v128.andnot |
0x4f |
:+1: |
:+1: |
v128.or |
0x50 |
:+1: |
:+1: |
v128.xor |
0x51 |
:+1: |
:+1: |
v128.bitselect |
0x52 |
:+1: |
:+1: |
i8x16 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i8x16.abs |
0x60 |
:+1: |
:+1: |
i8x16.neg |
0x61 |
:+1: |
:+1: |
i8x16.any_true |
0x62 |
:+1: |
:+1: |
i8x16.all_true |
0x63 |
:+1: |
:+1: |
i8x16.bitmask |
0x64 |
:question: |
|
i8x16.narrow_i16x8_s |
0x65 |
:+1: |
|
i8x16.narrow_i16x8_u |
0x66 |
:+1: |
|
---- widen ---- |
0x67 |
-- |
|
---- widen ---- |
0x68 |
-- |
|
---- widen ---- |
0x69 |
-- |
|
---- widen ---- |
0x6a |
-- |
|
i8x16.shl |
0x6b |
:+1: |
@abrown |
i8x16.shr_s |
0x6c |
:+1: |
@abrown |
i8x16.shr_u |
0x6d |
:+1: |
@abrown |
i8x16.add |
0x6e |
:+1: |
:+1: |
i8x16.add_sat_s |
0x6f |
:+1: |
:+1: |
i8x16.add_sat_u |
0x70 |
:+1: |
:+1: |
i8x16.sub |
0x71 |
:+1: |
:+1: |
i8x16.sub_sat_s |
0x72 |
:+1: |
:+1: |
i8x16.sub_sat_u |
0x73 |
:+1: |
:+1: |
---- dot ---- |
0x74 |
-- |
|
---- mul ---- |
0x75 |
:question: |
|
i8x16.min_s |
0x76 |
:+1: |
:+1: |
i8x16.min_u |
0x77 |
:+1: |
:+1: |
i8x16.max_s |
0x78 |
:+1: |
:+1: |
i8x16.max_u |
0x79 |
:+1: |
:+1: |
---- avgr_s ---- |
0x7a |
-- |
|
i8x16.avgr_u |
0x7b |
:+1: |
:+1: |
i16x8 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i16x8.abs |
0x80 |
:+1: |
:+1: |
i16x8.neg |
0x81 |
:+1: |
:+1: |
i16x8.any_true |
0x82 |
:+1: |
:+1: |
i16x8.all_true |
0x83 |
:+1: |
:+1: |
i16x8.bitmask |
0x84 |
:question: |
|
i16x8.narrow_i32x4_s |
0x85 |
:+1: |
|
i16x8.narrow_i32x4_u |
0x86 |
:+1: |
|
i16x8.widen_low_i8x16_s |
0x87 |
:+1: |
|
i16x8.widen_high_i8x16_s |
0x88 |
:+1: |
|
i16x8.widen_low_i8x16_u |
0x89 |
:+1: |
|
i16x8.widen_high_i8x16_u |
0x8a |
:+1: |
|
i16x8.shl |
0x8b |
:+1: |
@abrown |
i16x8.shr_s |
0x8c |
:+1: |
@abrown |
i16x8.shr_u |
0x8d |
:+1: |
@abrown |
i16x8.add |
0x8e |
:+1: |
:+1: |
i16x8.add_sat_s |
0x8f |
:+1: |
:+1: |
i16x8.add_sat_u |
0x90 |
:+1: |
:+1: |
i16x8.sub |
0x91 |
:+1: |
:+1: |
i16x8.sub_sat_s |
0x92 |
:+1: |
:+1: |
i16x8.sub_sat_u |
0x93 |
:+1: |
:+1: |
---- dot ---- |
0x94 |
-- |
|
i16x8.mul |
0x95 |
:+1: |
:+1: |
i16x8.min_s |
0x96 |
:+1: |
:+1: |
i16x8.min_u |
0x97 |
:+1: |
:+1: |
i16x8.max_s |
0x98 |
:+1: |
:+1: |
i16x8.max_u |
0x99 |
:+1: |
:+1: |
---- avgr_s ---- |
0x9a |
-- |
|
i16x8.avgr_u |
0x9b |
:+1: |
:+1: |
i32x4 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i32x4.abs |
0xa0 |
:+1: |
:+1: |
i32x4.neg |
0xa1 |
:+1: |
:+1: |
i32x4.any_true |
0xa2 |
:+1: |
:+1: |
i32x4.all_true |
0xa3 |
:+1: |
:+1: |
i32x4.bitmask |
0xa4 |
:question: |
|
---- narrow ---- |
0xa5 |
-- |
|
---- narrow ---- |
0xa6 |
-- |
|
i32x4.widen_low_i16x8_s |
0xa7 |
:+1: |
|
i32x4.widen_high_i16x8_s |
0xa8 |
:+1: |
|
i32x4.widen_low_i16x8_u |
0xa9 |
:+1: |
|
i32x4.widen_high_i16x8_u |
0xaa |
:+1: |
|
i32x4.shl |
0xab |
:+1: |
@abrown |
i32x4.shr_s |
0xac |
:+1: |
@abrown |
i32x4.shr_u |
0xad |
:+1: |
@abrown |
i32x4.add |
0xae |
:+1: |
:+1: |
---- add_sat ---- |
0xaf |
-- |
|
---- add_sat ---- |
0xb0 |
-- |
|
i32x4.sub |
0xb1 |
:+1: |
:+1: |
---- sub_sat ---- |
0xb2 |
-- |
|
---- sub_sat ---- |
0xb3 |
-- |
|
---- dot ---- |
0xb4 |
-- |
|
i32x4.mul |
0xb5 |
:+1: |
:+1: |
i32x4.min_s |
0xb6 |
:+1: |
:+1: |
i32x4.min_u |
0xb7 |
:+1: |
:+1: |
i32x4.max_s |
0xb8 |
:+1: |
:+1: |
i32x4.max_u |
0xb9 |
:+1: |
:+1: |
---- avgr_s ---- |
0xba |
-- |
|
---- avgr_u ---- |
0xbb |
-- |
|
i64x2 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
---- |
0xc0 |
-- |
|
i64x2.neg |
0xc1 |
:+1: |
|
---- |
0xc2 |
-- |
|
---- |
0xc3 |
-- |
|
---- |
0xc4 |
-- |
|
---- |
0xc5 |
-- |
|
---- |
0xc6 |
-- |
|
---- |
0xc7 |
-- |
|
---- |
0xc8 |
-- |
|
---- |
0xc9 |
-- |
|
---- |
0xca |
-- |
|
i64x2.shl |
0xcb |
:+1: |
@abrown |
i64x2.shr_s |
0xcc |
:+1: |
@abrown |
i64x2.shr_u |
0xcd |
:+1: |
@abrown |
i64x2.add |
0xce |
:+1: |
:+1: |
---- |
0xcf |
-- |
|
---- |
0xd0 |
-- |
|
i64x2.sub |
0xd1 |
:+1: |
:+1: |
---- |
0xd2 |
-- |
|
---- |
0xd3 |
-- |
|
---- |
0xd4 |
-- |
|
i64x2.mul |
0xd5 |
:+1: |
:+1: |
---- |
0xd6 |
-- |
|
---- |
0xd7 |
-- |
|
f32x4 Op |
Opcode |
Old Backend Status |
VCode Status |
f32x4.ceil |
0xd8 |
:question: |
|
f32x4.floor |
0xd9 |
:question: |
|
f32x4.trunc |
0xda |
:question: |
|
f32x4.nearest |
0xdb |
:question: |
|
f32x4.abs |
0xe0 |
:+1: |
:+1: |
f32x4.neg |
0xe1 |
:+1: |
:+1: |
---- round ---- |
0xe2 |
-- |
|
f32x4.sqrt |
0xe3 |
:+1: |
:+1: |
f32x4.add |
0xe4 |
:+1: |
:+1: |
f32x4.sub |
0xe5 |
:+1: |
:+1: |
f32x4.mul |
0xe6 |
:+1: |
:+1: |
f32x4.div |
0xe7 |
:+1: |
:+1: |
f32x4.min |
0xe8 |
:+1: |
:+1: |
f32x4.max |
0xe9 |
:+1: |
:+1: |
f32x4.pmin |
0xea |
:question: |
|
f32x4.pmax |
0xeb |
:question: |
|
f64x2 Op |
Opcode |
Old Backend Status |
VCode Status |
f64x2.ceil |
0xdc |
:question: |
|
f64x2.floor |
0xdd |
:question: |
|
f64x2.trunc |
0xde |
:question: |
|
f64x2.nearest |
0xdf |
:question: |
|
f64x2.abs |
0xec |
:+1: |
:+1: |
f64x2.neg |
0xed |
:+1: |
:+1: |
---- round ---- |
0xee |
-- |
|
f64x2.sqrt |
0xef |
:+1: |
:+1: |
f64x2.add |
0xf0 |
:+1: |
:+1: |
f64x2.sub |
0xf1 |
:+1: |
:+1: |
f64x2.mul |
0xf2 |
:+1: |
:+1: |
f64x2.div |
0xf3 |
:+1: |
:+1: |
f64x2.min |
0xf4 |
:+1: |
:+1: |
f64x2.max |
0xf5 |
:+1: |
:+1: |
f64x2.pmin |
0xf6 |
:question: |
|
f64x2.pmax |
0xf7 |
:question: |
|
Conversion Op |
Opcode |
Old Backend Status |
VCode Status |
i32x4.trunc_sat_f32x4_s |
0xf8 |
:question: |
@jlb6740 |
i32x4.trunc_sat_f32x4_u |
0xf9 |
:question: |
@jlb6740 |
f32x4.convert_i32x4_s |
0xfa |
:+1: |
:+1: |
f32x4.convert_i32x4_u |
0xfb |
:question: |
@jlb6740 |
jlb6740 edited Issue #2272:
Last Update: 10/17/2020
Loads |
Opcode |
Old Backend Status |
VCode Status |
v128.load |
0x00 |
:+1: |
:+1: |
v128.load8x8_s |
0x01 |
:+1: |
-- |
v128.load8x8_u |
0x02 |
:+1: |
-- |
v128.load16x4_s |
0x03 |
:+1: |
-- |
v128.load16x4_u |
0x04 |
:+1: |
-- |
v128.load32x2_s |
0x05 |
:+1: |
-- |
v128.load32x2_u |
0x06 |
:+1: |
-- |
v128.load8_splat |
0x07 |
:+1: |
-- |
v128.load16_splat |
0x08 |
:+1: |
-- |
v128.load32_splat |
0x09 |
:+1: |
-- |
v128.load64_splat |
0x0a |
:+1: |
-- |
Stores |
Opcode |
Old Backend Status |
VCode Status |
v128.store |
0x0b |
:+1: |
:+1: |
Basic operation |
Opcode |
Old Backend Status |
VCode Status |
v128.const |
0x0c |
:+1: |
:+1: |
i8x16.shuffle |
0x0d |
:+1: |
:+1: |
i8x16.swizzle |
0x0e |
:+1: |
:+1: |
Splat operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.splat |
0x0f |
:+1: |
:+1: |
i16x8.splat |
0x10 |
:+1: |
:+1: |
i32x4.splat |
0x11 |
:+1: |
:+1: |
i64x2.splat |
0x12 |
:+1: |
:+1: |
f32x4.splat |
0x13 |
:+1: |
:+1: |
f64x2.splat |
0x14 |
:+1: |
:+1: |
Lane operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.extract_lane_s |
0x15 |
:+1: |
:+1: |
i8x16.extract_lane_u |
0x16 |
:+1: |
:+1: |
i8x16.replace_lane |
0x17 |
:+1: |
:+1: |
i16x8.extract_lane_s |
0x18 |
:+1: |
:+1: |
i16x8.extract_lane_u |
0x19 |
:+1: |
:+1: |
i16x8.replace_lane |
0x1a |
:+1: |
:+1: |
i32x4.extract_lane |
0x1b |
:+1: |
:+1: |
i32x4.replace_lane |
0x1c |
:+1: |
:+1: |
i64x2.extract_lane |
0x1d |
:+1: |
:+1: |
i64x2.replace_lane |
0x1e |
:+1: |
:+1: |
f32x4.extract_lane |
0x1f |
:+1: |
:+1: |
f32x4.replace_lane |
0x20 |
:+1: |
:+1: |
f64x2.extract_lane |
0x21 |
:+1: |
:+1: |
f64x2.replace_lane |
0x22 |
:+1: |
:+1: |
Integer Cmp |
Opcode |
Old Backend Status |
VCode Status |
i8x16.eq |
0x23 |
:+1: |
:+1: |
i8x16.ne |
0x24 |
:+1: |
:+1: |
i8x16.lt_s |
0x25 |
:+1: |
:+1: |
i8x16.lt_u |
0x26 |
:+1: |
:+1: |
i8x16.gt_s |
0x27 |
:+1: |
:+1: |
i8x16.gt_u |
0x28 |
:+1: |
:+1: |
i8x16.le_s |
0x29 |
:+1: |
:+1: |
i8x16.le_u |
0x2a |
:+1: |
:+1: |
i8x16.ge_s |
0x2b |
:+1: |
:+1: |
i8x16.ge_u |
0x2c |
:+1: |
:+1: |
i16x8.eq |
0x2d |
:+1: |
:+1: |
i16x8.ne |
0x2e |
:+1: |
:+1: |
i16x8.lt_s |
0x2f |
:+1: |
:+1: |
i16x8.lt_u |
0x30 |
:+1: |
:+1: |
i16x8.gt_s |
0x31 |
:+1: |
:+1: |
i16x8.gt_u |
0x32 |
:+1: |
:+1: |
i16x8.le_s |
0x33 |
:+1: |
:+1: |
i16x8.le_u |
0x34 |
:+1: |
:+1: |
i16x8.ge_s |
0x35 |
:+1: |
:+1: |
i16x8.ge_u |
0x36 |
:+1: |
:+1: |
i32x4.eq |
0x37 |
:+1: |
:+1: |
i32x4.ne |
0x38 |
:+1: |
:+1: |
i32x4.lt_s |
0x39 |
:+1: |
:+1: |
i32x4.lt_u |
0x3a |
:+1: |
:+1: |
i32x4.gt_s |
0x3b |
:+1: |
:+1: |
i32x4.gt_u |
0x3c |
:+1: |
:+1: |
i32x4.le_s |
0x3d |
:+1: |
:+1: |
i32x4.le_u |
0x3e |
:+1: |
:+1: |
i32x4.ge_s |
0x3f |
:+1: |
:+1: |
i32x4.ge_u |
0x40 |
:+1: |
:+1: |
Float Cmp |
Opcode |
Old Backend Status |
VCode Status |
f32x4.eq |
0x41 |
:+1: |
:+1: |
f32x4.ne |
0x42 |
:+1: |
:+1: |
f32x4.lt |
0x43 |
:+1: |
:+1: |
f32x4.gt |
0x44 |
:+1: |
:+1: |
f32x4.le |
0x45 |
:+1: |
:+1: |
f32x4.ge |
0x46 |
:+1: |
:+1: |
f64x2.eq |
0x47 |
:+1: |
:+1: |
f64x2.ne |
0x48 |
:+1: |
:+1: |
f64x2.lt |
0x49 |
:+1: |
:+1: |
f64x2.gt |
0x4a |
:+1: |
:+1: |
f64x2.le |
0x4b |
:+1: |
:+1: |
f64x2.ge |
0x4c |
:+1: |
:+1: |
v128 Op |
Opcode |
Old Backend Status |
VCode Status |
v128.not |
0x4d |
:+1: |
:+1: |
v128.and |
0x4e |
:+1: |
:+1: |
v128.andnot |
0x4f |
:+1: |
:+1: |
v128.or |
0x50 |
:+1: |
:+1: |
v128.xor |
0x51 |
:+1: |
:+1: |
v128.bitselect |
0x52 |
:+1: |
:+1: |
i8x16 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i8x16.abs |
0x60 |
:+1: |
:+1: |
i8x16.neg |
0x61 |
:+1: |
:+1: |
i8x16.any_true |
0x62 |
:+1: |
:+1: |
i8x16.all_true |
0x63 |
:+1: |
:+1: |
i8x16.bitmask |
0x64 |
:question: |
|
i8x16.narrow_i16x8_s |
0x65 |
:+1: |
|
i8x16.narrow_i16x8_u |
0x66 |
:+1: |
|
---- widen ---- |
0x67 |
-- |
|
---- widen ---- |
0x68 |
-- |
|
---- widen ---- |
0x69 |
-- |
|
---- widen ---- |
0x6a |
-- |
|
i8x16.shl |
0x6b |
:+1: |
@abrown |
i8x16.shr_s |
0x6c |
:+1: |
@abrown |
i8x16.shr_u |
0x6d |
:+1: |
@abrown |
i8x16.add |
0x6e |
:+1: |
:+1: |
i8x16.add_sat_s |
0x6f |
:+1: |
:+1: |
i8x16.add_sat_u |
0x70 |
:+1: |
:+1: |
i8x16.sub |
0x71 |
:+1: |
:+1: |
i8x16.sub_sat_s |
0x72 |
:+1: |
:+1: |
i8x16.sub_sat_u |
0x73 |
:+1: |
:+1: |
---- dot ---- |
0x74 |
-- |
|
---- mul ---- |
0x75 |
:question: |
|
i8x16.min_s |
0x76 |
:+1: |
:+1: |
i8x16.min_u |
0x77 |
:+1: |
:+1: |
i8x16.max_s |
0x78 |
:+1: |
:+1: |
i8x16.max_u |
0x79 |
:+1: |
:+1: |
---- avgr_s ---- |
0x7a |
-- |
|
i8x16.avgr_u |
0x7b |
:+1: |
:+1: |
i16x8 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i16x8.abs |
0x80 |
:+1: |
:+1: |
i16x8.neg |
0x81 |
:+1: |
:+1: |
i16x8.any_true |
0x82 |
:+1: |
:+1: |
i16x8.all_true |
0x83 |
:+1: |
:+1: |
i16x8.bitmask |
0x84 |
:question: |
|
i16x8.narrow_i32x4_s |
0x85 |
:+1: |
|
i16x8.narrow_i32x4_u |
0x86 |
:+1: |
|
i16x8.widen_low_i8x16_s |
0x87 |
:+1: |
|
i16x8.widen_high_i8x16_s |
0x88 |
:+1: |
|
i16x8.widen_low_i8x16_u |
0x89 |
:+1: |
|
i16x8.widen_high_i8x16_u |
0x8a |
:+1: |
|
i16x8.shl |
0x8b |
:+1: |
@abrown |
i16x8.shr_s |
0x8c |
:+1: |
@abrown |
i16x8.shr_u |
0x8d |
:+1: |
@abrown |
i16x8.add |
0x8e |
:+1: |
:+1: |
i16x8.add_sat_s |
0x8f |
:+1: |
:+1: |
i16x8.add_sat_u |
0x90 |
:+1: |
:+1: |
i16x8.sub |
0x91 |
:+1: |
:+1: |
i16x8.sub_sat_s |
0x92 |
:+1: |
:+1: |
i16x8.sub_sat_u |
0x93 |
:+1: |
:+1: |
---- dot ---- |
0x94 |
-- |
|
i16x8.mul |
0x95 |
:+1: |
:+1: |
i16x8.min_s |
0x96 |
:+1: |
:+1: |
i16x8.min_u |
0x97 |
:+1: |
:+1: |
i16x8.max_s |
0x98 |
:+1: |
:+1: |
i16x8.max_u |
0x99 |
:+1: |
:+1: |
---- avgr_s ---- |
0x9a |
-- |
|
i16x8.avgr_u |
0x9b |
:+1: |
:+1: |
i32x4 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i32x4.abs |
0xa0 |
:+1: |
:+1: |
i32x4.neg |
0xa1 |
:+1: |
:+1: |
i32x4.any_true |
0xa2 |
:+1: |
:+1: |
i32x4.all_true |
0xa3 |
:+1: |
:+1: |
i32x4.bitmask |
0xa4 |
:question: |
|
---- narrow ---- |
0xa5 |
-- |
|
---- narrow ---- |
0xa6 |
-- |
|
i32x4.widen_low_i16x8_s |
0xa7 |
:+1: |
|
i32x4.widen_high_i16x8_s |
0xa8 |
:+1: |
|
i32x4.widen_low_i16x8_u |
0xa9 |
:+1: |
|
i32x4.widen_high_i16x8_u |
0xaa |
:+1: |
|
i32x4.shl |
0xab |
:+1: |
@abrown |
i32x4.shr_s |
0xac |
:+1: |
@abrown |
i32x4.shr_u |
0xad |
:+1: |
@abrown |
i32x4.add |
0xae |
:+1: |
:+1: |
---- add_sat ---- |
0xaf |
-- |
|
---- add_sat ---- |
0xb0 |
-- |
|
i32x4.sub |
0xb1 |
:+1: |
:+1: |
---- sub_sat ---- |
0xb2 |
-- |
|
---- sub_sat ---- |
0xb3 |
-- |
|
---- dot ---- |
0xb4 |
-- |
|
i32x4.mul |
0xb5 |
:+1: |
:+1: |
i32x4.min_s |
0xb6 |
:+1: |
:+1: |
i32x4.min_u |
0xb7 |
:+1: |
:+1: |
i32x4.max_s |
0xb8 |
:+1: |
:+1: |
i32x4.max_u |
0xb9 |
:+1: |
:+1: |
---- avgr_s ---- |
0xba |
-- |
|
---- avgr_u ---- |
0xbb |
-- |
|
i64x2 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
---- |
0xc0 |
-- |
|
i64x2.neg |
0xc1 |
:+1: |
|
---- |
0xc2 |
-- |
|
---- |
0xc3 |
-- |
|
---- |
0xc4 |
-- |
|
---- |
0xc5 |
-- |
|
---- |
0xc6 |
-- |
|
---- |
0xc7 |
-- |
|
---- |
0xc8 |
-- |
|
---- |
0xc9 |
-- |
|
---- |
0xca |
-- |
|
i64x2.shl |
0xcb |
:+1: |
@abrown |
i64x2.shr_s |
0xcc |
:+1: |
@abrown |
i64x2.shr_u |
0xcd |
:+1: |
@abrown |
i64x2.add |
0xce |
:+1: |
:+1: |
---- |
0xcf |
-- |
|
---- |
0xd0 |
-- |
|
i64x2.sub |
0xd1 |
:+1: |
:+1: |
---- |
0xd2 |
-- |
|
---- |
0xd3 |
-- |
|
---- |
0xd4 |
-- |
|
i64x2.mul |
0xd5 |
:+1: |
:+1: |
---- |
0xd6 |
-- |
|
---- |
0xd7 |
-- |
|
f32x4 Op |
Opcode |
Old Backend Status |
VCode Status |
f32x4.ceil |
0xd8 |
:question: |
|
f32x4.floor |
0xd9 |
:question: |
|
f32x4.trunc |
0xda |
:question: |
|
f32x4.nearest |
0xdb |
:question: |
|
f32x4.abs |
0xe0 |
:+1: |
:+1: |
f32x4.neg |
0xe1 |
:+1: |
:+1: |
---- round ---- |
0xe2 |
-- |
|
f32x4.sqrt |
0xe3 |
:+1: |
:+1: |
f32x4.add |
0xe4 |
:+1: |
:+1: |
f32x4.sub |
0xe5 |
:+1: |
:+1: |
f32x4.mul |
0xe6 |
:+1: |
:+1: |
f32x4.div |
0xe7 |
:+1: |
:+1: |
f32x4.min |
0xe8 |
:+1: |
:+1: |
f32x4.max |
0xe9 |
:+1: |
:+1: |
f32x4.pmin |
0xea |
:question: |
|
f32x4.pmax |
0xeb |
:question: |
|
f64x2 Op |
Opcode |
Old Backend Status |
VCode Status |
f64x2.ceil |
0xdc |
:question: |
|
f64x2.floor |
0xdd |
:question: |
|
f64x2.trunc |
0xde |
:question: |
|
f64x2.nearest |
0xdf |
:question: |
|
f64x2.abs |
0xec |
:+1: |
:+1: |
f64x2.neg |
0xed |
:+1: |
:+1: |
---- round ---- |
0xee |
-- |
|
f64x2.sqrt |
0xef |
:+1: |
:+1: |
f64x2.add |
0xf0 |
:+1: |
:+1: |
f64x2.sub |
0xf1 |
:+1: |
:+1: |
f64x2.mul |
0xf2 |
:+1: |
:+1: |
f64x2.div |
0xf3 |
:+1: |
:+1: |
f64x2.min |
0xf4 |
:+1: |
:+1: |
f64x2.max |
0xf5 |
:+1: |
:+1: |
f64x2.pmin |
0xf6 |
:question: |
|
f64x2.pmax |
0xf7 |
:question: |
|
Conversion Op |
Opcode |
Old Backend Status |
VCode Status |
i32x4.trunc_sat_f32x4_s |
0xf8 |
:question: |
@jlb6740 |
i32x4.trunc_sat_f32x4_u |
0xf9 |
:question: |
@jlb6740 |
f32x4.convert_i32x4_s |
0xfa |
:+1: |
:+1: |
f32x4.convert_i32x4_u |
0xfb |
:question: |
@jlb6740 |
jlb6740 edited Issue #2272:
Last Update: 10/17/2020
Loads |
Opcode |
Old Backend Status |
VCode Status |
v128.load |
0x00 |
:+1: |
:+1: |
v128.load8x8_s |
0x01 |
:+1: |
-- |
v128.load8x8_u |
0x02 |
:+1: |
-- |
v128.load16x4_s |
0x03 |
:+1: |
-- |
v128.load16x4_u |
0x04 |
:+1: |
-- |
v128.load32x2_s |
0x05 |
:+1: |
-- |
v128.load32x2_u |
0x06 |
:+1: |
-- |
v128.load8_splat |
0x07 |
:+1: |
-- |
v128.load16_splat |
0x08 |
:+1: |
-- |
v128.load32_splat |
0x09 |
:+1: |
-- |
v128.load64_splat |
0x0a |
:+1: |
-- |
Stores |
Opcode |
Old Backend Status |
VCode Status |
v128.store |
0x0b |
:+1: |
:+1: |
Basic operation |
Opcode |
Old Backend Status |
VCode Status |
v128.const |
0x0c |
:+1: |
:+1: |
i8x16.shuffle |
0x0d |
:+1: |
:+1: |
i8x16.swizzle |
0x0e |
:+1: |
:+1: |
Splat operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.splat |
0x0f |
:+1: |
:+1: |
i16x8.splat |
0x10 |
:+1: |
:+1: |
i32x4.splat |
0x11 |
:+1: |
:+1: |
i64x2.splat |
0x12 |
:+1: |
:+1: |
f32x4.splat |
0x13 |
:+1: |
:+1: |
f64x2.splat |
0x14 |
:+1: |
:+1: |
Lane operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.extract_lane_s |
0x15 |
:+1: |
:+1: |
i8x16.extract_lane_u |
0x16 |
:+1: |
:+1: |
i8x16.replace_lane |
0x17 |
:+1: |
:+1: |
i16x8.extract_lane_s |
0x18 |
:+1: |
:+1: |
i16x8.extract_lane_u |
0x19 |
:+1: |
:+1: |
i16x8.replace_lane |
0x1a |
:+1: |
:+1: |
i32x4.extract_lane |
0x1b |
:+1: |
:+1: |
i32x4.replace_lane |
0x1c |
:+1: |
:+1: |
i64x2.extract_lane |
0x1d |
:+1: |
:+1: |
i64x2.replace_lane |
0x1e |
:+1: |
:+1: |
f32x4.extract_lane |
0x1f |
:+1: |
:+1: |
f32x4.replace_lane |
0x20 |
:+1: |
:+1: |
f64x2.extract_lane |
0x21 |
:+1: |
:+1: |
f64x2.replace_lane |
0x22 |
:+1: |
:+1: |
Integer Cmp |
Opcode |
Old Backend Status |
VCode Status |
i8x16.eq |
0x23 |
:+1: |
:+1: |
i8x16.ne |
0x24 |
:+1: |
:+1: |
i8x16.lt_s |
0x25 |
:+1: |
:+1: |
i8x16.lt_u |
0x26 |
:+1: |
:+1: |
i8x16.gt_s |
0x27 |
:+1: |
:+1: |
i8x16.gt_u |
0x28 |
:+1: |
:+1: |
i8x16.le_s |
0x29 |
:+1: |
:+1: |
i8x16.le_u |
0x2a |
:+1: |
:+1: |
i8x16.ge_s |
0x2b |
:+1: |
:+1: |
i8x16.ge_u |
0x2c |
:+1: |
:+1: |
i16x8.eq |
0x2d |
:+1: |
:+1: |
i16x8.ne |
0x2e |
:+1: |
:+1: |
i16x8.lt_s |
0x2f |
:+1: |
:+1: |
i16x8.lt_u |
0x30 |
:+1: |
:+1: |
i16x8.gt_s |
0x31 |
:+1: |
:+1: |
i16x8.gt_u |
0x32 |
:+1: |
:+1: |
i16x8.le_s |
0x33 |
:+1: |
:+1: |
i16x8.le_u |
0x34 |
:+1: |
:+1: |
i16x8.ge_s |
0x35 |
:+1: |
:+1: |
i16x8.ge_u |
0x36 |
:+1: |
:+1: |
i32x4.eq |
0x37 |
:+1: |
:+1: |
i32x4.ne |
0x38 |
:+1: |
:+1: |
i32x4.lt_s |
0x39 |
:+1: |
:+1: |
i32x4.lt_u |
0x3a |
:+1: |
:+1: |
i32x4.gt_s |
0x3b |
:+1: |
:+1: |
i32x4.gt_u |
0x3c |
:+1: |
:+1: |
i32x4.le_s |
0x3d |
:+1: |
:+1: |
i32x4.le_u |
0x3e |
:+1: |
:+1: |
i32x4.ge_s |
0x3f |
:+1: |
:+1: |
i32x4.ge_u |
0x40 |
:+1: |
:+1: |
Float Cmp |
Opcode |
Old Backend Status |
VCode Status |
f32x4.eq |
0x41 |
:+1: |
:+1: |
f32x4.ne |
0x42 |
:+1: |
:+1: |
f32x4.lt |
0x43 |
:+1: |
:+1: |
f32x4.gt |
0x44 |
:+1: |
:+1: |
f32x4.le |
0x45 |
:+1: |
:+1: |
f32x4.ge |
0x46 |
:+1: |
:+1: |
f64x2.eq |
0x47 |
:+1: |
:+1: |
f64x2.ne |
0x48 |
:+1: |
:+1: |
f64x2.lt |
0x49 |
:+1: |
:+1: |
f64x2.gt |
0x4a |
:+1: |
:+1: |
f64x2.le |
0x4b |
:+1: |
:+1: |
f64x2.ge |
0x4c |
:+1: |
:+1: |
v128 Op |
Opcode |
Old Backend Status |
VCode Status |
v128.not |
0x4d |
:+1: |
:+1: |
v128.and |
0x4e |
:+1: |
:+1: |
v128.andnot |
0x4f |
:+1: |
:+1: |
v128.or |
0x50 |
:+1: |
:+1: |
v128.xor |
0x51 |
:+1: |
:+1: |
v128.bitselect |
0x52 |
:+1: |
:+1: |
i8x16 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i8x16.abs |
0x60 |
:+1: |
:+1: |
i8x16.neg |
0x61 |
:+1: |
:+1: |
i8x16.any_true |
0x62 |
:+1: |
:+1: |
i8x16.all_true |
0x63 |
:+1: |
:+1: |
i8x16.bitmask |
0x64 |
:question: |
|
i8x16.narrow_i16x8_s |
0x65 |
:+1: |
|
i8x16.narrow_i16x8_u |
0x66 |
:+1: |
|
---- widen ---- |
0x67 |
-- |
|
---- widen ---- |
0x68 |
-- |
|
---- widen ---- |
0x69 |
-- |
|
---- widen ---- |
0x6a |
-- |
|
i8x16.shl |
0x6b |
:+1: |
@abrown |
i8x16.shr_s |
0x6c |
:+1: |
@abrown |
i8x16.shr_u |
0x6d |
:+1: |
@abrown |
i8x16.add |
0x6e |
:+1: |
:+1: |
i8x16.add_sat_s |
0x6f |
:+1: |
:+1: |
i8x16.add_sat_u |
0x70 |
:+1: |
:+1: |
i8x16.sub |
0x71 |
:+1: |
:+1: |
i8x16.sub_sat_s |
0x72 |
:+1: |
:+1: |
i8x16.sub_sat_u |
0x73 |
:+1: |
:+1: |
---- dot ---- |
0x74 |
-- |
|
---- mul ---- |
0x75 |
:question: |
|
i8x16.min_s |
0x76 |
:+1: |
:+1: |
i8x16.min_u |
0x77 |
:+1: |
:+1: |
i8x16.max_s |
0x78 |
:+1: |
:+1: |
i8x16.max_u |
0x79 |
:+1: |
:+1: |
---- avgr_s ---- |
0x7a |
-- |
|
i8x16.avgr_u |
0x7b |
:+1: |
:+1: |
i16x8 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i16x8.abs |
0x80 |
:+1: |
:+1: |
i16x8.neg |
0x81 |
:+1: |
:+1: |
i16x8.any_true |
0x82 |
:+1: |
:+1: |
i16x8.all_true |
0x83 |
:+1: |
:+1: |
i16x8.bitmask |
0x84 |
:question: |
|
i16x8.narrow_i32x4_s |
0x85 |
:+1: |
|
i16x8.narrow_i32x4_u |
0x86 |
:+1: |
|
i16x8.widen_low_i8x16_s |
0x87 |
:+1: |
|
i16x8.widen_high_i8x16_s |
0x88 |
:+1: |
|
i16x8.widen_low_i8x16_u |
0x89 |
:+1: |
|
i16x8.widen_high_i8x16_u |
0x8a |
:+1: |
|
i16x8.shl |
0x8b |
:+1: |
@abrown |
i16x8.shr_s |
0x8c |
:+1: |
@abrown |
i16x8.shr_u |
0x8d |
:+1: |
@abrown |
i16x8.add |
0x8e |
:+1: |
:+1: |
i16x8.add_sat_s |
0x8f |
:+1: |
:+1: |
i16x8.add_sat_u |
0x90 |
:+1: |
:+1: |
i16x8.sub |
0x91 |
:+1: |
:+1: |
i16x8.sub_sat_s |
0x92 |
:+1: |
:+1: |
i16x8.sub_sat_u |
0x93 |
:+1: |
:+1: |
---- dot ---- |
0x94 |
-- |
|
i16x8.mul |
0x95 |
:+1: |
:+1: |
i16x8.min_s |
0x96 |
:+1: |
:+1: |
i16x8.min_u |
0x97 |
:+1: |
:+1: |
i16x8.max_s |
0x98 |
:+1: |
:+1: |
i16x8.max_u |
0x99 |
:+1: |
:+1: |
---- avgr_s ---- |
0x9a |
-- |
|
i16x8.avgr_u |
0x9b |
:+1: |
:+1: |
i32x4 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i32x4.abs |
0xa0 |
:+1: |
:+1: |
i32x4.neg |
0xa1 |
:+1: |
:+1: |
i32x4.any_true |
0xa2 |
:+1: |
:+1: |
i32x4.all_true |
0xa3 |
:+1: |
:+1: |
i32x4.bitmask |
0xa4 |
:question: |
|
---- narrow ---- |
0xa5 |
-- |
|
---- narrow ---- |
0xa6 |
-- |
|
i32x4.widen_low_i16x8_s |
0xa7 |
:+1: |
|
i32x4.widen_high_i16x8_s |
0xa8 |
:+1: |
|
i32x4.widen_low_i16x8_u |
0xa9 |
:+1: |
|
i32x4.widen_high_i16x8_u |
0xaa |
:+1: |
|
i32x4.shl |
0xab |
:+1: |
@abrown |
i32x4.shr_s |
0xac |
:+1: |
@abrown |
i32x4.shr_u |
0xad |
:+1: |
@abrown |
i32x4.add |
0xae |
:+1: |
:+1: |
---- add_sat ---- |
0xaf |
-- |
|
---- add_sat ---- |
0xb0 |
-- |
|
i32x4.sub |
0xb1 |
:+1: |
:+1: |
---- sub_sat ---- |
0xb2 |
-- |
|
---- sub_sat ---- |
0xb3 |
-- |
|
---- dot ---- |
0xb4 |
-- |
|
i32x4.mul |
0xb5 |
:+1: |
:+1: |
i32x4.min_s |
0xb6 |
:+1: |
:+1: |
i32x4.min_u |
0xb7 |
:+1: |
:+1: |
i32x4.max_s |
0xb8 |
:+1: |
:+1: |
i32x4.max_u |
0xb9 |
:+1: |
:+1: |
---- avgr_s ---- |
0xba |
-- |
|
---- avgr_u ---- |
0xbb |
-- |
|
i64x2 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
---- |
0xc0 |
-- |
|
i64x2.neg |
0xc1 |
:+1: |
|
---- |
0xc2 |
-- |
|
---- |
0xc3 |
-- |
|
---- |
0xc4 |
-- |
|
---- |
0xc5 |
-- |
|
---- |
0xc6 |
-- |
|
---- |
0xc7 |
-- |
|
---- |
0xc8 |
-- |
|
---- |
0xc9 |
-- |
|
---- |
0xca |
-- |
|
i64x2.shl |
0xcb |
:+1: |
@abrown |
i64x2.shr_s |
0xcc |
:+1: |
@abrown |
i64x2.shr_u |
0xcd |
:+1: |
@abrown |
i64x2.add |
0xce |
:+1: |
:+1: |
---- |
0xcf |
-- |
|
---- |
0xd0 |
-- |
|
i64x2.sub |
0xd1 |
:+1: |
:+1: |
---- |
0xd2 |
-- |
|
---- |
0xd3 |
-- |
|
---- |
0xd4 |
-- |
|
i64x2.mul |
0xd5 |
:+1: |
:+1: |
---- |
0xd6 |
-- |
|
---- |
0xd7 |
-- |
|
f32x4 Op |
Opcode |
Old Backend Status |
VCode Status |
f32x4.ceil |
0xd8 |
:question: |
|
f32x4.floor |
0xd9 |
:question: |
|
f32x4.trunc |
0xda |
:question: |
|
f32x4.nearest |
0xdb |
:question: |
|
f32x4.abs |
0xe0 |
:+1: |
:+1: |
f32x4.neg |
0xe1 |
:+1: |
:+1: |
---- round ---- |
0xe2 |
-- |
|
f32x4.sqrt |
0xe3 |
:+1: |
:+1: |
f32x4.add |
0xe4 |
:+1: |
:+1: |
f32x4.sub |
0xe5 |
:+1: |
:+1: |
f32x4.mul |
0xe6 |
:+1: |
:+1: |
f32x4.div |
0xe7 |
:+1: |
:+1: |
f32x4.min |
0xe8 |
:+1: |
:+1: |
f32x4.max |
0xe9 |
:+1: |
:+1: |
f32x4.pmin |
0xea |
:question: |
:+1: |
f32x4.pmax |
0xeb |
:question: |
:+1: |
f64x2 Op |
Opcode |
Old Backend Status |
VCode Status |
f64x2.ceil |
0xdc |
:question: |
|
f64x2.floor |
0xdd |
:question: |
|
f64x2.trunc |
0xde |
:question: |
|
f64x2.nearest |
0xdf |
:question: |
|
f64x2.abs |
0xec |
:+1: |
:+1: |
f64x2.neg |
0xed |
:+1: |
:+1: |
---- round ---- |
0xee |
-- |
|
f64x2.sqrt |
0xef |
:+1: |
:+1: |
f64x2.add |
0xf0 |
:+1: |
:+1: |
f64x2.sub |
0xf1 |
:+1: |
:+1: |
f64x2.mul |
0xf2 |
:+1: |
:+1: |
f64x2.div |
0xf3 |
:+1: |
:+1: |
f64x2.min |
0xf4 |
:+1: |
:+1: |
f64x2.max |
0xf5 |
:+1: |
:+1: |
f64x2.pmin |
0xf6 |
:question: |
|
f64x2.pmax |
0xf7 |
:question: |
|
Conversion Op |
Opcode |
Old Backend Status |
VCode Status |
i32x4.trunc_sat_f32x4_s |
0xf8 |
:question: |
:+1: |
i32x4.trunc_sat_f32x4_u |
0xf9 |
:question: |
@jlb6740 |
f32x4.convert_i32x4_s |
0xfa |
:+1: |
:+1: |
f32x4.convert_i32x4_u |
0xfb |
:question: |
:+1: |
jlb6740 edited Issue #2272:
Last Update: 10/28/2020
Loads |
Opcode |
Old Backend Status |
VCode Status |
v128.load |
0x00 |
:+1: |
:+1: |
v128.load8x8_s |
0x01 |
:+1: |
-- |
v128.load8x8_u |
0x02 |
:+1: |
-- |
v128.load16x4_s |
0x03 |
:+1: |
-- |
v128.load16x4_u |
0x04 |
:+1: |
-- |
v128.load32x2_s |
0x05 |
:+1: |
-- |
v128.load32x2_u |
0x06 |
:+1: |
-- |
v128.load8_splat |
0x07 |
:+1: |
-- |
v128.load16_splat |
0x08 |
:+1: |
-- |
v128.load32_splat |
0x09 |
:+1: |
-- |
v128.load64_splat |
0x0a |
:+1: |
-- |
Stores |
Opcode |
Old Backend Status |
VCode Status |
v128.store |
0x0b |
:+1: |
:+1: |
Basic operation |
Opcode |
Old Backend Status |
VCode Status |
v128.const |
0x0c |
:+1: |
:+1: |
i8x16.shuffle |
0x0d |
:+1: |
:+1: |
i8x16.swizzle |
0x0e |
:+1: |
:+1: |
Splat operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.splat |
0x0f |
:+1: |
:+1: |
i16x8.splat |
0x10 |
:+1: |
:+1: |
i32x4.splat |
0x11 |
:+1: |
:+1: |
i64x2.splat |
0x12 |
:+1: |
:+1: |
f32x4.splat |
0x13 |
:+1: |
:+1: |
f64x2.splat |
0x14 |
:+1: |
:+1: |
Lane operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.extract_lane_s |
0x15 |
:+1: |
:+1: |
i8x16.extract_lane_u |
0x16 |
:+1: |
:+1: |
i8x16.replace_lane |
0x17 |
:+1: |
:+1: |
i16x8.extract_lane_s |
0x18 |
:+1: |
:+1: |
i16x8.extract_lane_u |
0x19 |
:+1: |
:+1: |
i16x8.replace_lane |
0x1a |
:+1: |
:+1: |
i32x4.extract_lane |
0x1b |
:+1: |
:+1: |
i32x4.replace_lane |
0x1c |
:+1: |
:+1: |
i64x2.extract_lane |
0x1d |
:+1: |
:+1: |
i64x2.replace_lane |
0x1e |
:+1: |
:+1: |
f32x4.extract_lane |
0x1f |
:+1: |
:+1: |
f32x4.replace_lane |
0x20 |
:+1: |
:+1: |
f64x2.extract_lane |
0x21 |
:+1: |
:+1: |
f64x2.replace_lane |
0x22 |
:+1: |
:+1: |
Integer Cmp |
Opcode |
Old Backend Status |
VCode Status |
i8x16.eq |
0x23 |
:+1: |
:+1: |
i8x16.ne |
0x24 |
:+1: |
:+1: |
i8x16.lt_s |
0x25 |
:+1: |
:+1: |
i8x16.lt_u |
0x26 |
:+1: |
:+1: |
i8x16.gt_s |
0x27 |
:+1: |
:+1: |
i8x16.gt_u |
0x28 |
:+1: |
:+1: |
i8x16.le_s |
0x29 |
:+1: |
:+1: |
i8x16.le_u |
0x2a |
:+1: |
:+1: |
i8x16.ge_s |
0x2b |
:+1: |
:+1: |
i8x16.ge_u |
0x2c |
:+1: |
:+1: |
i16x8.eq |
0x2d |
:+1: |
:+1: |
i16x8.ne |
0x2e |
:+1: |
:+1: |
i16x8.lt_s |
0x2f |
:+1: |
:+1: |
i16x8.lt_u |
0x30 |
:+1: |
:+1: |
i16x8.gt_s |
0x31 |
:+1: |
:+1: |
i16x8.gt_u |
0x32 |
:+1: |
:+1: |
i16x8.le_s |
0x33 |
:+1: |
:+1: |
i16x8.le_u |
0x34 |
:+1: |
:+1: |
i16x8.ge_s |
0x35 |
:+1: |
:+1: |
i16x8.ge_u |
0x36 |
:+1: |
:+1: |
i32x4.eq |
0x37 |
:+1: |
:+1: |
i32x4.ne |
0x38 |
:+1: |
:+1: |
i32x4.lt_s |
0x39 |
:+1: |
:+1: |
i32x4.lt_u |
0x3a |
:+1: |
:+1: |
i32x4.gt_s |
0x3b |
:+1: |
:+1: |
i32x4.gt_u |
0x3c |
:+1: |
:+1: |
i32x4.le_s |
0x3d |
:+1: |
:+1: |
i32x4.le_u |
0x3e |
:+1: |
:+1: |
i32x4.ge_s |
0x3f |
:+1: |
:+1: |
i32x4.ge_u |
0x40 |
:+1: |
:+1: |
Float Cmp |
Opcode |
Old Backend Status |
VCode Status |
f32x4.eq |
0x41 |
:+1: |
:+1: |
f32x4.ne |
0x42 |
:+1: |
:+1: |
f32x4.lt |
0x43 |
:+1: |
:+1: |
f32x4.gt |
0x44 |
:+1: |
:+1: |
f32x4.le |
0x45 |
:+1: |
:+1: |
f32x4.ge |
0x46 |
:+1: |
:+1: |
f64x2.eq |
0x47 |
:+1: |
:+1: |
f64x2.ne |
0x48 |
:+1: |
:+1: |
f64x2.lt |
0x49 |
:+1: |
:+1: |
f64x2.gt |
0x4a |
:+1: |
:+1: |
f64x2.le |
0x4b |
:+1: |
:+1: |
f64x2.ge |
0x4c |
:+1: |
:+1: |
v128 Op |
Opcode |
Old Backend Status |
VCode Status |
v128.not |
0x4d |
:+1: |
:+1: |
v128.and |
0x4e |
:+1: |
:+1: |
v128.andnot |
0x4f |
:+1: |
:+1: |
v128.or |
0x50 |
:+1: |
:+1: |
v128.xor |
0x51 |
:+1: |
:+1: |
v128.bitselect |
0x52 |
:+1: |
:+1: |
i8x16 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i8x16.abs |
0x60 |
:+1: |
:+1: |
i8x16.neg |
0x61 |
:+1: |
:+1: |
i8x16.any_true |
0x62 |
:+1: |
:+1: |
i8x16.all_true |
0x63 |
:+1: |
:+1: |
i8x16.bitmask |
0x64 |
:question: |
|
i8x16.narrow_i16x8_s |
0x65 |
:+1: |
|
i8x16.narrow_i16x8_u |
0x66 |
:+1: |
|
---- widen ---- |
0x67 |
-- |
|
---- widen ---- |
0x68 |
-- |
|
---- widen ---- |
0x69 |
-- |
|
---- widen ---- |
0x6a |
-- |
|
i8x16.shl |
0x6b |
:+1: |
@abrown |
i8x16.shr_s |
0x6c |
:+1: |
@abrown |
i8x16.shr_u |
0x6d |
:+1: |
@abrown |
i8x16.add |
0x6e |
:+1: |
:+1: |
i8x16.add_sat_s |
0x6f |
:+1: |
:+1: |
i8x16.add_sat_u |
0x70 |
:+1: |
:+1: |
i8x16.sub |
0x71 |
:+1: |
:+1: |
i8x16.sub_sat_s |
0x72 |
:+1: |
:+1: |
i8x16.sub_sat_u |
0x73 |
:+1: |
:+1: |
---- dot ---- |
0x74 |
-- |
|
---- mul ---- |
0x75 |
:question: |
|
i8x16.min_s |
0x76 |
:+1: |
:+1: |
i8x16.min_u |
0x77 |
:+1: |
:+1: |
i8x16.max_s |
0x78 |
:+1: |
:+1: |
i8x16.max_u |
0x79 |
:+1: |
:+1: |
---- avgr_s ---- |
0x7a |
-- |
|
i8x16.avgr_u |
0x7b |
:+1: |
:+1: |
i16x8 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i16x8.abs |
0x80 |
:+1: |
:+1: |
i16x8.neg |
0x81 |
:+1: |
:+1: |
i16x8.any_true |
0x82 |
:+1: |
:+1: |
i16x8.all_true |
0x83 |
:+1: |
:+1: |
i16x8.bitmask |
0x84 |
:question: |
|
i16x8.narrow_i32x4_s |
0x85 |
:+1: |
|
i16x8.narrow_i32x4_u |
0x86 |
:+1: |
|
i16x8.widen_low_i8x16_s |
0x87 |
:+1: |
|
i16x8.widen_high_i8x16_s |
0x88 |
:+1: |
|
i16x8.widen_low_i8x16_u |
0x89 |
:+1: |
|
i16x8.widen_high_i8x16_u |
0x8a |
:+1: |
|
i16x8.shl |
0x8b |
:+1: |
@abrown |
i16x8.shr_s |
0x8c |
:+1: |
@abrown |
i16x8.shr_u |
0x8d |
:+1: |
@abrown |
i16x8.add |
0x8e |
:+1: |
:+1: |
i16x8.add_sat_s |
0x8f |
:+1: |
:+1: |
i16x8.add_sat_u |
0x90 |
:+1: |
:+1: |
i16x8.sub |
0x91 |
:+1: |
:+1: |
i16x8.sub_sat_s |
0x92 |
:+1: |
:+1: |
i16x8.sub_sat_u |
0x93 |
:+1: |
:+1: |
---- dot ---- |
0x94 |
-- |
|
i16x8.mul |
0x95 |
:+1: |
:+1: |
i16x8.min_s |
0x96 |
:+1: |
:+1: |
i16x8.min_u |
0x97 |
:+1: |
:+1: |
i16x8.max_s |
0x98 |
:+1: |
:+1: |
i16x8.max_u |
0x99 |
:+1: |
:+1: |
---- avgr_s ---- |
0x9a |
-- |
|
i16x8.avgr_u |
0x9b |
:+1: |
:+1: |
i32x4 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i32x4.abs |
0xa0 |
:+1: |
:+1: |
i32x4.neg |
0xa1 |
:+1: |
:+1: |
i32x4.any_true |
0xa2 |
:+1: |
:+1: |
i32x4.all_true |
0xa3 |
:+1: |
:+1: |
i32x4.bitmask |
0xa4 |
:question: |
|
---- narrow ---- |
0xa5 |
-- |
|
---- narrow ---- |
0xa6 |
-- |
|
i32x4.widen_low_i16x8_s |
0xa7 |
:+1: |
|
i32x4.widen_high_i16x8_s |
0xa8 |
:+1: |
|
i32x4.widen_low_i16x8_u |
0xa9 |
:+1: |
|
i32x4.widen_high_i16x8_u |
0xaa |
:+1: |
|
i32x4.shl |
0xab |
:+1: |
@abrown |
i32x4.shr_s |
0xac |
:+1: |
@abrown |
i32x4.shr_u |
0xad |
:+1: |
@abrown |
i32x4.add |
0xae |
:+1: |
:+1: |
---- add_sat ---- |
0xaf |
-- |
|
---- add_sat ---- |
0xb0 |
-- |
|
i32x4.sub |
0xb1 |
:+1: |
:+1: |
---- sub_sat ---- |
0xb2 |
-- |
|
---- sub_sat ---- |
0xb3 |
-- |
|
---- dot ---- |
0xb4 |
-- |
|
i32x4.mul |
0xb5 |
:+1: |
:+1: |
i32x4.min_s |
0xb6 |
:+1: |
:+1: |
i32x4.min_u |
0xb7 |
:+1: |
:+1: |
i32x4.max_s |
0xb8 |
:+1: |
:+1: |
i32x4.max_u |
0xb9 |
:+1: |
:+1: |
---- avgr_s ---- |
0xba |
-- |
|
---- avgr_u ---- |
0xbb |
-- |
|
i64x2 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
---- |
0xc0 |
-- |
|
i64x2.neg |
0xc1 |
:+1: |
|
---- |
0xc2 |
-- |
|
---- |
0xc3 |
-- |
|
---- |
0xc4 |
-- |
|
---- |
0xc5 |
-- |
|
---- |
0xc6 |
-- |
|
---- |
0xc7 |
-- |
|
---- |
0xc8 |
-- |
|
---- |
0xc9 |
-- |
|
---- |
0xca |
-- |
|
i64x2.shl |
0xcb |
:+1: |
@abrown |
i64x2.shr_s |
0xcc |
:+1: |
@abrown |
i64x2.shr_u |
0xcd |
:+1: |
@abrown |
i64x2.add |
0xce |
:+1: |
:+1: |
---- |
0xcf |
-- |
|
---- |
0xd0 |
-- |
|
i64x2.sub |
0xd1 |
:+1: |
:+1: |
---- |
0xd2 |
-- |
|
---- |
0xd3 |
-- |
|
---- |
0xd4 |
-- |
|
i64x2.mul |
0xd5 |
:+1: |
:+1: |
---- |
0xd6 |
-- |
|
---- |
0xd7 |
-- |
|
f32x4 Op |
Opcode |
Old Backend Status |
VCode Status |
f32x4.ceil |
0xd8 |
:question: |
@jlb6740 |
f32x4.floor |
0xd9 |
:question: |
@jlb6740 |
f32x4.trunc |
0xda |
:question: |
@jlb6740 |
f32x4.nearest |
0xdb |
:question: |
@jlb6740 |
f32x4.abs |
0xe0 |
:+1: |
:+1: |
f32x4.neg |
0xe1 |
:+1: |
:+1: |
---- round ---- |
0xe2 |
-- |
|
f32x4.sqrt |
0xe3 |
:+1: |
:+1: |
f32x4.add |
0xe4 |
:+1: |
:+1: |
f32x4.sub |
0xe5 |
:+1: |
:+1: |
f32x4.mul |
0xe6 |
:+1: |
:+1: |
f32x4.div |
0xe7 |
:+1: |
:+1: |
f32x4.min |
0xe8 |
:+1: |
:+1: |
f32x4.max |
0xe9 |
:+1: |
:+1: |
f32x4.pmin |
0xea |
:question: |
:+1: |
f32x4.pmax |
0xeb |
:question: |
:+1: |
f64x2 Op |
Opcode |
Old Backend Status |
VCode Status |
f64x2.ceil |
0xdc |
:question: |
@jlb6740 |
f64x2.floor |
0xdd |
:question: |
@jlb6740 |
f64x2.trunc |
0xde |
:question: |
@jlb6740 |
f64x2.nearest |
0xdf |
:question: |
@jlb6740 |
f64x2.abs |
0xec |
:+1: |
:+1: |
f64x2.neg |
0xed |
:+1: |
:+1: |
---- round ---- |
0xee |
-- |
|
f64x2.sqrt |
0xef |
:+1: |
:+1: |
f64x2.add |
0xf0 |
:+1: |
:+1: |
f64x2.sub |
0xf1 |
:+1: |
:+1: |
f64x2.mul |
0xf2 |
:+1: |
:+1: |
f64x2.div |
0xf3 |
:+1: |
:+1: |
f64x2.min |
0xf4 |
:+1: |
:+1: |
f64x2.max |
0xf5 |
:+1: |
:+1: |
f64x2.pmin |
0xf6 |
:question: |
:+1: |
f64x2.pmax |
0xf7 |
:question: |
:+1: |
Conversion Op |
Opcode |
Old Backend Status |
VCode Status |
i32x4.trunc_sat_f32x4_s |
0xf8 |
:question: |
:+1: |
i32x4.trunc_sat_f32x4_u |
0xf9 |
:question: |
@jlb6740 |
f32x4.convert_i32x4_s |
0xfa |
:+1: |
:+1: |
f32x4.convert_i32x4_u |
0xfb |
:question: |
:+1: |
abrown edited Issue #2272:
Last Update: 10/28/2020
Loads |
Opcode |
Old Backend Status |
VCode Status |
v128.load |
0x00 |
:+1: |
:+1: |
v128.load8x8_s |
0x01 |
:+1: |
-- |
v128.load8x8_u |
0x02 |
:+1: |
-- |
v128.load16x4_s |
0x03 |
:+1: |
-- |
v128.load16x4_u |
0x04 |
:+1: |
-- |
v128.load32x2_s |
0x05 |
:+1: |
-- |
v128.load32x2_u |
0x06 |
:+1: |
-- |
v128.load8_splat |
0x07 |
:+1: |
-- |
v128.load16_splat |
0x08 |
:+1: |
-- |
v128.load32_splat |
0x09 |
:+1: |
-- |
v128.load64_splat |
0x0a |
:+1: |
-- |
Stores |
Opcode |
Old Backend Status |
VCode Status |
v128.store |
0x0b |
:+1: |
:+1: |
Basic operation |
Opcode |
Old Backend Status |
VCode Status |
v128.const |
0x0c |
:+1: |
:+1: |
i8x16.shuffle |
0x0d |
:+1: |
:+1: |
i8x16.swizzle |
0x0e |
:+1: |
:+1: |
Splat operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.splat |
0x0f |
:+1: |
:+1: |
i16x8.splat |
0x10 |
:+1: |
:+1: |
i32x4.splat |
0x11 |
:+1: |
:+1: |
i64x2.splat |
0x12 |
:+1: |
:+1: |
f32x4.splat |
0x13 |
:+1: |
:+1: |
f64x2.splat |
0x14 |
:+1: |
:+1: |
Lane operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.extract_lane_s |
0x15 |
:+1: |
:+1: |
i8x16.extract_lane_u |
0x16 |
:+1: |
:+1: |
i8x16.replace_lane |
0x17 |
:+1: |
:+1: |
i16x8.extract_lane_s |
0x18 |
:+1: |
:+1: |
i16x8.extract_lane_u |
0x19 |
:+1: |
:+1: |
i16x8.replace_lane |
0x1a |
:+1: |
:+1: |
i32x4.extract_lane |
0x1b |
:+1: |
:+1: |
i32x4.replace_lane |
0x1c |
:+1: |
:+1: |
i64x2.extract_lane |
0x1d |
:+1: |
:+1: |
i64x2.replace_lane |
0x1e |
:+1: |
:+1: |
f32x4.extract_lane |
0x1f |
:+1: |
:+1: |
f32x4.replace_lane |
0x20 |
:+1: |
:+1: |
f64x2.extract_lane |
0x21 |
:+1: |
:+1: |
f64x2.replace_lane |
0x22 |
:+1: |
:+1: |
Integer Cmp |
Opcode |
Old Backend Status |
VCode Status |
i8x16.eq |
0x23 |
:+1: |
:+1: |
i8x16.ne |
0x24 |
:+1: |
:+1: |
i8x16.lt_s |
0x25 |
:+1: |
:+1: |
i8x16.lt_u |
0x26 |
:+1: |
:+1: |
i8x16.gt_s |
0x27 |
:+1: |
:+1: |
i8x16.gt_u |
0x28 |
:+1: |
:+1: |
i8x16.le_s |
0x29 |
:+1: |
:+1: |
i8x16.le_u |
0x2a |
:+1: |
:+1: |
i8x16.ge_s |
0x2b |
:+1: |
:+1: |
i8x16.ge_u |
0x2c |
:+1: |
:+1: |
i16x8.eq |
0x2d |
:+1: |
:+1: |
i16x8.ne |
0x2e |
:+1: |
:+1: |
i16x8.lt_s |
0x2f |
:+1: |
:+1: |
i16x8.lt_u |
0x30 |
:+1: |
:+1: |
i16x8.gt_s |
0x31 |
:+1: |
:+1: |
i16x8.gt_u |
0x32 |
:+1: |
:+1: |
i16x8.le_s |
0x33 |
:+1: |
:+1: |
i16x8.le_u |
0x34 |
:+1: |
:+1: |
i16x8.ge_s |
0x35 |
:+1: |
:+1: |
i16x8.ge_u |
0x36 |
:+1: |
:+1: |
i32x4.eq |
0x37 |
:+1: |
:+1: |
i32x4.ne |
0x38 |
:+1: |
:+1: |
i32x4.lt_s |
0x39 |
:+1: |
:+1: |
i32x4.lt_u |
0x3a |
:+1: |
:+1: |
i32x4.gt_s |
0x3b |
:+1: |
:+1: |
i32x4.gt_u |
0x3c |
:+1: |
:+1: |
i32x4.le_s |
0x3d |
:+1: |
:+1: |
i32x4.le_u |
0x3e |
:+1: |
:+1: |
i32x4.ge_s |
0x3f |
:+1: |
:+1: |
i32x4.ge_u |
0x40 |
:+1: |
:+1: |
Float Cmp |
Opcode |
Old Backend Status |
VCode Status |
f32x4.eq |
0x41 |
:+1: |
:+1: |
f32x4.ne |
0x42 |
:+1: |
:+1: |
f32x4.lt |
0x43 |
:+1: |
:+1: |
f32x4.gt |
0x44 |
:+1: |
:+1: |
f32x4.le |
0x45 |
:+1: |
:+1: |
f32x4.ge |
0x46 |
:+1: |
:+1: |
f64x2.eq |
0x47 |
:+1: |
:+1: |
f64x2.ne |
0x48 |
:+1: |
:+1: |
f64x2.lt |
0x49 |
:+1: |
:+1: |
f64x2.gt |
0x4a |
:+1: |
:+1: |
f64x2.le |
0x4b |
:+1: |
:+1: |
f64x2.ge |
0x4c |
:+1: |
:+1: |
v128 Op |
Opcode |
Old Backend Status |
VCode Status |
v128.not |
0x4d |
:+1: |
:+1: |
v128.and |
0x4e |
:+1: |
:+1: |
v128.andnot |
0x4f |
:+1: |
:+1: |
v128.or |
0x50 |
:+1: |
:+1: |
v128.xor |
0x51 |
:+1: |
:+1: |
v128.bitselect |
0x52 |
:+1: |
:+1: |
i8x16 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i8x16.abs |
0x60 |
:+1: |
:+1: |
i8x16.neg |
0x61 |
:+1: |
:+1: |
i8x16.any_true |
0x62 |
:+1: |
:+1: |
i8x16.all_true |
0x63 |
:+1: |
:+1: |
i8x16.bitmask |
0x64 |
:question: |
:+1: |
i8x16.narrow_i16x8_s |
0x65 |
:+1: |
|
i8x16.narrow_i16x8_u |
0x66 |
:+1: |
|
---- widen ---- |
0x67 |
-- |
|
---- widen ---- |
0x68 |
-- |
|
---- widen ---- |
0x69 |
-- |
|
---- widen ---- |
0x6a |
-- |
|
i8x16.shl |
0x6b |
:+1: |
:+1: |
i8x16.shr_s |
0x6c |
:+1: |
:+1: |
i8x16.shr_u |
0x6d |
:+1: |
:+1: |
i8x16.add |
0x6e |
:+1: |
:+1: |
i8x16.add_sat_s |
0x6f |
:+1: |
:+1: |
i8x16.add_sat_u |
0x70 |
:+1: |
:+1: |
i8x16.sub |
0x71 |
:+1: |
:+1: |
i8x16.sub_sat_s |
0x72 |
:+1: |
:+1: |
i8x16.sub_sat_u |
0x73 |
:+1: |
:+1: |
---- dot ---- |
0x74 |
-- |
|
---- mul ---- |
0x75 |
:question: |
|
i8x16.min_s |
0x76 |
:+1: |
:+1: |
i8x16.min_u |
0x77 |
:+1: |
:+1: |
i8x16.max_s |
0x78 |
:+1: |
:+1: |
i8x16.max_u |
0x79 |
:+1: |
:+1: |
---- avgr_s ---- |
0x7a |
-- |
|
i8x16.avgr_u |
0x7b |
:+1: |
:+1: |
i16x8 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i16x8.abs |
0x80 |
:+1: |
:+1: |
i16x8.neg |
0x81 |
:+1: |
:+1: |
i16x8.any_true |
0x82 |
:+1: |
:+1: |
i16x8.all_true |
0x83 |
:+1: |
:+1: |
i16x8.bitmask |
0x84 |
:question: |
:+1: |
i16x8.narrow_i32x4_s |
0x85 |
:+1: |
|
i16x8.narrow_i32x4_u |
0x86 |
:+1: |
|
i16x8.widen_low_i8x16_s |
0x87 |
:+1: |
|
i16x8.widen_high_i8x16_s |
0x88 |
:+1: |
|
i16x8.widen_low_i8x16_u |
0x89 |
:+1: |
|
i16x8.widen_high_i8x16_u |
0x8a |
:+1: |
|
i16x8.shl |
0x8b |
:+1: |
:+1: |
i16x8.shr_s |
0x8c |
:+1: |
:+1: |
i16x8.shr_u |
0x8d |
:+1: |
:+1: |
i16x8.add |
0x8e |
:+1: |
:+1: |
i16x8.add_sat_s |
0x8f |
:+1: |
:+1: |
i16x8.add_sat_u |
0x90 |
:+1: |
:+1: |
i16x8.sub |
0x91 |
:+1: |
:+1: |
i16x8.sub_sat_s |
0x92 |
:+1: |
:+1: |
i16x8.sub_sat_u |
0x93 |
:+1: |
:+1: |
---- dot ---- |
0x94 |
-- |
|
i16x8.mul |
0x95 |
:+1: |
:+1: |
i16x8.min_s |
0x96 |
:+1: |
:+1: |
i16x8.min_u |
0x97 |
:+1: |
:+1: |
i16x8.max_s |
0x98 |
:+1: |
:+1: |
i16x8.max_u |
0x99 |
:+1: |
:+1: |
---- avgr_s ---- |
0x9a |
-- |
|
i16x8.avgr_u |
0x9b |
:+1: |
:+1: |
i32x4 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i32x4.abs |
0xa0 |
:+1: |
:+1: |
i32x4.neg |
0xa1 |
:+1: |
:+1: |
i32x4.any_true |
0xa2 |
:+1: |
:+1: |
i32x4.all_true |
0xa3 |
:+1: |
:+1: |
i32x4.bitmask |
0xa4 |
:question: |
:+1: |
---- narrow ---- |
0xa5 |
-- |
|
---- narrow ---- |
0xa6 |
-- |
|
i32x4.widen_low_i16x8_s |
0xa7 |
:+1: |
|
i32x4.widen_high_i16x8_s |
0xa8 |
:+1: |
|
i32x4.widen_low_i16x8_u |
0xa9 |
:+1: |
|
i32x4.widen_high_i16x8_u |
0xaa |
:+1: |
|
i32x4.shl |
0xab |
:+1: |
:+1: |
i32x4.shr_s |
0xac |
:+1: |
:+1: |
i32x4.shr_u |
0xad |
:+1: |
:+1: |
i32x4.add |
0xae |
:+1: |
:+1: |
---- add_sat ---- |
0xaf |
-- |
|
---- add_sat ---- |
0xb0 |
-- |
|
i32x4.sub |
0xb1 |
:+1: |
:+1: |
---- sub_sat ---- |
0xb2 |
-- |
|
---- sub_sat ---- |
0xb3 |
-- |
|
---- dot ---- |
0xb4 |
-- |
|
i32x4.mul |
0xb5 |
:+1: |
:+1: |
i32x4.min_s |
0xb6 |
:+1: |
:+1: |
i32x4.min_u |
0xb7 |
:+1: |
:+1: |
i32x4.max_s |
0xb8 |
:+1: |
:+1: |
i32x4.max_u |
0xb9 |
:+1: |
:+1: |
---- avgr_s ---- |
0xba |
-- |
|
---- avgr_u ---- |
0xbb |
-- |
|
i64x2 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
---- |
0xc0 |
-- |
|
i64x2.neg |
0xc1 |
:+1: |
:+1: |
---- |
0xc2 |
-- |
|
---- |
0xc3 |
-- |
|
---- |
0xc4 |
-- |
|
---- |
0xc5 |
-- |
|
---- |
0xc6 |
-- |
|
---- |
0xc7 |
-- |
|
---- |
0xc8 |
-- |
|
---- |
0xc9 |
-- |
|
---- |
0xca |
-- |
|
i64x2.shl |
0xcb |
:+1: |
:+1: |
i64x2.shr_s |
0xcc |
:+1: |
:+1: |
i64x2.shr_u |
0xcd |
:+1: |
:+1: |
i64x2.add |
0xce |
:+1: |
:+1: |
---- |
0xcf |
-- |
|
---- |
0xd0 |
-- |
|
i64x2.sub |
0xd1 |
:+1: |
:+1: |
---- |
0xd2 |
-- |
|
---- |
0xd3 |
-- |
|
---- |
0xd4 |
-- |
|
i64x2.mul |
0xd5 |
:+1: |
:+1: |
---- |
0xd6 |
-- |
|
---- |
0xd7 |
-- |
|
f32x4 Op |
Opcode |
Old Backend Status |
VCode Status |
f32x4.ceil |
0xd8 |
:question: |
@jlb6740 |
f32x4.floor |
0xd9 |
:question: |
@jlb6740 |
f32x4.trunc |
0xda |
:question: |
@jlb6740 |
f32x4.nearest |
0xdb |
:question: |
@jlb6740 |
f32x4.abs |
0xe0 |
:+1: |
:+1: |
f32x4.neg |
0xe1 |
:+1: |
:+1: |
---- round ---- |
0xe2 |
-- |
|
f32x4.sqrt |
0xe3 |
:+1: |
:+1: |
f32x4.add |
0xe4 |
:+1: |
:+1: |
f32x4.sub |
0xe5 |
:+1: |
:+1: |
f32x4.mul |
0xe6 |
:+1: |
:+1: |
f32x4.div |
0xe7 |
:+1: |
:+1: |
f32x4.min |
0xe8 |
:+1: |
:+1: |
f32x4.max |
0xe9 |
:+1: |
:+1: |
f32x4.pmin |
0xea |
:question: |
:+1: |
f32x4.pmax |
0xeb |
:question: |
:+1: |
f64x2 Op |
Opcode |
Old Backend Status |
VCode Status |
f64x2.ceil |
0xdc |
:question: |
@jlb6740 |
f64x2.floor |
0xdd |
:question: |
@jlb6740 |
f64x2.trunc |
0xde |
:question: |
@jlb6740 |
f64x2.nearest |
0xdf |
:question: |
@jlb6740 |
f64x2.abs |
0xec |
:+1: |
:+1: |
f64x2.neg |
0xed |
:+1: |
:+1: |
---- round ---- |
0xee |
-- |
|
f64x2.sqrt |
0xef |
:+1: |
:+1: |
f64x2.add |
0xf0 |
:+1: |
:+1: |
f64x2.sub |
0xf1 |
:+1: |
:+1: |
f64x2.mul |
0xf2 |
:+1: |
:+1: |
f64x2.div |
0xf3 |
:+1: |
:+1: |
f64x2.min |
0xf4 |
:+1: |
:+1: |
f64x2.max |
0xf5 |
:+1: |
:+1: |
f64x2.pmin |
0xf6 |
:question: |
:+1: |
f64x2.pmax |
0xf7 |
:question: |
:+1: |
Conversion Op |
Opcode |
Old Backend Status |
VCode Status |
i32x4.trunc_sat_f32x4_s |
0xf8 |
:question: |
:+1: |
i32x4.trunc_sat_f32x4_u |
0xf9 |
:question: |
@jlb6740 |
f32x4.convert_i32x4_s |
0xfa |
:+1: |
:+1: |
f32x4.convert_i32x4_u |
0xfb |
:question: |
:+1: |
jlb6740 edited Issue #2272:
Last Update: 10/28/2020
Loads |
Opcode |
Old Backend Status |
VCode Status |
v128.load |
0x00 |
:+1: |
:+1: |
v128.load8x8_s |
0x01 |
:+1: |
-- |
v128.load8x8_u |
0x02 |
:+1: |
-- |
v128.load16x4_s |
0x03 |
:+1: |
-- |
v128.load16x4_u |
0x04 |
:+1: |
-- |
v128.load32x2_s |
0x05 |
:+1: |
-- |
v128.load32x2_u |
0x06 |
:+1: |
-- |
v128.load8_splat |
0x07 |
:+1: |
-- |
v128.load16_splat |
0x08 |
:+1: |
-- |
v128.load32_splat |
0x09 |
:+1: |
-- |
v128.load64_splat |
0x0a |
:+1: |
-- |
Stores |
Opcode |
Old Backend Status |
VCode Status |
v128.store |
0x0b |
:+1: |
:+1: |
Basic operation |
Opcode |
Old Backend Status |
VCode Status |
v128.const |
0x0c |
:+1: |
:+1: |
i8x16.shuffle |
0x0d |
:+1: |
:+1: |
i8x16.swizzle |
0x0e |
:+1: |
:+1: |
Splat operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.splat |
0x0f |
:+1: |
:+1: |
i16x8.splat |
0x10 |
:+1: |
:+1: |
i32x4.splat |
0x11 |
:+1: |
:+1: |
i64x2.splat |
0x12 |
:+1: |
:+1: |
f32x4.splat |
0x13 |
:+1: |
:+1: |
f64x2.splat |
0x14 |
:+1: |
:+1: |
Lane operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.extract_lane_s |
0x15 |
:+1: |
:+1: |
i8x16.extract_lane_u |
0x16 |
:+1: |
:+1: |
i8x16.replace_lane |
0x17 |
:+1: |
:+1: |
i16x8.extract_lane_s |
0x18 |
:+1: |
:+1: |
i16x8.extract_lane_u |
0x19 |
:+1: |
:+1: |
i16x8.replace_lane |
0x1a |
:+1: |
:+1: |
i32x4.extract_lane |
0x1b |
:+1: |
:+1: |
i32x4.replace_lane |
0x1c |
:+1: |
:+1: |
i64x2.extract_lane |
0x1d |
:+1: |
:+1: |
i64x2.replace_lane |
0x1e |
:+1: |
:+1: |
f32x4.extract_lane |
0x1f |
:+1: |
:+1: |
f32x4.replace_lane |
0x20 |
:+1: |
:+1: |
f64x2.extract_lane |
0x21 |
:+1: |
:+1: |
f64x2.replace_lane |
0x22 |
:+1: |
:+1: |
Integer Cmp |
Opcode |
Old Backend Status |
VCode Status |
i8x16.eq |
0x23 |
:+1: |
:+1: |
i8x16.ne |
0x24 |
:+1: |
:+1: |
i8x16.lt_s |
0x25 |
:+1: |
:+1: |
i8x16.lt_u |
0x26 |
:+1: |
:+1: |
i8x16.gt_s |
0x27 |
:+1: |
:+1: |
i8x16.gt_u |
0x28 |
:+1: |
:+1: |
i8x16.le_s |
0x29 |
:+1: |
:+1: |
i8x16.le_u |
0x2a |
:+1: |
:+1: |
i8x16.ge_s |
0x2b |
:+1: |
:+1: |
i8x16.ge_u |
0x2c |
:+1: |
:+1: |
i16x8.eq |
0x2d |
:+1: |
:+1: |
i16x8.ne |
0x2e |
:+1: |
:+1: |
i16x8.lt_s |
0x2f |
:+1: |
:+1: |
i16x8.lt_u |
0x30 |
:+1: |
:+1: |
i16x8.gt_s |
0x31 |
:+1: |
:+1: |
i16x8.gt_u |
0x32 |
:+1: |
:+1: |
i16x8.le_s |
0x33 |
:+1: |
:+1: |
i16x8.le_u |
0x34 |
:+1: |
:+1: |
i16x8.ge_s |
0x35 |
:+1: |
:+1: |
i16x8.ge_u |
0x36 |
:+1: |
:+1: |
i32x4.eq |
0x37 |
:+1: |
:+1: |
i32x4.ne |
0x38 |
:+1: |
:+1: |
i32x4.lt_s |
0x39 |
:+1: |
:+1: |
i32x4.lt_u |
0x3a |
:+1: |
:+1: |
i32x4.gt_s |
0x3b |
:+1: |
:+1: |
i32x4.gt_u |
0x3c |
:+1: |
:+1: |
i32x4.le_s |
0x3d |
:+1: |
:+1: |
i32x4.le_u |
0x3e |
:+1: |
:+1: |
i32x4.ge_s |
0x3f |
:+1: |
:+1: |
i32x4.ge_u |
0x40 |
:+1: |
:+1: |
Float Cmp |
Opcode |
Old Backend Status |
VCode Status |
f32x4.eq |
0x41 |
:+1: |
:+1: |
f32x4.ne |
0x42 |
:+1: |
:+1: |
f32x4.lt |
0x43 |
:+1: |
:+1: |
f32x4.gt |
0x44 |
:+1: |
:+1: |
f32x4.le |
0x45 |
:+1: |
:+1: |
f32x4.ge |
0x46 |
:+1: |
:+1: |
f64x2.eq |
0x47 |
:+1: |
:+1: |
f64x2.ne |
0x48 |
:+1: |
:+1: |
f64x2.lt |
0x49 |
:+1: |
:+1: |
f64x2.gt |
0x4a |
:+1: |
:+1: |
f64x2.le |
0x4b |
:+1: |
:+1: |
f64x2.ge |
0x4c |
:+1: |
:+1: |
v128 Op |
Opcode |
Old Backend Status |
VCode Status |
v128.not |
0x4d |
:+1: |
:+1: |
v128.and |
0x4e |
:+1: |
:+1: |
v128.andnot |
0x4f |
:+1: |
:+1: |
v128.or |
0x50 |
:+1: |
:+1: |
v128.xor |
0x51 |
:+1: |
:+1: |
v128.bitselect |
0x52 |
:+1: |
:+1: |
i8x16 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i8x16.abs |
0x60 |
:+1: |
:+1: |
i8x16.neg |
0x61 |
:+1: |
:+1: |
i8x16.any_true |
0x62 |
:+1: |
:+1: |
i8x16.all_true |
0x63 |
:+1: |
:+1: |
i8x16.bitmask |
0x64 |
:question: |
:+1: |
i8x16.narrow_i16x8_s |
0x65 |
:+1: |
@jlb6740 |
i8x16.narrow_i16x8_u |
0x66 |
:+1: |
@jlb6740 |
---- widen ---- |
0x67 |
-- |
|
---- widen ---- |
0x68 |
-- |
|
---- widen ---- |
0x69 |
-- |
|
---- widen ---- |
0x6a |
-- |
|
i8x16.shl |
0x6b |
:+1: |
:+1: |
i8x16.shr_s |
0x6c |
:+1: |
:+1: |
i8x16.shr_u |
0x6d |
:+1: |
:+1: |
i8x16.add |
0x6e |
:+1: |
:+1: |
i8x16.add_sat_s |
0x6f |
:+1: |
:+1: |
i8x16.add_sat_u |
0x70 |
:+1: |
:+1: |
i8x16.sub |
0x71 |
:+1: |
:+1: |
i8x16.sub_sat_s |
0x72 |
:+1: |
:+1: |
i8x16.sub_sat_u |
0x73 |
:+1: |
:+1: |
---- dot ---- |
0x74 |
-- |
|
---- mul ---- |
0x75 |
:question: |
|
i8x16.min_s |
0x76 |
:+1: |
:+1: |
i8x16.min_u |
0x77 |
:+1: |
:+1: |
i8x16.max_s |
0x78 |
:+1: |
:+1: |
i8x16.max_u |
0x79 |
:+1: |
:+1: |
---- avgr_s ---- |
0x7a |
-- |
|
i8x16.avgr_u |
0x7b |
:+1: |
:+1: |
i16x8 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i16x8.abs |
0x80 |
:+1: |
:+1: |
i16x8.neg |
0x81 |
:+1: |
:+1: |
i16x8.any_true |
0x82 |
:+1: |
:+1: |
i16x8.all_true |
0x83 |
:+1: |
:+1: |
i16x8.bitmask |
0x84 |
:question: |
:+1: |
i16x8.narrow_i32x4_s |
0x85 |
:+1: |
@jlb6740 |
i16x8.narrow_i32x4_u |
0x86 |
:+1: |
@jlb6740 |
i16x8.widen_low_i8x16_s |
0x87 |
:+1: |
@jlb6740 |
i16x8.widen_high_i8x16_s |
0x88 |
:+1: |
@jlb6740 |
i16x8.widen_low_i8x16_u |
0x89 |
:+1: |
@jlb6740 |
i16x8.widen_high_i8x16_u |
0x8a |
:+1: |
@jlb6740 |
i16x8.shl |
0x8b |
:+1: |
:+1: |
i16x8.shr_s |
0x8c |
:+1: |
:+1: |
i16x8.shr_u |
0x8d |
:+1: |
:+1: |
i16x8.add |
0x8e |
:+1: |
:+1: |
i16x8.add_sat_s |
0x8f |
:+1: |
:+1: |
i16x8.add_sat_u |
0x90 |
:+1: |
:+1: |
i16x8.sub |
0x91 |
:+1: |
:+1: |
i16x8.sub_sat_s |
0x92 |
:+1: |
:+1: |
i16x8.sub_sat_u |
0x93 |
:+1: |
:+1: |
---- dot ---- |
0x94 |
-- |
|
i16x8.mul |
0x95 |
:+1: |
:+1: |
i16x8.min_s |
0x96 |
:+1: |
:+1: |
i16x8.min_u |
0x97 |
:+1: |
:+1: |
i16x8.max_s |
0x98 |
:+1: |
:+1: |
i16x8.max_u |
0x99 |
:+1: |
:+1: |
---- avgr_s ---- |
0x9a |
-- |
|
i16x8.avgr_u |
0x9b |
:+1: |
:+1: |
i32x4 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i32x4.abs |
0xa0 |
:+1: |
:+1: |
i32x4.neg |
0xa1 |
:+1: |
:+1: |
i32x4.any_true |
0xa2 |
:+1: |
:+1: |
i32x4.all_true |
0xa3 |
:+1: |
:+1: |
i32x4.bitmask |
0xa4 |
:question: |
:+1: |
---- narrow ---- |
0xa5 |
-- |
|
---- narrow ---- |
0xa6 |
-- |
|
i32x4.widen_low_i16x8_s |
0xa7 |
:+1: |
@jlb6740 |
i32x4.widen_high_i16x8_s |
0xa8 |
:+1: |
@jlb6740 |
i32x4.widen_low_i16x8_u |
0xa9 |
:+1: |
@jlb6740 |
i32x4.widen_high_i16x8_u |
0xaa |
:+1: |
@jlb6740 |
i32x4.shl |
0xab |
:+1: |
:+1: |
i32x4.shr_s |
0xac |
:+1: |
:+1: |
i32x4.shr_u |
0xad |
:+1: |
:+1: |
i32x4.add |
0xae |
:+1: |
:+1: |
---- add_sat ---- |
0xaf |
-- |
|
---- add_sat ---- |
0xb0 |
-- |
|
i32x4.sub |
0xb1 |
:+1: |
:+1: |
---- sub_sat ---- |
0xb2 |
-- |
|
---- sub_sat ---- |
0xb3 |
-- |
|
---- dot ---- |
0xb4 |
-- |
|
i32x4.mul |
0xb5 |
:+1: |
:+1: |
i32x4.min_s |
0xb6 |
:+1: |
:+1: |
i32x4.min_u |
0xb7 |
:+1: |
:+1: |
i32x4.max_s |
0xb8 |
:+1: |
:+1: |
i32x4.max_u |
0xb9 |
:+1: |
:+1: |
---- avgr_s ---- |
0xba |
-- |
|
---- avgr_u ---- |
0xbb |
-- |
|
i64x2 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
---- |
0xc0 |
-- |
|
i64x2.neg |
0xc1 |
:+1: |
:+1: |
---- |
0xc2 |
-- |
|
---- |
0xc3 |
-- |
|
---- |
0xc4 |
-- |
|
---- |
0xc5 |
-- |
|
---- |
0xc6 |
-- |
|
---- |
0xc7 |
-- |
|
---- |
0xc8 |
-- |
|
---- |
0xc9 |
-- |
|
---- |
0xca |
-- |
|
i64x2.shl |
0xcb |
:+1: |
:+1: |
i64x2.shr_s |
0xcc |
:+1: |
:+1: |
i64x2.shr_u |
0xcd |
:+1: |
:+1: |
i64x2.add |
0xce |
:+1: |
:+1: |
---- |
0xcf |
-- |
|
---- |
0xd0 |
-- |
|
i64x2.sub |
0xd1 |
:+1: |
:+1: |
---- |
0xd2 |
-- |
|
---- |
0xd3 |
-- |
|
---- |
0xd4 |
-- |
|
i64x2.mul |
0xd5 |
:+1: |
:+1: |
---- |
0xd6 |
-- |
|
---- |
0xd7 |
-- |
|
f32x4 Op |
Opcode |
Old Backend Status |
VCode Status |
f32x4.ceil |
0xd8 |
:question: |
@jlb6740 |
f32x4.floor |
0xd9 |
:question: |
@jlb6740 |
f32x4.trunc |
0xda |
:question: |
@jlb6740 |
f32x4.nearest |
0xdb |
:question: |
@jlb6740 |
f32x4.abs |
0xe0 |
:+1: |
:+1: |
f32x4.neg |
0xe1 |
:+1: |
:+1: |
---- round ---- |
0xe2 |
-- |
|
f32x4.sqrt |
0xe3 |
:+1: |
:+1: |
f32x4.add |
0xe4 |
:+1: |
:+1: |
f32x4.sub |
0xe5 |
:+1: |
:+1: |
f32x4.mul |
0xe6 |
:+1: |
:+1: |
f32x4.div |
0xe7 |
:+1: |
:+1: |
f32x4.min |
0xe8 |
:+1: |
:+1: |
f32x4.max |
0xe9 |
:+1: |
:+1: |
f32x4.pmin |
0xea |
:question: |
:+1: |
f32x4.pmax |
0xeb |
:question: |
:+1: |
f64x2 Op |
Opcode |
Old Backend Status |
VCode Status |
f64x2.ceil |
0xdc |
:question: |
@jlb6740 |
f64x2.floor |
0xdd |
:question: |
@jlb6740 |
f64x2.trunc |
0xde |
:question: |
@jlb6740 |
f64x2.nearest |
0xdf |
:question: |
@jlb6740 |
f64x2.abs |
0xec |
:+1: |
:+1: |
f64x2.neg |
0xed |
:+1: |
:+1: |
---- round ---- |
0xee |
-- |
|
f64x2.sqrt |
0xef |
:+1: |
:+1: |
f64x2.add |
0xf0 |
:+1: |
:+1: |
f64x2.sub |
0xf1 |
:+1: |
:+1: |
f64x2.mul |
0xf2 |
:+1: |
:+1: |
f64x2.div |
0xf3 |
:+1: |
:+1: |
f64x2.min |
0xf4 |
:+1: |
:+1: |
f64x2.max |
0xf5 |
:+1: |
:+1: |
f64x2.pmin |
0xf6 |
:question: |
:+1: |
f64x2.pmax |
0xf7 |
:question: |
:+1: |
Conversion Op |
Opcode |
Old Backend Status |
VCode Status |
i32x4.trunc_sat_f32x4_s |
0xf8 |
:question: |
:+1: |
i32x4.trunc_sat_f32x4_u |
0xf9 |
:question: |
@jlb6740 |
f32x4.convert_i32x4_s |
0xfa |
:+1: |
:+1: |
f32x4.convert_i32x4_u |
0xfb |
:question: |
:+1: |
jlb6740 edited Issue #2272:
Last Update: 10/28/2020
Loads |
Opcode |
Old Backend Status |
VCode Status |
v128.load |
0x00 |
:+1: |
:+1: |
v128.load8x8_s |
0x01 |
:+1: |
@jlb6740 |
v128.load8x8_u |
0x02 |
:+1: |
@jlb6740 |
v128.load16x4_s |
0x03 |
:+1: |
@jlb6740 |
v128.load16x4_u |
0x04 |
:+1: |
@jlb6740 |
v128.load32x2_s |
0x05 |
:+1: |
@jlb6740 |
v128.load32x2_u |
0x06 |
:+1: |
@jlb6740 |
v128.load8_splat |
0x07 |
:+1: |
@jlb6740 |
v128.load16_splat |
0x08 |
:+1: |
@jlb6740 |
v128.load32_splat |
0x09 |
:+1: |
@jlb6740 |
v128.load64_splat |
0x0a |
:+1: |
@jlb6740 |
Stores |
Opcode |
Old Backend Status |
VCode Status |
v128.store |
0x0b |
:+1: |
:+1: |
Basic operation |
Opcode |
Old Backend Status |
VCode Status |
v128.const |
0x0c |
:+1: |
:+1: |
i8x16.shuffle |
0x0d |
:+1: |
:+1: |
i8x16.swizzle |
0x0e |
:+1: |
:+1: |
Splat operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.splat |
0x0f |
:+1: |
:+1: |
i16x8.splat |
0x10 |
:+1: |
:+1: |
i32x4.splat |
0x11 |
:+1: |
:+1: |
i64x2.splat |
0x12 |
:+1: |
:+1: |
f32x4.splat |
0x13 |
:+1: |
:+1: |
f64x2.splat |
0x14 |
:+1: |
:+1: |
Lane operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.extract_lane_s |
0x15 |
:+1: |
:+1: |
i8x16.extract_lane_u |
0x16 |
:+1: |
:+1: |
i8x16.replace_lane |
0x17 |
:+1: |
:+1: |
i16x8.extract_lane_s |
0x18 |
:+1: |
:+1: |
i16x8.extract_lane_u |
0x19 |
:+1: |
:+1: |
i16x8.replace_lane |
0x1a |
:+1: |
:+1: |
i32x4.extract_lane |
0x1b |
:+1: |
:+1: |
i32x4.replace_lane |
0x1c |
:+1: |
:+1: |
i64x2.extract_lane |
0x1d |
:+1: |
:+1: |
i64x2.replace_lane |
0x1e |
:+1: |
:+1: |
f32x4.extract_lane |
0x1f |
:+1: |
:+1: |
f32x4.replace_lane |
0x20 |
:+1: |
:+1: |
f64x2.extract_lane |
0x21 |
:+1: |
:+1: |
f64x2.replace_lane |
0x22 |
:+1: |
:+1: |
Integer Cmp |
Opcode |
Old Backend Status |
VCode Status |
i8x16.eq |
0x23 |
:+1: |
:+1: |
i8x16.ne |
0x24 |
:+1: |
:+1: |
i8x16.lt_s |
0x25 |
:+1: |
:+1: |
i8x16.lt_u |
0x26 |
:+1: |
:+1: |
i8x16.gt_s |
0x27 |
:+1: |
:+1: |
i8x16.gt_u |
0x28 |
:+1: |
:+1: |
i8x16.le_s |
0x29 |
:+1: |
:+1: |
i8x16.le_u |
0x2a |
:+1: |
:+1: |
i8x16.ge_s |
0x2b |
:+1: |
:+1: |
i8x16.ge_u |
0x2c |
:+1: |
:+1: |
i16x8.eq |
0x2d |
:+1: |
:+1: |
i16x8.ne |
0x2e |
:+1: |
:+1: |
i16x8.lt_s |
0x2f |
:+1: |
:+1: |
i16x8.lt_u |
0x30 |
:+1: |
:+1: |
i16x8.gt_s |
0x31 |
:+1: |
:+1: |
i16x8.gt_u |
0x32 |
:+1: |
:+1: |
i16x8.le_s |
0x33 |
:+1: |
:+1: |
i16x8.le_u |
0x34 |
:+1: |
:+1: |
i16x8.ge_s |
0x35 |
:+1: |
:+1: |
i16x8.ge_u |
0x36 |
:+1: |
:+1: |
i32x4.eq |
0x37 |
:+1: |
:+1: |
i32x4.ne |
0x38 |
:+1: |
:+1: |
i32x4.lt_s |
0x39 |
:+1: |
:+1: |
i32x4.lt_u |
0x3a |
:+1: |
:+1: |
i32x4.gt_s |
0x3b |
:+1: |
:+1: |
i32x4.gt_u |
0x3c |
:+1: |
:+1: |
i32x4.le_s |
0x3d |
:+1: |
:+1: |
i32x4.le_u |
0x3e |
:+1: |
:+1: |
i32x4.ge_s |
0x3f |
:+1: |
:+1: |
i32x4.ge_u |
0x40 |
:+1: |
:+1: |
Float Cmp |
Opcode |
Old Backend Status |
VCode Status |
f32x4.eq |
0x41 |
:+1: |
:+1: |
f32x4.ne |
0x42 |
:+1: |
:+1: |
f32x4.lt |
0x43 |
:+1: |
:+1: |
f32x4.gt |
0x44 |
:+1: |
:+1: |
f32x4.le |
0x45 |
:+1: |
:+1: |
f32x4.ge |
0x46 |
:+1: |
:+1: |
f64x2.eq |
0x47 |
:+1: |
:+1: |
f64x2.ne |
0x48 |
:+1: |
:+1: |
f64x2.lt |
0x49 |
:+1: |
:+1: |
f64x2.gt |
0x4a |
:+1: |
:+1: |
f64x2.le |
0x4b |
:+1: |
:+1: |
f64x2.ge |
0x4c |
:+1: |
:+1: |
v128 Op |
Opcode |
Old Backend Status |
VCode Status |
v128.not |
0x4d |
:+1: |
:+1: |
v128.and |
0x4e |
:+1: |
:+1: |
v128.andnot |
0x4f |
:+1: |
:+1: |
v128.or |
0x50 |
:+1: |
:+1: |
v128.xor |
0x51 |
:+1: |
:+1: |
v128.bitselect |
0x52 |
:+1: |
:+1: |
i8x16 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i8x16.abs |
0x60 |
:+1: |
:+1: |
i8x16.neg |
0x61 |
:+1: |
:+1: |
i8x16.any_true |
0x62 |
:+1: |
:+1: |
i8x16.all_true |
0x63 |
:+1: |
:+1: |
i8x16.bitmask |
0x64 |
:question: |
:+1: |
i8x16.narrow_i16x8_s |
0x65 |
:+1: |
:+1: |
i8x16.narrow_i16x8_u |
0x66 |
:+1: |
:+1: |
---- widen ---- |
0x67 |
-- |
|
---- widen ---- |
0x68 |
-- |
|
---- widen ---- |
0x69 |
-- |
|
---- widen ---- |
0x6a |
-- |
|
i8x16.shl |
0x6b |
:+1: |
:+1: |
i8x16.shr_s |
0x6c |
:+1: |
:+1: |
i8x16.shr_u |
0x6d |
:+1: |
:+1: |
i8x16.add |
0x6e |
:+1: |
:+1: |
i8x16.add_sat_s |
0x6f |
:+1: |
:+1: |
i8x16.add_sat_u |
0x70 |
:+1: |
:+1: |
i8x16.sub |
0x71 |
:+1: |
:+1: |
i8x16.sub_sat_s |
0x72 |
:+1: |
:+1: |
i8x16.sub_sat_u |
0x73 |
:+1: |
:+1: |
---- dot ---- |
0x74 |
-- |
|
---- mul ---- |
0x75 |
:question: |
|
i8x16.min_s |
0x76 |
:+1: |
:+1: |
i8x16.min_u |
0x77 |
:+1: |
:+1: |
i8x16.max_s |
0x78 |
:+1: |
:+1: |
i8x16.max_u |
0x79 |
:+1: |
:+1: |
---- avgr_s ---- |
0x7a |
-- |
|
i8x16.avgr_u |
0x7b |
:+1: |
:+1: |
i16x8 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i16x8.abs |
0x80 |
:+1: |
:+1: |
i16x8.neg |
0x81 |
:+1: |
:+1: |
i16x8.any_true |
0x82 |
:+1: |
:+1: |
i16x8.all_true |
0x83 |
:+1: |
:+1: |
i16x8.bitmask |
0x84 |
:question: |
:+1: |
i16x8.narrow_i32x4_s |
0x85 |
:+1: |
:+1: |
i16x8.narrow_i32x4_u |
0x86 |
:+1: |
:+1: |
i16x8.widen_low_i8x16_s |
0x87 |
:+1: |
:+1: |
i16x8.widen_high_i8x16_s |
0x88 |
:+1: |
:+1: |
i16x8.widen_low_i8x16_u |
0x89 |
:+1: |
:+1: |
i16x8.widen_high_i8x16_u |
0x8a |
:+1: |
:+1: |
i16x8.shl |
0x8b |
:+1: |
:+1: |
i16x8.shr_s |
0x8c |
:+1: |
:+1: |
i16x8.shr_u |
0x8d |
:+1: |
:+1: |
i16x8.add |
0x8e |
:+1: |
:+1: |
i16x8.add_sat_s |
0x8f |
:+1: |
:+1: |
i16x8.add_sat_u |
0x90 |
:+1: |
:+1: |
i16x8.sub |
0x91 |
:+1: |
:+1: |
i16x8.sub_sat_s |
0x92 |
:+1: |
:+1: |
i16x8.sub_sat_u |
0x93 |
:+1: |
:+1: |
---- dot ---- |
0x94 |
-- |
|
i16x8.mul |
0x95 |
:+1: |
:+1: |
i16x8.min_s |
0x96 |
:+1: |
:+1: |
i16x8.min_u |
0x97 |
:+1: |
:+1: |
i16x8.max_s |
0x98 |
:+1: |
:+1: |
i16x8.max_u |
0x99 |
:+1: |
:+1: |
---- avgr_s ---- |
0x9a |
-- |
|
i16x8.avgr_u |
0x9b |
:+1: |
:+1: |
i32x4 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i32x4.abs |
0xa0 |
:+1: |
:+1: |
i32x4.neg |
0xa1 |
:+1: |
:+1: |
i32x4.any_true |
0xa2 |
:+1: |
:+1: |
i32x4.all_true |
0xa3 |
:+1: |
:+1: |
i32x4.bitmask |
0xa4 |
:question: |
:+1: |
---- narrow ---- |
0xa5 |
-- |
|
---- narrow ---- |
0xa6 |
-- |
|
i32x4.widen_low_i16x8_s |
0xa7 |
:+1: |
:+1: |
i32x4.widen_high_i16x8_s |
0xa8 |
:+1: |
:+1: |
i32x4.widen_low_i16x8_u |
0xa9 |
:+1: |
:+1: |
i32x4.widen_high_i16x8_u |
0xaa |
:+1: |
:+1: |
i32x4.shl |
0xab |
:+1: |
:+1: |
i32x4.shr_s |
0xac |
:+1: |
:+1: |
i32x4.shr_u |
0xad |
:+1: |
:+1: |
i32x4.add |
0xae |
:+1: |
:+1: |
---- add_sat ---- |
0xaf |
-- |
|
---- add_sat ---- |
0xb0 |
-- |
|
i32x4.sub |
0xb1 |
:+1: |
:+1: |
---- sub_sat ---- |
0xb2 |
-- |
|
---- sub_sat ---- |
0xb3 |
-- |
|
---- dot ---- |
0xb4 |
-- |
|
i32x4.mul |
0xb5 |
:+1: |
:+1: |
i32x4.min_s |
0xb6 |
:+1: |
:+1: |
i32x4.min_u |
0xb7 |
:+1: |
:+1: |
i32x4.max_s |
0xb8 |
:+1: |
:+1: |
i32x4.max_u |
0xb9 |
:+1: |
:+1: |
---- avgr_s ---- |
0xba |
-- |
|
---- avgr_u ---- |
0xbb |
-- |
|
i64x2 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
---- |
0xc0 |
-- |
|
i64x2.neg |
0xc1 |
:+1: |
:+1: |
---- |
0xc2 |
-- |
|
---- |
0xc3 |
-- |
|
---- |
0xc4 |
-- |
|
---- |
0xc5 |
-- |
|
---- |
0xc6 |
-- |
|
---- |
0xc7 |
-- |
|
---- |
0xc8 |
-- |
|
---- |
0xc9 |
-- |
|
---- |
0xca |
-- |
|
i64x2.shl |
0xcb |
:+1: |
:+1: |
i64x2.shr_s |
0xcc |
:+1: |
:+1: |
i64x2.shr_u |
0xcd |
:+1: |
:+1: |
i64x2.add |
0xce |
:+1: |
:+1: |
---- |
0xcf |
-- |
|
---- |
0xd0 |
-- |
|
i64x2.sub |
0xd1 |
:+1: |
:+1: |
---- |
0xd2 |
-- |
|
---- |
0xd3 |
-- |
|
---- |
0xd4 |
-- |
|
i64x2.mul |
0xd5 |
:+1: |
:+1: |
---- |
0xd6 |
-- |
|
---- |
0xd7 |
-- |
|
f32x4 Op |
Opcode |
Old Backend Status |
VCode Status |
f32x4.ceil |
0xd8 |
:question: |
@jlb6740 |
f32x4.floor |
0xd9 |
:question: |
@jlb6740 |
f32x4.trunc |
0xda |
:question: |
@jlb6740 |
f32x4.nearest |
0xdb |
:question: |
@jlb6740 |
f32x4.abs |
0xe0 |
:+1: |
:+1: |
f32x4.neg |
0xe1 |
:+1: |
:+1: |
---- round ---- |
0xe2 |
-- |
|
f32x4.sqrt |
0xe3 |
:+1: |
:+1: |
f32x4.add |
0xe4 |
:+1: |
:+1: |
f32x4.sub |
0xe5 |
:+1: |
:+1: |
f32x4.mul |
0xe6 |
:+1: |
:+1: |
f32x4.div |
0xe7 |
:+1: |
:+1: |
f32x4.min |
0xe8 |
:+1: |
:+1: |
f32x4.max |
0xe9 |
:+1: |
:+1: |
f32x4.pmin |
0xea |
:question: |
:+1: |
f32x4.pmax |
0xeb |
:question: |
:+1: |
f64x2 Op |
Opcode |
Old Backend Status |
VCode Status |
f64x2.ceil |
0xdc |
:question: |
@jlb6740 |
f64x2.floor |
0xdd |
:question: |
@jlb6740 |
f64x2.trunc |
0xde |
:question: |
@jlb6740 |
f64x2.nearest |
0xdf |
:question: |
@jlb6740 |
f64x2.abs |
0xec |
:+1: |
:+1: |
f64x2.neg |
0xed |
:+1: |
:+1: |
---- round ---- |
0xee |
-- |
|
f64x2.sqrt |
0xef |
:+1: |
:+1: |
f64x2.add |
0xf0 |
:+1: |
:+1: |
f64x2.sub |
0xf1 |
:+1: |
:+1: |
f64x2.mul |
0xf2 |
:+1: |
:+1: |
f64x2.div |
0xf3 |
:+1: |
:+1: |
f64x2.min |
0xf4 |
:+1: |
:+1: |
f64x2.max |
0xf5 |
:+1: |
:+1: |
f64x2.pmin |
0xf6 |
:question: |
:+1: |
f64x2.pmax |
0xf7 |
:question: |
:+1: |
Conversion Op |
Opcode |
Old Backend Status |
VCode Status |
i32x4.trunc_sat_f32x4_s |
0xf8 |
:question: |
:+1: |
i32x4.trunc_sat_f32x4_u |
0xf9 |
:question: |
:+1: |
f32x4.convert_i32x4_s |
0xfa |
:+1: |
:+1: |
f32x4.convert_i32x4_u |
0xfb |
:question: |
:+1: |
jlb6740 edited Issue #2272:
Last Update: 10/28/2020
Loads |
Opcode |
Old Backend Status |
VCode Status |
v128.load |
0x00 |
:+1: |
:+1: |
v128.load8x8_s |
0x01 |
:+1: |
@jlb6740 |
v128.load8x8_u |
0x02 |
:+1: |
@jlb6740 |
v128.load16x4_s |
0x03 |
:+1: |
@jlb6740 |
v128.load16x4_u |
0x04 |
:+1: |
@jlb6740 |
v128.load32x2_s |
0x05 |
:+1: |
@jlb6740 |
v128.load32x2_u |
0x06 |
:+1: |
@jlb6740 |
v128.load8_splat |
0x07 |
:+1: |
@jlb6740 |
v128.load16_splat |
0x08 |
:+1: |
@jlb6740 |
v128.load32_splat |
0x09 |
:+1: |
@jlb6740 |
v128.load64_splat |
0x0a |
:+1: |
@jlb6740 |
Stores |
Opcode |
Old Backend Status |
VCode Status |
v128.store |
0x0b |
:+1: |
:+1: |
Basic operation |
Opcode |
Old Backend Status |
VCode Status |
v128.const |
0x0c |
:+1: |
:+1: |
i8x16.shuffle |
0x0d |
:+1: |
:+1: |
i8x16.swizzle |
0x0e |
:+1: |
:+1: |
Splat operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.splat |
0x0f |
:+1: |
:+1: |
i16x8.splat |
0x10 |
:+1: |
:+1: |
i32x4.splat |
0x11 |
:+1: |
:+1: |
i64x2.splat |
0x12 |
:+1: |
:+1: |
f32x4.splat |
0x13 |
:+1: |
:+1: |
f64x2.splat |
0x14 |
:+1: |
:+1: |
Lane operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.extract_lane_s |
0x15 |
:+1: |
:+1: |
i8x16.extract_lane_u |
0x16 |
:+1: |
:+1: |
i8x16.replace_lane |
0x17 |
:+1: |
:+1: |
i16x8.extract_lane_s |
0x18 |
:+1: |
:+1: |
i16x8.extract_lane_u |
0x19 |
:+1: |
:+1: |
i16x8.replace_lane |
0x1a |
:+1: |
:+1: |
i32x4.extract_lane |
0x1b |
:+1: |
:+1: |
i32x4.replace_lane |
0x1c |
:+1: |
:+1: |
i64x2.extract_lane |
0x1d |
:+1: |
:+1: |
i64x2.replace_lane |
0x1e |
:+1: |
:+1: |
f32x4.extract_lane |
0x1f |
:+1: |
:+1: |
f32x4.replace_lane |
0x20 |
:+1: |
:+1: |
f64x2.extract_lane |
0x21 |
:+1: |
:+1: |
f64x2.replace_lane |
0x22 |
:+1: |
:+1: |
Integer Cmp |
Opcode |
Old Backend Status |
VCode Status |
i8x16.eq |
0x23 |
:+1: |
:+1: |
i8x16.ne |
0x24 |
:+1: |
:+1: |
i8x16.lt_s |
0x25 |
:+1: |
:+1: |
i8x16.lt_u |
0x26 |
:+1: |
:+1: |
i8x16.gt_s |
0x27 |
:+1: |
:+1: |
i8x16.gt_u |
0x28 |
:+1: |
:+1: |
i8x16.le_s |
0x29 |
:+1: |
:+1: |
i8x16.le_u |
0x2a |
:+1: |
:+1: |
i8x16.ge_s |
0x2b |
:+1: |
:+1: |
i8x16.ge_u |
0x2c |
:+1: |
:+1: |
i16x8.eq |
0x2d |
:+1: |
:+1: |
i16x8.ne |
0x2e |
:+1: |
:+1: |
i16x8.lt_s |
0x2f |
:+1: |
:+1: |
i16x8.lt_u |
0x30 |
:+1: |
:+1: |
i16x8.gt_s |
0x31 |
:+1: |
:+1: |
i16x8.gt_u |
0x32 |
:+1: |
:+1: |
i16x8.le_s |
0x33 |
:+1: |
:+1: |
i16x8.le_u |
0x34 |
:+1: |
:+1: |
i16x8.ge_s |
0x35 |
:+1: |
:+1: |
i16x8.ge_u |
0x36 |
:+1: |
:+1: |
i32x4.eq |
0x37 |
:+1: |
:+1: |
i32x4.ne |
0x38 |
:+1: |
:+1: |
i32x4.lt_s |
0x39 |
:+1: |
:+1: |
i32x4.lt_u |
0x3a |
:+1: |
:+1: |
i32x4.gt_s |
0x3b |
:+1: |
:+1: |
i32x4.gt_u |
0x3c |
:+1: |
:+1: |
i32x4.le_s |
0x3d |
:+1: |
:+1: |
i32x4.le_u |
0x3e |
:+1: |
:+1: |
i32x4.ge_s |
0x3f |
:+1: |
:+1: |
i32x4.ge_u |
0x40 |
:+1: |
:+1: |
Float Cmp |
Opcode |
Old Backend Status |
VCode Status |
f32x4.eq |
0x41 |
:+1: |
:+1: |
f32x4.ne |
0x42 |
:+1: |
:+1: |
f32x4.lt |
0x43 |
:+1: |
:+1: |
f32x4.gt |
0x44 |
:+1: |
:+1: |
f32x4.le |
0x45 |
:+1: |
:+1: |
f32x4.ge |
0x46 |
:+1: |
:+1: |
f64x2.eq |
0x47 |
:+1: |
:+1: |
f64x2.ne |
0x48 |
:+1: |
:+1: |
f64x2.lt |
0x49 |
:+1: |
:+1: |
f64x2.gt |
0x4a |
:+1: |
:+1: |
f64x2.le |
0x4b |
:+1: |
:+1: |
f64x2.ge |
0x4c |
:+1: |
:+1: |
v128 Op |
Opcode |
Old Backend Status |
VCode Status |
v128.not |
0x4d |
:+1: |
:+1: |
v128.and |
0x4e |
:+1: |
:+1: |
v128.andnot |
0x4f |
:+1: |
:+1: |
v128.or |
0x50 |
:+1: |
:+1: |
v128.xor |
0x51 |
:+1: |
:+1: |
v128.bitselect |
0x52 |
:+1: |
:+1: |
i8x16 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i8x16.abs |
0x60 |
:+1: |
:+1: |
i8x16.neg |
0x61 |
:+1: |
:+1: |
i8x16.any_true |
0x62 |
:+1: |
:+1: |
i8x16.all_true |
0x63 |
:+1: |
:+1: |
i8x16.bitmask |
0x64 |
:question: |
:+1: |
i8x16.narrow_i16x8_s |
0x65 |
:+1: |
:+1: |
i8x16.narrow_i16x8_u |
0x66 |
:+1: |
:+1: |
---- widen ---- |
0x67 |
-- |
|
---- widen ---- |
0x68 |
-- |
|
---- widen ---- |
0x69 |
-- |
|
---- widen ---- |
0x6a |
-- |
|
i8x16.shl |
0x6b |
:+1: |
:+1: |
i8x16.shr_s |
0x6c |
:+1: |
:+1: |
i8x16.shr_u |
0x6d |
:+1: |
:+1: |
i8x16.add |
0x6e |
:+1: |
:+1: |
i8x16.add_sat_s |
0x6f |
:+1: |
:+1: |
i8x16.add_sat_u |
0x70 |
:+1: |
:+1: |
i8x16.sub |
0x71 |
:+1: |
:+1: |
i8x16.sub_sat_s |
0x72 |
:+1: |
:+1: |
i8x16.sub_sat_u |
0x73 |
:+1: |
:+1: |
---- dot ---- |
0x74 |
-- |
|
---- mul ---- |
0x75 |
:question: |
|
i8x16.min_s |
0x76 |
:+1: |
:+1: |
i8x16.min_u |
0x77 |
:+1: |
:+1: |
i8x16.max_s |
0x78 |
:+1: |
:+1: |
i8x16.max_u |
0x79 |
:+1: |
:+1: |
---- avgr_s ---- |
0x7a |
-- |
|
i8x16.avgr_u |
0x7b |
:+1: |
:+1: |
i16x8 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i16x8.abs |
0x80 |
:+1: |
:+1: |
i16x8.neg |
0x81 |
:+1: |
:+1: |
i16x8.any_true |
0x82 |
:+1: |
:+1: |
i16x8.all_true |
0x83 |
:+1: |
:+1: |
i16x8.bitmask |
0x84 |
:question: |
:+1: |
i16x8.narrow_i32x4_s |
0x85 |
:+1: |
:+1: |
i16x8.narrow_i32x4_u |
0x86 |
:+1: |
:+1: |
i16x8.widen_low_i8x16_s |
0x87 |
:+1: |
:+1: |
i16x8.widen_high_i8x16_s |
0x88 |
:+1: |
:+1: |
i16x8.widen_low_i8x16_u |
0x89 |
:+1: |
:+1: |
i16x8.widen_high_i8x16_u |
0x8a |
:+1: |
:+1: |
i16x8.shl |
0x8b |
:+1: |
:+1: |
i16x8.shr_s |
0x8c |
:+1: |
:+1: |
i16x8.shr_u |
0x8d |
:+1: |
:+1: |
i16x8.add |
0x8e |
:+1: |
:+1: |
i16x8.add_sat_s |
0x8f |
:+1: |
:+1: |
i16x8.add_sat_u |
0x90 |
:+1: |
:+1: |
i16x8.sub |
0x91 |
:+1: |
:+1: |
i16x8.sub_sat_s |
0x92 |
:+1: |
:+1: |
i16x8.sub_sat_u |
0x93 |
:+1: |
:+1: |
---- dot ---- |
0x94 |
-- |
|
i16x8.mul |
0x95 |
:+1: |
:+1: |
i16x8.min_s |
0x96 |
:+1: |
:+1: |
i16x8.min_u |
0x97 |
:+1: |
:+1: |
i16x8.max_s |
0x98 |
:+1: |
:+1: |
i16x8.max_u |
0x99 |
:+1: |
:+1: |
---- avgr_s ---- |
0x9a |
-- |
|
i16x8.avgr_u |
0x9b |
:+1: |
:+1: |
i32x4 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i32x4.abs |
0xa0 |
:+1: |
:+1: |
i32x4.neg |
0xa1 |
:+1: |
:+1: |
i32x4.any_true |
0xa2 |
:+1: |
:+1: |
i32x4.all_true |
0xa3 |
:+1: |
:+1: |
i32x4.bitmask |
0xa4 |
:question: |
:+1: |
---- narrow ---- |
0xa5 |
-- |
|
---- narrow ---- |
0xa6 |
-- |
|
i32x4.widen_low_i16x8_s |
0xa7 |
:+1: |
:+1: |
i32x4.widen_high_i16x8_s |
0xa8 |
:+1: |
:+1: |
i32x4.widen_low_i16x8_u |
0xa9 |
:+1: |
:+1: |
i32x4.widen_high_i16x8_u |
0xaa |
:+1: |
:+1: |
i32x4.shl |
0xab |
:+1: |
:+1: |
i32x4.shr_s |
0xac |
:+1: |
:+1: |
i32x4.shr_u |
0xad |
:+1: |
:+1: |
i32x4.add |
0xae |
:+1: |
:+1: |
---- add_sat ---- |
0xaf |
-- |
|
---- add_sat ---- |
0xb0 |
-- |
|
i32x4.sub |
0xb1 |
:+1: |
:+1: |
---- sub_sat ---- |
0xb2 |
-- |
|
---- sub_sat ---- |
0xb3 |
-- |
|
---- dot ---- |
0xb4 |
-- |
|
i32x4.mul |
0xb5 |
:+1: |
:+1: |
i32x4.min_s |
0xb6 |
:+1: |
:+1: |
i32x4.min_u |
0xb7 |
:+1: |
:+1: |
i32x4.max_s |
0xb8 |
:+1: |
:+1: |
i32x4.max_u |
0xb9 |
:+1: |
:+1: |
---- avgr_s ---- |
0xba |
-- |
|
---- avgr_u ---- |
0xbb |
-- |
|
i64x2 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
---- |
0xc0 |
-- |
|
i64x2.neg |
0xc1 |
:+1: |
:+1: |
---- |
0xc2 |
-- |
|
---- |
0xc3 |
-- |
|
---- |
0xc4 |
-- |
|
---- |
0xc5 |
-- |
|
---- |
0xc6 |
-- |
|
---- |
0xc7 |
-- |
|
---- |
0xc8 |
-- |
|
---- |
0xc9 |
-- |
|
---- |
0xca |
-- |
|
i64x2.shl |
0xcb |
:+1: |
:+1: |
i64x2.shr_s |
0xcc |
:+1: |
:+1: |
i64x2.shr_u |
0xcd |
:+1: |
:+1: |
i64x2.add |
0xce |
:+1: |
:+1: |
---- |
0xcf |
-- |
|
---- |
0xd0 |
-- |
|
i64x2.sub |
0xd1 |
:+1: |
:+1: |
---- |
0xd2 |
-- |
|
---- |
0xd3 |
-- |
|
---- |
0xd4 |
-- |
|
i64x2.mul |
0xd5 |
:+1: |
:+1: |
---- |
0xd6 |
-- |
|
---- |
0xd7 |
-- |
|
f32x4 Op |
Opcode |
Old Backend Status |
VCode Status |
f32x4.ceil |
0xd8 |
:question: |
:+1: |
f32x4.floor |
0xd9 |
:question: |
:+1: |
f32x4.trunc |
0xda |
:question: |
:+1: |
f32x4.nearest |
0xdb |
:question: |
:+1: |
f32x4.abs |
0xe0 |
:+1: |
:+1: |
f32x4.neg |
0xe1 |
:+1: |
:+1: |
---- round ---- |
0xe2 |
-- |
|
f32x4.sqrt |
0xe3 |
:+1: |
:+1: |
f32x4.add |
0xe4 |
:+1: |
:+1: |
f32x4.sub |
0xe5 |
:+1: |
:+1: |
f32x4.mul |
0xe6 |
:+1: |
:+1: |
f32x4.div |
0xe7 |
:+1: |
:+1: |
f32x4.min |
0xe8 |
:+1: |
:+1: |
f32x4.max |
0xe9 |
:+1: |
:+1: |
f32x4.pmin |
0xea |
:question: |
:+1: |
f32x4.pmax |
0xeb |
:question: |
:+1: |
f64x2 Op |
Opcode |
Old Backend Status |
VCode Status |
f64x2.ceil |
0xdc |
:question: |
:+1: |
f64x2.floor |
0xdd |
:question: |
:+1: |
f64x2.trunc |
0xde |
:question: |
:+1: |
f64x2.nearest |
0xdf |
:question: |
:+1: |
f64x2.abs |
0xec |
:+1: |
:+1: |
f64x2.neg |
0xed |
:+1: |
:+1: |
---- round ---- |
0xee |
-- |
|
f64x2.sqrt |
0xef |
:+1: |
:+1: |
f64x2.add |
0xf0 |
:+1: |
:+1: |
f64x2.sub |
0xf1 |
:+1: |
:+1: |
f64x2.mul |
0xf2 |
:+1: |
:+1: |
f64x2.div |
0xf3 |
:+1: |
:+1: |
f64x2.min |
0xf4 |
:+1: |
:+1: |
f64x2.max |
0xf5 |
:+1: |
:+1: |
f64x2.pmin |
0xf6 |
:question: |
:+1: |
f64x2.pmax |
0xf7 |
:question: |
:+1: |
Conversion Op |
Opcode |
Old Backend Status |
VCode Status |
i32x4.trunc_sat_f32x4_s |
0xf8 |
:question: |
:+1: |
i32x4.trunc_sat_f32x4_u |
0xf9 |
:question: |
:+1: |
f32x4.convert_i32x4_s |
0xfa |
:+1: |
:+1: |
f32x4.convert_i32x4_u |
0xfb |
:question: |
:+1: |
jlb6740 edited Issue #2272:
Last Update: 12/03/2020
Loads |
Opcode |
Old Backend Status |
VCode Status |
v128.load |
0x00 |
:+1: |
:+1: |
v128.load8x8_s |
0x01 |
:+1: |
@jlb6740 |
v128.load8x8_u |
0x02 |
:+1: |
@jlb6740 |
v128.load16x4_s |
0x03 |
:+1: |
@jlb6740 |
v128.load16x4_u |
0x04 |
:+1: |
@jlb6740 |
v128.load32x2_s |
0x05 |
:+1: |
@jlb6740 |
v128.load32x2_u |
0x06 |
:+1: |
@jlb6740 |
v128.load8_splat |
0x07 |
:+1: |
@jlb6740 |
v128.load16_splat |
0x08 |
:+1: |
@jlb6740 |
v128.load32_splat |
0x09 |
:+1: |
@jlb6740 |
v128.load64_splat |
0x0a |
:+1: |
@jlb6740 |
Stores |
Opcode |
Old Backend Status |
VCode Status |
v128.store |
0x0b |
:+1: |
:+1: |
Basic operation |
Opcode |
Old Backend Status |
VCode Status |
v128.const |
0x0c |
:+1: |
:+1: |
i8x16.shuffle |
0x0d |
:+1: |
:+1: |
i8x16.swizzle |
0x0e |
:+1: |
:+1: |
Splat operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.splat |
0x0f |
:+1: |
:+1: |
i16x8.splat |
0x10 |
:+1: |
:+1: |
i32x4.splat |
0x11 |
:+1: |
:+1: |
i64x2.splat |
0x12 |
:+1: |
:+1: |
f32x4.splat |
0x13 |
:+1: |
:+1: |
f64x2.splat |
0x14 |
:+1: |
:+1: |
Lane operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.extract_lane_s |
0x15 |
:+1: |
:+1: |
i8x16.extract_lane_u |
0x16 |
:+1: |
:+1: |
i8x16.replace_lane |
0x17 |
:+1: |
:+1: |
i16x8.extract_lane_s |
0x18 |
:+1: |
:+1: |
i16x8.extract_lane_u |
0x19 |
:+1: |
:+1: |
i16x8.replace_lane |
0x1a |
:+1: |
:+1: |
i32x4.extract_lane |
0x1b |
:+1: |
:+1: |
i32x4.replace_lane |
0x1c |
:+1: |
:+1: |
i64x2.extract_lane |
0x1d |
:+1: |
:+1: |
i64x2.replace_lane |
0x1e |
:+1: |
:+1: |
f32x4.extract_lane |
0x1f |
:+1: |
:+1: |
f32x4.replace_lane |
0x20 |
:+1: |
:+1: |
f64x2.extract_lane |
0x21 |
:+1: |
:+1: |
f64x2.replace_lane |
0x22 |
:+1: |
:+1: |
Integer Cmp |
Opcode |
Old Backend Status |
VCode Status |
i8x16.eq |
0x23 |
:+1: |
:+1: |
i8x16.ne |
0x24 |
:+1: |
:+1: |
i8x16.lt_s |
0x25 |
:+1: |
:+1: |
i8x16.lt_u |
0x26 |
:+1: |
:+1: |
i8x16.gt_s |
0x27 |
:+1: |
:+1: |
i8x16.gt_u |
0x28 |
:+1: |
:+1: |
i8x16.le_s |
0x29 |
:+1: |
:+1: |
i8x16.le_u |
0x2a |
:+1: |
:+1: |
i8x16.ge_s |
0x2b |
:+1: |
:+1: |
i8x16.ge_u |
0x2c |
:+1: |
:+1: |
i16x8.eq |
0x2d |
:+1: |
:+1: |
i16x8.ne |
0x2e |
:+1: |
:+1: |
i16x8.lt_s |
0x2f |
:+1: |
:+1: |
i16x8.lt_u |
0x30 |
:+1: |
:+1: |
i16x8.gt_s |
0x31 |
:+1: |
:+1: |
i16x8.gt_u |
0x32 |
:+1: |
:+1: |
i16x8.le_s |
0x33 |
:+1: |
:+1: |
i16x8.le_u |
0x34 |
:+1: |
:+1: |
i16x8.ge_s |
0x35 |
:+1: |
:+1: |
i16x8.ge_u |
0x36 |
:+1: |
:+1: |
i32x4.eq |
0x37 |
:+1: |
:+1: |
i32x4.ne |
0x38 |
:+1: |
:+1: |
i32x4.lt_s |
0x39 |
:+1: |
:+1: |
i32x4.lt_u |
0x3a |
:+1: |
:+1: |
i32x4.gt_s |
0x3b |
:+1: |
:+1: |
i32x4.gt_u |
0x3c |
:+1: |
:+1: |
i32x4.le_s |
0x3d |
:+1: |
:+1: |
i32x4.le_u |
0x3e |
:+1: |
:+1: |
i32x4.ge_s |
0x3f |
:+1: |
:+1: |
i32x4.ge_u |
0x40 |
:+1: |
:+1: |
Float Cmp |
Opcode |
Old Backend Status |
VCode Status |
f32x4.eq |
0x41 |
:+1: |
:+1: |
f32x4.ne |
0x42 |
:+1: |
:+1: |
f32x4.lt |
0x43 |
:+1: |
:+1: |
f32x4.gt |
0x44 |
:+1: |
:+1: |
f32x4.le |
0x45 |
:+1: |
:+1: |
f32x4.ge |
0x46 |
:+1: |
:+1: |
f64x2.eq |
0x47 |
:+1: |
:+1: |
f64x2.ne |
0x48 |
:+1: |
:+1: |
f64x2.lt |
0x49 |
:+1: |
:+1: |
f64x2.gt |
0x4a |
:+1: |
:+1: |
f64x2.le |
0x4b |
:+1: |
:+1: |
f64x2.ge |
0x4c |
:+1: |
:+1: |
v128 Op |
Opcode |
Old Backend Status |
VCode Status |
v128.not |
0x4d |
:+1: |
:+1: |
v128.and |
0x4e |
:+1: |
:+1: |
v128.andnot |
0x4f |
:+1: |
:+1: |
v128.or |
0x50 |
:+1: |
:+1: |
v128.xor |
0x51 |
:+1: |
:+1: |
v128.bitselect |
0x52 |
:+1: |
:+1: |
i8x16 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i8x16.abs |
0x60 |
:+1: |
:+1: |
i8x16.neg |
0x61 |
:+1: |
:+1: |
i8x16.any_true |
0x62 |
:+1: |
:+1: |
i8x16.all_true |
0x63 |
:+1: |
:+1: |
i8x16.bitmask |
0x64 |
:question: |
:+1: |
i8x16.narrow_i16x8_s |
0x65 |
:+1: |
:+1: |
i8x16.narrow_i16x8_u |
0x66 |
:+1: |
:+1: |
---- widen ---- |
0x67 |
-- |
|
---- widen ---- |
0x68 |
-- |
|
---- widen ---- |
0x69 |
-- |
|
---- widen ---- |
0x6a |
-- |
|
i8x16.shl |
0x6b |
:+1: |
:+1: |
i8x16.shr_s |
0x6c |
:+1: |
:+1: |
i8x16.shr_u |
0x6d |
:+1: |
:+1: |
i8x16.add |
0x6e |
:+1: |
:+1: |
i8x16.add_sat_s |
0x6f |
:+1: |
:+1: |
i8x16.add_sat_u |
0x70 |
:+1: |
:+1: |
i8x16.sub |
0x71 |
:+1: |
:+1: |
i8x16.sub_sat_s |
0x72 |
:+1: |
:+1: |
i8x16.sub_sat_u |
0x73 |
:+1: |
:+1: |
---- dot ---- |
0x74 |
-- |
|
---- mul ---- |
0x75 |
:question: |
|
i8x16.min_s |
0x76 |
:+1: |
:+1: |
i8x16.min_u |
0x77 |
:+1: |
:+1: |
i8x16.max_s |
0x78 |
:+1: |
:+1: |
i8x16.max_u |
0x79 |
:+1: |
:+1: |
---- avgr_s ---- |
0x7a |
-- |
|
i8x16.avgr_u |
0x7b |
:+1: |
:+1: |
i16x8 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i16x8.abs |
0x80 |
:+1: |
:+1: |
i16x8.neg |
0x81 |
:+1: |
:+1: |
i16x8.any_true |
0x82 |
:+1: |
:+1: |
i16x8.all_true |
0x83 |
:+1: |
:+1: |
i16x8.bitmask |
0x84 |
:question: |
:+1: |
i16x8.narrow_i32x4_s |
0x85 |
:+1: |
:+1: |
i16x8.narrow_i32x4_u |
0x86 |
:+1: |
:+1: |
i16x8.widen_low_i8x16_s |
0x87 |
:+1: |
:+1: |
i16x8.widen_high_i8x16_s |
0x88 |
:+1: |
:+1: |
i16x8.widen_low_i8x16_u |
0x89 |
:+1: |
:+1: |
i16x8.widen_high_i8x16_u |
0x8a |
:+1: |
:+1: |
i16x8.shl |
0x8b |
:+1: |
:+1: |
i16x8.shr_s |
0x8c |
:+1: |
:+1: |
i16x8.shr_u |
0x8d |
:+1: |
:+1: |
i16x8.add |
0x8e |
:+1: |
:+1: |
i16x8.add_sat_s |
0x8f |
:+1: |
:+1: |
i16x8.add_sat_u |
0x90 |
:+1: |
:+1: |
i16x8.sub |
0x91 |
:+1: |
:+1: |
i16x8.sub_sat_s |
0x92 |
:+1: |
:+1: |
i16x8.sub_sat_u |
0x93 |
:+1: |
:+1: |
---- dot ---- |
0x94 |
-- |
|
i16x8.mul |
0x95 |
:+1: |
:+1: |
i16x8.min_s |
0x96 |
:+1: |
:+1: |
i16x8.min_u |
0x97 |
:+1: |
:+1: |
i16x8.max_s |
0x98 |
:+1: |
:+1: |
i16x8.max_u |
0x99 |
:+1: |
:+1: |
---- avgr_s ---- |
0x9a |
-- |
|
i16x8.avgr_u |
0x9b |
:+1: |
:+1: |
i32x4 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i32x4.abs |
0xa0 |
:+1: |
:+1: |
i32x4.neg |
0xa1 |
:+1: |
:+1: |
i32x4.any_true |
0xa2 |
:+1: |
:+1: |
i32x4.all_true |
0xa3 |
:+1: |
:+1: |
i32x4.bitmask |
0xa4 |
:question: |
:+1: |
---- narrow ---- |
0xa5 |
-- |
|
---- narrow ---- |
0xa6 |
-- |
|
i32x4.widen_low_i16x8_s |
0xa7 |
:+1: |
:+1: |
i32x4.widen_high_i16x8_s |
0xa8 |
:+1: |
:+1: |
i32x4.widen_low_i16x8_u |
0xa9 |
:+1: |
:+1: |
i32x4.widen_high_i16x8_u |
0xaa |
:+1: |
:+1: |
i32x4.shl |
0xab |
:+1: |
:+1: |
i32x4.shr_s |
0xac |
:+1: |
:+1: |
i32x4.shr_u |
0xad |
:+1: |
:+1: |
i32x4.add |
0xae |
:+1: |
:+1: |
---- add_sat ---- |
0xaf |
-- |
|
---- add_sat ---- |
0xb0 |
-- |
|
i32x4.sub |
0xb1 |
:+1: |
:+1: |
---- sub_sat ---- |
0xb2 |
-- |
|
---- sub_sat ---- |
0xb3 |
-- |
|
---- dot ---- |
0xb4 |
-- |
|
i32x4.mul |
0xb5 |
:+1: |
:+1: |
i32x4.min_s |
0xb6 |
:+1: |
:+1: |
i32x4.min_u |
0xb7 |
:+1: |
:+1: |
i32x4.max_s |
0xb8 |
:+1: |
:+1: |
i32x4.max_u |
0xb9 |
:+1: |
:+1: |
---- avgr_s ---- |
0xba |
-- |
|
---- avgr_u ---- |
0xbb |
-- |
|
i64x2 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
---- |
0xc0 |
-- |
|
i64x2.neg |
0xc1 |
:+1: |
:+1: |
---- |
0xc2 |
-- |
|
---- |
0xc3 |
-- |
|
---- |
0xc4 |
-- |
|
---- |
0xc5 |
-- |
|
---- |
0xc6 |
-- |
|
---- |
0xc7 |
-- |
|
---- |
0xc8 |
-- |
|
---- |
0xc9 |
-- |
|
---- |
0xca |
-- |
|
i64x2.shl |
0xcb |
:+1: |
:+1: |
i64x2.shr_s |
0xcc |
:+1: |
:+1: |
i64x2.shr_u |
0xcd |
:+1: |
:+1: |
i64x2.add |
0xce |
:+1: |
:+1: |
---- |
0xcf |
-- |
|
---- |
0xd0 |
-- |
|
i64x2.sub |
0xd1 |
:+1: |
:+1: |
---- |
0xd2 |
-- |
|
---- |
0xd3 |
-- |
|
---- |
0xd4 |
-- |
|
i64x2.mul |
0xd5 |
:+1: |
:+1: |
---- |
0xd6 |
-- |
|
---- |
0xd7 |
-- |
|
f32x4 Op |
Opcode |
Old Backend Status |
VCode Status |
f32x4.ceil |
0xd8 |
:question: |
:+1: |
f32x4.floor |
0xd9 |
:question: |
:+1: |
f32x4.trunc |
0xda |
:question: |
:+1: |
f32x4.nearest |
0xdb |
:question: |
:+1: |
f32x4.abs |
0xe0 |
:+1: |
:+1: |
f32x4.neg |
0xe1 |
:+1: |
:+1: |
---- round ---- |
0xe2 |
-- |
|
f32x4.sqrt |
0xe3 |
:+1: |
:+1: |
f32x4.add |
0xe4 |
:+1: |
:+1: |
f32x4.sub |
0xe5 |
:+1: |
:+1: |
f32x4.mul |
0xe6 |
:+1: |
:+1: |
f32x4.div |
0xe7 |
:+1: |
:+1: |
f32x4.min |
0xe8 |
:+1: |
:+1: |
f32x4.max |
0xe9 |
:+1: |
:+1: |
f32x4.pmin |
0xea |
:question: |
:+1: |
f32x4.pmax |
0xeb |
:question: |
:+1: |
f64x2 Op |
Opcode |
Old Backend Status |
VCode Status |
f64x2.ceil |
0xdc |
:question: |
:+1: |
f64x2.floor |
0xdd |
:question: |
:+1: |
f64x2.trunc |
0xde |
:question: |
:+1: |
f64x2.nearest |
0xdf |
:question: |
:+1: |
f64x2.abs |
0xec |
:+1: |
:+1: |
f64x2.neg |
0xed |
:+1: |
:+1: |
---- round ---- |
0xee |
-- |
|
f64x2.sqrt |
0xef |
:+1: |
:+1: |
f64x2.add |
0xf0 |
:+1: |
:+1: |
f64x2.sub |
0xf1 |
:+1: |
:+1: |
f64x2.mul |
0xf2 |
:+1: |
:+1: |
f64x2.div |
0xf3 |
:+1: |
:+1: |
f64x2.min |
0xf4 |
:+1: |
:+1: |
f64x2.max |
0xf5 |
:+1: |
:+1: |
f64x2.pmin |
0xf6 |
:question: |
:+1: |
f64x2.pmax |
0xf7 |
:question: |
:+1: |
Conversion Op |
Opcode |
Old Backend Status |
VCode Status |
i32x4.trunc_sat_f32x4_s |
0xf8 |
:question: |
:+1: |
i32x4.trunc_sat_f32x4_u |
0xf9 |
:question: |
:+1: |
f32x4.convert_i32x4_s |
0xfa |
:+1: |
:+1: |
f32x4.convert_i32x4_u |
0xfb |
:question: |
:+1: |
abrown edited Issue #2272:
Last Update: 12/03/2020
Loads |
Opcode |
Old Backend Status |
VCode Status |
v128.load |
0x00 |
:+1: |
:+1: |
v128.load32_zero |
0xfc |
-- |
@abrown |
v128.load64_zero |
0xfd |
-- |
@abrown |
v128.load8x8_s |
0x01 |
:+1: |
@jlb6740 |
v128.load8x8_u |
0x02 |
:+1: |
@jlb6740 |
v128.load16x4_s |
0x03 |
:+1: |
@jlb6740 |
v128.load16x4_u |
0x04 |
:+1: |
@jlb6740 |
v128.load32x2_s |
0x05 |
:+1: |
@jlb6740 |
v128.load32x2_u |
0x06 |
:+1: |
@jlb6740 |
v128.load8_splat |
0x07 |
:+1: |
@jlb6740 |
v128.load16_splat |
0x08 |
:+1: |
@jlb6740 |
v128.load32_splat |
0x09 |
:+1: |
@jlb6740 |
v128.load64_splat |
0x0a |
:+1: |
@jlb6740 |
Stores |
Opcode |
Old Backend Status |
VCode Status |
v128.store |
0x0b |
:+1: |
:+1: |
Basic operation |
Opcode |
Old Backend Status |
VCode Status |
v128.const |
0x0c |
:+1: |
:+1: |
i8x16.shuffle |
0x0d |
:+1: |
:+1: |
i8x16.swizzle |
0x0e |
:+1: |
:+1: |
Splat operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.splat |
0x0f |
:+1: |
:+1: |
i16x8.splat |
0x10 |
:+1: |
:+1: |
i32x4.splat |
0x11 |
:+1: |
:+1: |
i64x2.splat |
0x12 |
:+1: |
:+1: |
f32x4.splat |
0x13 |
:+1: |
:+1: |
f64x2.splat |
0x14 |
:+1: |
:+1: |
Lane operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.extract_lane_s |
0x15 |
:+1: |
:+1: |
i8x16.extract_lane_u |
0x16 |
:+1: |
:+1: |
i8x16.replace_lane |
0x17 |
:+1: |
:+1: |
i16x8.extract_lane_s |
0x18 |
:+1: |
:+1: |
i16x8.extract_lane_u |
0x19 |
:+1: |
:+1: |
i16x8.replace_lane |
0x1a |
:+1: |
:+1: |
i32x4.extract_lane |
0x1b |
:+1: |
:+1: |
i32x4.replace_lane |
0x1c |
:+1: |
:+1: |
i64x2.extract_lane |
0x1d |
:+1: |
:+1: |
i64x2.replace_lane |
0x1e |
:+1: |
:+1: |
f32x4.extract_lane |
0x1f |
:+1: |
:+1: |
f32x4.replace_lane |
0x20 |
:+1: |
:+1: |
f64x2.extract_lane |
0x21 |
:+1: |
:+1: |
f64x2.replace_lane |
0x22 |
:+1: |
:+1: |
Integer Cmp |
Opcode |
Old Backend Status |
VCode Status |
i8x16.eq |
0x23 |
:+1: |
:+1: |
i8x16.ne |
0x24 |
:+1: |
:+1: |
i8x16.lt_s |
0x25 |
:+1: |
:+1: |
i8x16.lt_u |
0x26 |
:+1: |
:+1: |
i8x16.gt_s |
0x27 |
:+1: |
:+1: |
i8x16.gt_u |
0x28 |
:+1: |
:+1: |
i8x16.le_s |
0x29 |
:+1: |
:+1: |
i8x16.le_u |
0x2a |
:+1: |
:+1: |
i8x16.ge_s |
0x2b |
:+1: |
:+1: |
i8x16.ge_u |
0x2c |
:+1: |
:+1: |
i16x8.eq |
0x2d |
:+1: |
:+1: |
i16x8.ne |
0x2e |
:+1: |
:+1: |
i16x8.lt_s |
0x2f |
:+1: |
:+1: |
i16x8.lt_u |
0x30 |
:+1: |
:+1: |
i16x8.gt_s |
0x31 |
:+1: |
:+1: |
i16x8.gt_u |
0x32 |
:+1: |
:+1: |
i16x8.le_s |
0x33 |
:+1: |
:+1: |
i16x8.le_u |
0x34 |
:+1: |
:+1: |
i16x8.ge_s |
0x35 |
:+1: |
:+1: |
i16x8.ge_u |
0x36 |
:+1: |
:+1: |
i32x4.eq |
0x37 |
:+1: |
:+1: |
i32x4.ne |
0x38 |
:+1: |
:+1: |
i32x4.lt_s |
0x39 |
:+1: |
:+1: |
i32x4.lt_u |
0x3a |
:+1: |
:+1: |
i32x4.gt_s |
0x3b |
:+1: |
:+1: |
i32x4.gt_u |
0x3c |
:+1: |
:+1: |
i32x4.le_s |
0x3d |
:+1: |
:+1: |
i32x4.le_u |
0x3e |
:+1: |
:+1: |
i32x4.ge_s |
0x3f |
:+1: |
:+1: |
i32x4.ge_u |
0x40 |
:+1: |
:+1: |
Float Cmp |
Opcode |
Old Backend Status |
VCode Status |
f32x4.eq |
0x41 |
:+1: |
:+1: |
f32x4.ne |
0x42 |
:+1: |
:+1: |
f32x4.lt |
0x43 |
:+1: |
:+1: |
f32x4.gt |
0x44 |
:+1: |
:+1: |
f32x4.le |
0x45 |
:+1: |
:+1: |
f32x4.ge |
0x46 |
:+1: |
:+1: |
f64x2.eq |
0x47 |
:+1: |
:+1: |
f64x2.ne |
0x48 |
:+1: |
:+1: |
f64x2.lt |
0x49 |
:+1: |
:+1: |
f64x2.gt |
0x4a |
:+1: |
:+1: |
f64x2.le |
0x4b |
:+1: |
:+1: |
f64x2.ge |
0x4c |
:+1: |
:+1: |
v128 Op |
Opcode |
Old Backend Status |
VCode Status |
v128.not |
0x4d |
:+1: |
:+1: |
v128.and |
0x4e |
:+1: |
:+1: |
v128.andnot |
0x4f |
:+1: |
:+1: |
v128.or |
0x50 |
:+1: |
:+1: |
v128.xor |
0x51 |
:+1: |
:+1: |
v128.bitselect |
0x52 |
:+1: |
:+1: |
i8x16 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i8x16.abs |
0x60 |
:+1: |
:+1: |
i8x16.neg |
0x61 |
:+1: |
:+1: |
i8x16.any_true |
0x62 |
:+1: |
:+1: |
i8x16.all_true |
0x63 |
:+1: |
:+1: |
i8x16.bitmask |
0x64 |
:question: |
:+1: |
i8x16.narrow_i16x8_s |
0x65 |
:+1: |
:+1: |
i8x16.narrow_i16x8_u |
0x66 |
:+1: |
:+1: |
---- widen ---- |
0x67 |
-- |
|
---- widen ---- |
0x68 |
-- |
|
---- widen ---- |
0x69 |
-- |
|
---- widen ---- |
0x6a |
-- |
|
i8x16.shl |
0x6b |
:+1: |
:+1: |
i8x16.shr_s |
0x6c |
:+1: |
:+1: |
i8x16.shr_u |
0x6d |
:+1: |
:+1: |
i8x16.add |
0x6e |
:+1: |
:+1: |
i8x16.add_sat_s |
0x6f |
:+1: |
:+1: |
i8x16.add_sat_u |
0x70 |
:+1: |
:+1: |
i8x16.sub |
0x71 |
:+1: |
:+1: |
i8x16.sub_sat_s |
0x72 |
:+1: |
:+1: |
i8x16.sub_sat_u |
0x73 |
:+1: |
:+1: |
---- dot ---- |
0x74 |
-- |
|
---- mul ---- |
0x75 |
:question: |
|
i8x16.min_s |
0x76 |
:+1: |
:+1: |
i8x16.min_u |
0x77 |
:+1: |
:+1: |
i8x16.max_s |
0x78 |
:+1: |
:+1: |
i8x16.max_u |
0x79 |
:+1: |
:+1: |
---- avgr_s ---- |
0x7a |
-- |
|
i8x16.avgr_u |
0x7b |
:+1: |
:+1: |
i16x8 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i16x8.abs |
0x80 |
:+1: |
:+1: |
i16x8.neg |
0x81 |
:+1: |
:+1: |
i16x8.any_true |
0x82 |
:+1: |
:+1: |
i16x8.all_true |
0x83 |
:+1: |
:+1: |
i16x8.bitmask |
0x84 |
:question: |
:+1: |
i16x8.narrow_i32x4_s |
0x85 |
:+1: |
:+1: |
i16x8.narrow_i32x4_u |
0x86 |
:+1: |
:+1: |
i16x8.widen_low_i8x16_s |
0x87 |
:+1: |
:+1: |
i16x8.widen_high_i8x16_s |
0x88 |
:+1: |
:+1: |
i16x8.widen_low_i8x16_u |
0x89 |
:+1: |
:+1: |
i16x8.widen_high_i8x16_u |
0x8a |
:+1: |
:+1: |
i16x8.shl |
0x8b |
:+1: |
:+1: |
i16x8.shr_s |
0x8c |
:+1: |
:+1: |
i16x8.shr_u |
0x8d |
:+1: |
:+1: |
i16x8.add |
0x8e |
:+1: |
:+1: |
i16x8.add_sat_s |
0x8f |
:+1: |
:+1: |
i16x8.add_sat_u |
0x90 |
:+1: |
:+1: |
i16x8.sub |
0x91 |
:+1: |
:+1: |
i16x8.sub_sat_s |
0x92 |
:+1: |
:+1: |
i16x8.sub_sat_u |
0x93 |
:+1: |
:+1: |
---- dot ---- |
0x94 |
-- |
@abrown |
i16x8.mul |
0x95 |
:+1: |
:+1: |
i16x8.min_s |
0x96 |
:+1: |
:+1: |
i16x8.min_u |
0x97 |
:+1: |
:+1: |
i16x8.max_s |
0x98 |
:+1: |
:+1: |
i16x8.max_u |
0x99 |
:+1: |
:+1: |
---- avgr_s ---- |
0x9a |
-- |
|
i16x8.avgr_u |
0x9b |
:+1: |
:+1: |
i32x4 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i32x4.abs |
0xa0 |
:+1: |
:+1: |
i32x4.neg |
0xa1 |
:+1: |
:+1: |
i32x4.any_true |
0xa2 |
:+1: |
:+1: |
i32x4.all_true |
0xa3 |
:+1: |
:+1: |
i32x4.bitmask |
0xa4 |
:question: |
:+1: |
---- narrow ---- |
0xa5 |
-- |
|
---- narrow ---- |
0xa6 |
-- |
|
i32x4.widen_low_i16x8_s |
0xa7 |
:+1: |
:+1: |
i32x4.widen_high_i16x8_s |
0xa8 |
:+1: |
:+1: |
i32x4.widen_low_i16x8_u |
0xa9 |
:+1: |
:+1: |
i32x4.widen_high_i16x8_u |
0xaa |
:+1: |
:+1: |
i32x4.shl |
0xab |
:+1: |
:+1: |
i32x4.shr_s |
0xac |
:+1: |
:+1: |
i32x4.shr_u |
0xad |
:+1: |
:+1: |
i32x4.add |
0xae |
:+1: |
:+1: |
---- add_sat ---- |
0xaf |
-- |
|
---- add_sat ---- |
0xb0 |
-- |
|
i32x4.sub |
0xb1 |
:+1: |
:+1: |
---- sub_sat ---- |
0xb2 |
-- |
|
---- sub_sat ---- |
0xb3 |
-- |
|
---- dot ---- |
0xb4 |
-- |
|
i32x4.mul |
0xb5 |
:+1: |
:+1: |
i32x4.min_s |
0xb6 |
:+1: |
:+1: |
i32x4.min_u |
0xb7 |
:+1: |
:+1: |
i32x4.max_s |
0xb8 |
:+1: |
:+1: |
i32x4.max_u |
0xb9 |
:+1: |
:+1: |
---- avgr_s ---- |
0xba |
-- |
|
---- avgr_u ---- |
0xbb |
-- |
|
i64x2 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
---- |
0xc0 |
-- |
|
i64x2.neg |
0xc1 |
:+1: |
:+1: |
---- |
0xc2 |
-- |
|
---- |
0xc3 |
-- |
|
---- |
0xc4 |
-- |
|
---- |
0xc5 |
-- |
|
---- |
0xc6 |
-- |
|
---- |
0xc7 |
-- |
|
---- |
0xc8 |
-- |
|
---- |
0xc9 |
-- |
|
---- |
0xca |
-- |
|
i64x2.shl |
0xcb |
:+1: |
:+1: |
i64x2.shr_s |
0xcc |
:+1: |
:+1: |
i64x2.shr_u |
0xcd |
:+1: |
:+1: |
i64x2.add |
0xce |
:+1: |
:+1: |
---- |
0xcf |
-- |
|
---- |
0xd0 |
-- |
|
i64x2.sub |
0xd1 |
:+1: |
:+1: |
---- |
0xd2 |
-- |
|
---- |
0xd3 |
-- |
|
---- |
0xd4 |
-- |
|
i64x2.mul |
0xd5 |
:+1: |
:+1: |
---- |
0xd6 |
-- |
|
---- |
0xd7 |
-- |
|
f32x4 Op |
Opcode |
Old Backend Status |
VCode Status |
f32x4.ceil |
0xd8 |
:question: |
:+1: |
f32x4.floor |
0xd9 |
:question: |
:+1: |
f32x4.trunc |
0xda |
:question: |
:+1: |
f32x4.nearest |
0xdb |
:question: |
:+1: |
f32x4.abs |
0xe0 |
:+1: |
:+1: |
f32x4.neg |
0xe1 |
:+1: |
:+1: |
---- round ---- |
0xe2 |
-- |
|
f32x4.sqrt |
0xe3 |
:+1: |
:+1: |
f32x4.add |
0xe4 |
:+1: |
:+1: |
f32x4.sub |
0xe5 |
:+1: |
:+1: |
f32x4.mul |
0xe6 |
:+1: |
:+1: |
f32x4.div |
0xe7 |
:+1: |
:+1: |
f32x4.min |
0xe8 |
:+1: |
:+1: |
f32x4.max |
0xe9 |
:+1: |
:+1: |
f32x4.pmin |
0xea |
:question: |
:+1: |
f32x4.pmax |
0xeb |
:question: |
:+1: |
f64x2 Op |
Opcode |
Old Backend Status |
VCode Status |
f64x2.ceil |
0xdc |
:question: |
:+1: |
f64x2.floor |
0xdd |
:question: |
:+1: |
f64x2.trunc |
0xde |
:question: |
:+1: |
f64x2.nearest |
0xdf |
:question: |
:+1: |
f64x2.abs |
0xec |
:+1: |
:+1: |
f64x2.neg |
0xed |
:+1: |
:+1: |
---- round ---- |
0xee |
-- |
|
f64x2.sqrt |
0xef |
:+1: |
:+1: |
f64x2.add |
0xf0 |
:+1: |
:+1: |
f64x2.sub |
0xf1 |
:+1: |
:+1: |
f64x2.mul |
0xf2 |
:+1: |
:+1: |
f64x2.div |
0xf3 |
:+1: |
:+1: |
f64x2.min |
0xf4 |
:+1: |
:+1: |
f64x2.max |
0xf5 |
:+1: |
:+1: |
f64x2.pmin |
0xf6 |
:question: |
:+1: |
f64x2.pmax |
0xf7 |
:question: |
:+1: |
Conversion Op |
Opcode |
Old Backend Status |
VCode Status |
i32x4.trunc_sat_f32x4_s |
0xf8 |
:question: |
:+1: |
i32x4.trunc_sat_f32x4_u |
0xf9 |
:question: |
:+1: |
f32x4.convert_i32x4_s |
0xfa |
:+1: |
:+1: |
f32x4.convert_i32x4_u |
0xfb |
:question: |
:+1: |
jlb6740 edited Issue #2272:
Last Update: 12/16/2020
Loads |
Opcode |
Old Backend Status |
VCode Status |
v128.load |
0x00 |
:+1: |
:+1: |
v128.load32_zero |
0xfc |
-- |
#2489 |
v128.load64_zero |
0xfd |
-- |
#2489 |
v128.load8x8_s |
0x01 |
:+1: |
#2510 |
v128.load8x8_u |
0x02 |
:+1: |
#2510 |
v128.load16x4_s |
0x03 |
:+1: |
#2510 |
v128.load16x4_u |
0x04 |
:+1: |
#2510 |
v128.load32x2_s |
0x05 |
:+1: |
#2510 |
v128.load32x2_u |
0x06 |
:+1: |
#2510 |
v128.load8_splat |
0x07 |
:+1: |
:+1: |
v128.load16_splat |
0x08 |
:+1: |
:+1: |
v128.load32_splat |
0x09 |
:+1: |
:+1: |
v128.load64_splat |
0x0a |
:+1: |
:+1: |
Stores |
Opcode |
Old Backend Status |
VCode Status |
v128.store |
0x0b |
:+1: |
:+1: |
Basic operation |
Opcode |
Old Backend Status |
VCode Status |
v128.const |
0x0c |
:+1: |
:+1: |
i8x16.shuffle |
0x0d |
:+1: |
:+1: |
i8x16.swizzle |
0x0e |
:+1: |
:+1: |
Splat operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.splat |
0x0f |
:+1: |
:+1: |
i16x8.splat |
0x10 |
:+1: |
:+1: |
i32x4.splat |
0x11 |
:+1: |
:+1: |
i64x2.splat |
0x12 |
:+1: |
:+1: |
f32x4.splat |
0x13 |
:+1: |
:+1: |
f64x2.splat |
0x14 |
:+1: |
:+1: |
Lane operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.extract_lane_s |
0x15 |
:+1: |
:+1: |
i8x16.extract_lane_u |
0x16 |
:+1: |
:+1: |
i8x16.replace_lane |
0x17 |
:+1: |
:+1: |
i16x8.extract_lane_s |
0x18 |
:+1: |
:+1: |
i16x8.extract_lane_u |
0x19 |
:+1: |
:+1: |
i16x8.replace_lane |
0x1a |
:+1: |
:+1: |
i32x4.extract_lane |
0x1b |
:+1: |
:+1: |
i32x4.replace_lane |
0x1c |
:+1: |
:+1: |
i64x2.extract_lane |
0x1d |
:+1: |
:+1: |
i64x2.replace_lane |
0x1e |
:+1: |
:+1: |
f32x4.extract_lane |
0x1f |
:+1: |
:+1: |
f32x4.replace_lane |
0x20 |
:+1: |
:+1: |
f64x2.extract_lane |
0x21 |
:+1: |
:+1: |
f64x2.replace_lane |
0x22 |
:+1: |
:+1: |
Integer Cmp |
Opcode |
Old Backend Status |
VCode Status |
i8x16.eq |
0x23 |
:+1: |
:+1: |
i8x16.ne |
0x24 |
:+1: |
:+1: |
i8x16.lt_s |
0x25 |
:+1: |
:+1: |
i8x16.lt_u |
0x26 |
:+1: |
:+1: |
i8x16.gt_s |
0x27 |
:+1: |
:+1: |
i8x16.gt_u |
0x28 |
:+1: |
:+1: |
i8x16.le_s |
0x29 |
:+1: |
:+1: |
i8x16.le_u |
0x2a |
:+1: |
:+1: |
i8x16.ge_s |
0x2b |
:+1: |
:+1: |
i8x16.ge_u |
0x2c |
:+1: |
:+1: |
i16x8.eq |
0x2d |
:+1: |
:+1: |
i16x8.ne |
0x2e |
:+1: |
:+1: |
i16x8.lt_s |
0x2f |
:+1: |
:+1: |
i16x8.lt_u |
0x30 |
:+1: |
:+1: |
i16x8.gt_s |
0x31 |
:+1: |
:+1: |
i16x8.gt_u |
0x32 |
:+1: |
:+1: |
i16x8.le_s |
0x33 |
:+1: |
:+1: |
i16x8.le_u |
0x34 |
:+1: |
:+1: |
i16x8.ge_s |
0x35 |
:+1: |
:+1: |
i16x8.ge_u |
0x36 |
:+1: |
:+1: |
i32x4.eq |
0x37 |
:+1: |
:+1: |
i32x4.ne |
0x38 |
:+1: |
:+1: |
i32x4.lt_s |
0x39 |
:+1: |
:+1: |
i32x4.lt_u |
0x3a |
:+1: |
:+1: |
i32x4.gt_s |
0x3b |
:+1: |
:+1: |
i32x4.gt_u |
0x3c |
:+1: |
:+1: |
i32x4.le_s |
0x3d |
:+1: |
:+1: |
i32x4.le_u |
0x3e |
:+1: |
:+1: |
i32x4.ge_s |
0x3f |
:+1: |
:+1: |
i32x4.ge_u |
0x40 |
:+1: |
:+1: |
Float Cmp |
Opcode |
Old Backend Status |
VCode Status |
f32x4.eq |
0x41 |
:+1: |
:+1: |
f32x4.ne |
0x42 |
:+1: |
:+1: |
f32x4.lt |
0x43 |
:+1: |
:+1: |
f32x4.gt |
0x44 |
:+1: |
:+1: |
f32x4.le |
0x45 |
:+1: |
:+1: |
f32x4.ge |
0x46 |
:+1: |
:+1: |
f64x2.eq |
0x47 |
:+1: |
:+1: |
f64x2.ne |
0x48 |
:+1: |
:+1: |
f64x2.lt |
0x49 |
:+1: |
:+1: |
f64x2.gt |
0x4a |
:+1: |
:+1: |
f64x2.le |
0x4b |
:+1: |
:+1: |
f64x2.ge |
0x4c |
:+1: |
:+1: |
v128 Op |
Opcode |
Old Backend Status |
VCode Status |
v128.not |
0x4d |
:+1: |
:+1: |
v128.and |
0x4e |
:+1: |
:+1: |
v128.andnot |
0x4f |
:+1: |
:+1: |
v128.or |
0x50 |
:+1: |
:+1: |
v128.xor |
0x51 |
:+1: |
:+1: |
v128.bitselect |
0x52 |
:+1: |
:+1: |
i8x16 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i8x16.abs |
0x60 |
:+1: |
:+1: |
i8x16.neg |
0x61 |
:+1: |
:+1: |
i8x16.any_true |
0x62 |
:+1: |
:+1: |
i8x16.all_true |
0x63 |
:+1: |
:+1: |
i8x16.bitmask |
0x64 |
:question: |
:+1: |
i8x16.narrow_i16x8_s |
0x65 |
:+1: |
:+1: |
i8x16.narrow_i16x8_u |
0x66 |
:+1: |
:+1: |
---- widen ---- |
0x67 |
-- |
|
---- widen ---- |
0x68 |
-- |
|
---- widen ---- |
0x69 |
-- |
|
---- widen ---- |
0x6a |
-- |
|
i8x16.shl |
0x6b |
:+1: |
:+1: |
i8x16.shr_s |
0x6c |
:+1: |
:+1: |
i8x16.shr_u |
0x6d |
:+1: |
:+1: |
i8x16.add |
0x6e |
:+1: |
:+1: |
i8x16.add_sat_s |
0x6f |
:+1: |
:+1: |
i8x16.add_sat_u |
0x70 |
:+1: |
:+1: |
i8x16.sub |
0x71 |
:+1: |
:+1: |
i8x16.sub_sat_s |
0x72 |
:+1: |
:+1: |
i8x16.sub_sat_u |
0x73 |
:+1: |
:+1: |
---- dot ---- |
0x74 |
-- |
|
---- mul ---- |
0x75 |
:question: |
|
i8x16.min_s |
0x76 |
:+1: |
:+1: |
i8x16.min_u |
0x77 |
:+1: |
:+1: |
i8x16.max_s |
0x78 |
:+1: |
:+1: |
i8x16.max_u |
0x79 |
:+1: |
:+1: |
---- avgr_s ---- |
0x7a |
-- |
|
i8x16.avgr_u |
0x7b |
:+1: |
:+1: |
i16x8 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i16x8.abs |
0x80 |
:+1: |
:+1: |
i16x8.neg |
0x81 |
:+1: |
:+1: |
i16x8.any_true |
0x82 |
:+1: |
:+1: |
i16x8.all_true |
0x83 |
:+1: |
:+1: |
i16x8.bitmask |
0x84 |
:question: |
:+1: |
i16x8.narrow_i32x4_s |
0x85 |
:+1: |
:+1: |
i16x8.narrow_i32x4_u |
0x86 |
:+1: |
:+1: |
i16x8.widen_low_i8x16_s |
0x87 |
:+1: |
:+1: |
i16x8.widen_high_i8x16_s |
0x88 |
:+1: |
:+1: |
i16x8.widen_low_i8x16_u |
0x89 |
:+1: |
:+1: |
i16x8.widen_high_i8x16_u |
0x8a |
:+1: |
:+1: |
i16x8.shl |
0x8b |
:+1: |
:+1: |
i16x8.shr_s |
0x8c |
:+1: |
:+1: |
i16x8.shr_u |
0x8d |
:+1: |
:+1: |
i16x8.add |
0x8e |
:+1: |
:+1: |
i16x8.add_sat_s |
0x8f |
:+1: |
:+1: |
i16x8.add_sat_u |
0x90 |
:+1: |
:+1: |
i16x8.sub |
0x91 |
:+1: |
:+1: |
i16x8.sub_sat_s |
0x92 |
:+1: |
:+1: |
i16x8.sub_sat_u |
0x93 |
:+1: |
:+1: |
---- dot ---- |
0x94 |
-- |
@abrown |
i16x8.mul |
0x95 |
:+1: |
:+1: |
i16x8.min_s |
0x96 |
:+1: |
:+1: |
i16x8.min_u |
0x97 |
:+1: |
:+1: |
i16x8.max_s |
0x98 |
:+1: |
:+1: |
i16x8.max_u |
0x99 |
:+1: |
:+1: |
---- avgr_s ---- |
0x9a |
-- |
|
i16x8.avgr_u |
0x9b |
:+1: |
:+1: |
i32x4 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i32x4.abs |
0xa0 |
:+1: |
:+1: |
i32x4.neg |
0xa1 |
:+1: |
:+1: |
i32x4.any_true |
0xa2 |
:+1: |
:+1: |
i32x4.all_true |
0xa3 |
:+1: |
:+1: |
i32x4.bitmask |
0xa4 |
:question: |
:+1: |
---- narrow ---- |
0xa5 |
-- |
|
---- narrow ---- |
0xa6 |
-- |
|
i32x4.widen_low_i16x8_s |
0xa7 |
:+1: |
:+1: |
i32x4.widen_high_i16x8_s |
0xa8 |
:+1: |
:+1: |
i32x4.widen_low_i16x8_u |
0xa9 |
:+1: |
:+1: |
i32x4.widen_high_i16x8_u |
0xaa |
:+1: |
:+1: |
i32x4.shl |
0xab |
:+1: |
:+1: |
i32x4.shr_s |
0xac |
:+1: |
:+1: |
i32x4.shr_u |
0xad |
:+1: |
:+1: |
i32x4.add |
0xae |
:+1: |
:+1: |
---- add_sat ---- |
0xaf |
-- |
|
---- add_sat ---- |
0xb0 |
-- |
|
i32x4.sub |
0xb1 |
:+1: |
:+1: |
---- sub_sat ---- |
0xb2 |
-- |
|
---- sub_sat ---- |
0xb3 |
-- |
|
---- dot ---- |
0xb4 |
-- |
|
i32x4.mul |
0xb5 |
:+1: |
:+1: |
i32x4.min_s |
0xb6 |
:+1: |
:+1: |
i32x4.min_u |
0xb7 |
:+1: |
:+1: |
i32x4.max_s |
0xb8 |
:+1: |
:+1: |
i32x4.max_u |
0xb9 |
:+1: |
:+1: |
---- avgr_s ---- |
0xba |
-- |
|
---- avgr_u ---- |
0xbb |
-- |
|
i64x2 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
---- |
0xc0 |
-- |
|
i64x2.neg |
0xc1 |
:+1: |
:+1: |
---- |
0xc2 |
-- |
|
---- |
0xc3 |
-- |
|
---- |
0xc4 |
-- |
|
---- |
0xc5 |
-- |
|
---- |
0xc6 |
-- |
|
---- |
0xc7 |
-- |
|
---- |
0xc8 |
-- |
|
---- |
0xc9 |
-- |
|
---- |
0xca |
-- |
|
i64x2.shl |
0xcb |
:+1: |
:+1: |
i64x2.shr_s |
0xcc |
:+1: |
:+1: |
i64x2.shr_u |
0xcd |
:+1: |
:+1: |
i64x2.add |
0xce |
:+1: |
:+1: |
---- |
0xcf |
-- |
|
---- |
0xd0 |
-- |
|
i64x2.sub |
0xd1 |
:+1: |
:+1: |
---- |
0xd2 |
-- |
|
---- |
0xd3 |
-- |
|
---- |
0xd4 |
-- |
|
i64x2.mul |
0xd5 |
:+1: |
:+1: |
---- |
0xd6 |
-- |
|
---- |
0xd7 |
-- |
|
f32x4 Op |
Opcode |
Old Backend Status |
VCode Status |
f32x4.ceil |
0xd8 |
:question: |
:+1: |
f32x4.floor |
0xd9 |
:question: |
:+1: |
f32x4.trunc |
0xda |
:question: |
:+1: |
f32x4.nearest |
0xdb |
:question: |
:+1: |
f32x4.abs |
0xe0 |
:+1: |
:+1: |
f32x4.neg |
0xe1 |
:+1: |
:+1: |
---- round ---- |
0xe2 |
-- |
|
f32x4.sqrt |
0xe3 |
:+1: |
:+1: |
f32x4.add |
0xe4 |
:+1: |
:+1: |
f32x4.sub |
0xe5 |
:+1: |
:+1: |
f32x4.mul |
0xe6 |
:+1: |
:+1: |
f32x4.div |
0xe7 |
:+1: |
:+1: |
f32x4.min |
0xe8 |
:+1: |
:+1: |
f32x4.max |
0xe9 |
:+1: |
:+1: |
f32x4.pmin |
0xea |
:question: |
:+1: |
f32x4.pmax |
0xeb |
:question: |
:+1: |
f64x2 Op |
Opcode |
Old Backend Status |
VCode Status |
f64x2.ceil |
0xdc |
:question: |
:+1: |
f64x2.floor |
0xdd |
:question: |
:+1: |
f64x2.trunc |
0xde |
:question: |
:+1: |
f64x2.nearest |
0xdf |
:question: |
:+1: |
f64x2.abs |
0xec |
:+1: |
:+1: |
f64x2.neg |
0xed |
:+1: |
:+1: |
---- round ---- |
0xee |
-- |
|
f64x2.sqrt |
0xef |
:+1: |
:+1: |
f64x2.add |
0xf0 |
:+1: |
:+1: |
f64x2.sub |
0xf1 |
:+1: |
:+1: |
f64x2.mul |
0xf2 |
:+1: |
:+1: |
f64x2.div |
0xf3 |
:+1: |
:+1: |
f64x2.min |
0xf4 |
:+1: |
:+1: |
f64x2.max |
0xf5 |
:+1: |
:+1: |
f64x2.pmin |
0xf6 |
:question: |
:+1: |
f64x2.pmax |
0xf7 |
:question: |
:+1: |
Conversion Op |
Opcode |
Old Backend Status |
VCode Status |
i32x4.trunc_sat_f32x4_s |
0xf8 |
:question: |
:+1: |
i32x4.trunc_sat_f32x4_u |
0xf9 |
:question: |
:+1: |
f32x4.convert_i32x4_s |
0xfa |
:+1: |
:+1: |
f32x4.convert_i32x4_u |
0xfb |
:question: |
:+1: |
jlb6740 edited Issue #2272:
Last Update: 12/16/2020
Loads |
Opcode |
Old Backend Status |
VCode Status |
v128.load |
0x00 |
:+1: |
:+1: |
v128.load32_zero |
0xfc |
-- |
:+1: |
v128.load64_zero |
0xfd |
-- |
:+1: |
v128.load8x8_s |
0x01 |
:+1: |
:+1: |
v128.load8x8_u |
0x02 |
:+1: |
:+1: |
v128.load16x4_s |
0x03 |
:+1: |
:+1: |
v128.load16x4_u |
0x04 |
:+1: |
:+1: |
v128.load32x2_s |
0x05 |
:+1: |
:+1: |
v128.load32x2_u |
0x06 |
:+1: |
:+1: |
v128.load8_splat |
0x07 |
:+1: |
:+1: |
v128.load16_splat |
0x08 |
:+1: |
:+1: |
v128.load32_splat |
0x09 |
:+1: |
:+1: |
v128.load64_splat |
0x0a |
:+1: |
:+1: |
Stores |
Opcode |
Old Backend Status |
VCode Status |
v128.store |
0x0b |
:+1: |
:+1: |
Basic operation |
Opcode |
Old Backend Status |
VCode Status |
v128.const |
0x0c |
:+1: |
:+1: |
i8x16.shuffle |
0x0d |
:+1: |
:+1: |
i8x16.swizzle |
0x0e |
:+1: |
:+1: |
Splat operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.splat |
0x0f |
:+1: |
:+1: |
i16x8.splat |
0x10 |
:+1: |
:+1: |
i32x4.splat |
0x11 |
:+1: |
:+1: |
i64x2.splat |
0x12 |
:+1: |
:+1: |
f32x4.splat |
0x13 |
:+1: |
:+1: |
f64x2.splat |
0x14 |
:+1: |
:+1: |
Lane operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.extract_lane_s |
0x15 |
:+1: |
:+1: |
i8x16.extract_lane_u |
0x16 |
:+1: |
:+1: |
i8x16.replace_lane |
0x17 |
:+1: |
:+1: |
i16x8.extract_lane_s |
0x18 |
:+1: |
:+1: |
i16x8.extract_lane_u |
0x19 |
:+1: |
:+1: |
i16x8.replace_lane |
0x1a |
:+1: |
:+1: |
i32x4.extract_lane |
0x1b |
:+1: |
:+1: |
i32x4.replace_lane |
0x1c |
:+1: |
:+1: |
i64x2.extract_lane |
0x1d |
:+1: |
:+1: |
i64x2.replace_lane |
0x1e |
:+1: |
:+1: |
f32x4.extract_lane |
0x1f |
:+1: |
:+1: |
f32x4.replace_lane |
0x20 |
:+1: |
:+1: |
f64x2.extract_lane |
0x21 |
:+1: |
:+1: |
f64x2.replace_lane |
0x22 |
:+1: |
:+1: |
Integer Cmp |
Opcode |
Old Backend Status |
VCode Status |
i8x16.eq |
0x23 |
:+1: |
:+1: |
i8x16.ne |
0x24 |
:+1: |
:+1: |
i8x16.lt_s |
0x25 |
:+1: |
:+1: |
i8x16.lt_u |
0x26 |
:+1: |
:+1: |
i8x16.gt_s |
0x27 |
:+1: |
:+1: |
i8x16.gt_u |
0x28 |
:+1: |
:+1: |
i8x16.le_s |
0x29 |
:+1: |
:+1: |
i8x16.le_u |
0x2a |
:+1: |
:+1: |
i8x16.ge_s |
0x2b |
:+1: |
:+1: |
i8x16.ge_u |
0x2c |
:+1: |
:+1: |
i16x8.eq |
0x2d |
:+1: |
:+1: |
i16x8.ne |
0x2e |
:+1: |
:+1: |
i16x8.lt_s |
0x2f |
:+1: |
:+1: |
i16x8.lt_u |
0x30 |
:+1: |
:+1: |
i16x8.gt_s |
0x31 |
:+1: |
:+1: |
i16x8.gt_u |
0x32 |
:+1: |
:+1: |
i16x8.le_s |
0x33 |
:+1: |
:+1: |
i16x8.le_u |
0x34 |
:+1: |
:+1: |
i16x8.ge_s |
0x35 |
:+1: |
:+1: |
i16x8.ge_u |
0x36 |
:+1: |
:+1: |
i32x4.eq |
0x37 |
:+1: |
:+1: |
i32x4.ne |
0x38 |
:+1: |
:+1: |
i32x4.lt_s |
0x39 |
:+1: |
:+1: |
i32x4.lt_u |
0x3a |
:+1: |
:+1: |
i32x4.gt_s |
0x3b |
:+1: |
:+1: |
i32x4.gt_u |
0x3c |
:+1: |
:+1: |
i32x4.le_s |
0x3d |
:+1: |
:+1: |
i32x4.le_u |
0x3e |
:+1: |
:+1: |
i32x4.ge_s |
0x3f |
:+1: |
:+1: |
i32x4.ge_u |
0x40 |
:+1: |
:+1: |
Float Cmp |
Opcode |
Old Backend Status |
VCode Status |
f32x4.eq |
0x41 |
:+1: |
:+1: |
f32x4.ne |
0x42 |
:+1: |
:+1: |
f32x4.lt |
0x43 |
:+1: |
:+1: |
f32x4.gt |
0x44 |
:+1: |
:+1: |
f32x4.le |
0x45 |
:+1: |
:+1: |
f32x4.ge |
0x46 |
:+1: |
:+1: |
f64x2.eq |
0x47 |
:+1: |
:+1: |
f64x2.ne |
0x48 |
:+1: |
:+1: |
f64x2.lt |
0x49 |
:+1: |
:+1: |
f64x2.gt |
0x4a |
:+1: |
:+1: |
f64x2.le |
0x4b |
:+1: |
:+1: |
f64x2.ge |
0x4c |
:+1: |
:+1: |
v128 Op |
Opcode |
Old Backend Status |
VCode Status |
v128.not |
0x4d |
:+1: |
:+1: |
v128.and |
0x4e |
:+1: |
:+1: |
v128.andnot |
0x4f |
:+1: |
:+1: |
v128.or |
0x50 |
:+1: |
:+1: |
v128.xor |
0x51 |
:+1: |
:+1: |
v128.bitselect |
0x52 |
:+1: |
:+1: |
i8x16 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i8x16.abs |
0x60 |
:+1: |
:+1: |
i8x16.neg |
0x61 |
:+1: |
:+1: |
i8x16.any_true |
0x62 |
:+1: |
:+1: |
i8x16.all_true |
0x63 |
:+1: |
:+1: |
i8x16.bitmask |
0x64 |
:question: |
:+1: |
i8x16.narrow_i16x8_s |
0x65 |
:+1: |
:+1: |
i8x16.narrow_i16x8_u |
0x66 |
:+1: |
:+1: |
---- widen ---- |
0x67 |
-- |
|
---- widen ---- |
0x68 |
-- |
|
---- widen ---- |
0x69 |
-- |
|
---- widen ---- |
0x6a |
-- |
|
i8x16.shl |
0x6b |
:+1: |
:+1: |
i8x16.shr_s |
0x6c |
:+1: |
:+1: |
i8x16.shr_u |
0x6d |
:+1: |
:+1: |
i8x16.add |
0x6e |
:+1: |
:+1: |
i8x16.add_sat_s |
0x6f |
:+1: |
:+1: |
i8x16.add_sat_u |
0x70 |
:+1: |
:+1: |
i8x16.sub |
0x71 |
:+1: |
:+1: |
i8x16.sub_sat_s |
0x72 |
:+1: |
:+1: |
i8x16.sub_sat_u |
0x73 |
:+1: |
:+1: |
---- dot ---- |
0x74 |
-- |
|
---- mul ---- |
0x75 |
:question: |
|
i8x16.min_s |
0x76 |
:+1: |
:+1: |
i8x16.min_u |
0x77 |
:+1: |
:+1: |
i8x16.max_s |
0x78 |
:+1: |
:+1: |
i8x16.max_u |
0x79 |
:+1: |
:+1: |
---- avgr_s ---- |
0x7a |
-- |
|
i8x16.avgr_u |
0x7b |
:+1: |
:+1: |
i16x8 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i16x8.abs |
0x80 |
:+1: |
:+1: |
i16x8.neg |
0x81 |
:+1: |
:+1: |
i16x8.any_true |
0x82 |
:+1: |
:+1: |
i16x8.all_true |
0x83 |
:+1: |
:+1: |
i16x8.bitmask |
0x84 |
:question: |
:+1: |
i16x8.narrow_i32x4_s |
0x85 |
:+1: |
:+1: |
i16x8.narrow_i32x4_u |
0x86 |
:+1: |
:+1: |
i16x8.widen_low_i8x16_s |
0x87 |
:+1: |
:+1: |
i16x8.widen_high_i8x16_s |
0x88 |
:+1: |
:+1: |
i16x8.widen_low_i8x16_u |
0x89 |
:+1: |
:+1: |
i16x8.widen_high_i8x16_u |
0x8a |
:+1: |
:+1: |
i16x8.shl |
0x8b |
:+1: |
:+1: |
i16x8.shr_s |
0x8c |
:+1: |
:+1: |
i16x8.shr_u |
0x8d |
:+1: |
:+1: |
i16x8.add |
0x8e |
:+1: |
:+1: |
i16x8.add_sat_s |
0x8f |
:+1: |
:+1: |
i16x8.add_sat_u |
0x90 |
:+1: |
:+1: |
i16x8.sub |
0x91 |
:+1: |
:+1: |
i16x8.sub_sat_s |
0x92 |
:+1: |
:+1: |
i16x8.sub_sat_u |
0x93 |
:+1: |
:+1: |
---- dot ---- |
0x94 |
-- |
@abrown |
i16x8.mul |
0x95 |
:+1: |
:+1: |
i16x8.min_s |
0x96 |
:+1: |
:+1: |
i16x8.min_u |
0x97 |
:+1: |
:+1: |
i16x8.max_s |
0x98 |
:+1: |
:+1: |
i16x8.max_u |
0x99 |
:+1: |
:+1: |
---- avgr_s ---- |
0x9a |
-- |
|
i16x8.avgr_u |
0x9b |
:+1: |
:+1: |
i32x4 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i32x4.abs |
0xa0 |
:+1: |
:+1: |
i32x4.neg |
0xa1 |
:+1: |
:+1: |
i32x4.any_true |
0xa2 |
:+1: |
:+1: |
i32x4.all_true |
0xa3 |
:+1: |
:+1: |
i32x4.bitmask |
0xa4 |
:question: |
:+1: |
---- narrow ---- |
0xa5 |
-- |
|
---- narrow ---- |
0xa6 |
-- |
|
i32x4.widen_low_i16x8_s |
0xa7 |
:+1: |
:+1: |
i32x4.widen_high_i16x8_s |
0xa8 |
:+1: |
:+1: |
i32x4.widen_low_i16x8_u |
0xa9 |
:+1: |
:+1: |
i32x4.widen_high_i16x8_u |
0xaa |
:+1: |
:+1: |
i32x4.shl |
0xab |
:+1: |
:+1: |
i32x4.shr_s |
0xac |
:+1: |
:+1: |
i32x4.shr_u |
0xad |
:+1: |
:+1: |
i32x4.add |
0xae |
:+1: |
:+1: |
---- add_sat ---- |
0xaf |
-- |
|
---- add_sat ---- |
0xb0 |
-- |
|
i32x4.sub |
0xb1 |
:+1: |
:+1: |
---- sub_sat ---- |
0xb2 |
-- |
|
---- sub_sat ---- |
0xb3 |
-- |
|
---- dot ---- |
0xb4 |
-- |
|
i32x4.mul |
0xb5 |
:+1: |
:+1: |
i32x4.min_s |
0xb6 |
:+1: |
:+1: |
i32x4.min_u |
0xb7 |
:+1: |
:+1: |
i32x4.max_s |
0xb8 |
:+1: |
:+1: |
i32x4.max_u |
0xb9 |
:+1: |
:+1: |
---- avgr_s ---- |
0xba |
-- |
|
---- avgr_u ---- |
0xbb |
-- |
|
i64x2 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
---- |
0xc0 |
-- |
|
i64x2.neg |
0xc1 |
:+1: |
:+1: |
---- |
0xc2 |
-- |
|
---- |
0xc3 |
-- |
|
---- |
0xc4 |
-- |
|
---- |
0xc5 |
-- |
|
---- |
0xc6 |
-- |
|
---- |
0xc7 |
-- |
|
---- |
0xc8 |
-- |
|
---- |
0xc9 |
-- |
|
---- |
0xca |
-- |
|
i64x2.shl |
0xcb |
:+1: |
:+1: |
i64x2.shr_s |
0xcc |
:+1: |
:+1: |
i64x2.shr_u |
0xcd |
:+1: |
:+1: |
i64x2.add |
0xce |
:+1: |
:+1: |
---- |
0xcf |
-- |
|
---- |
0xd0 |
-- |
|
i64x2.sub |
0xd1 |
:+1: |
:+1: |
---- |
0xd2 |
-- |
|
---- |
0xd3 |
-- |
|
---- |
0xd4 |
-- |
|
i64x2.mul |
0xd5 |
:+1: |
:+1: |
---- |
0xd6 |
-- |
|
---- |
0xd7 |
-- |
|
f32x4 Op |
Opcode |
Old Backend Status |
VCode Status |
f32x4.ceil |
0xd8 |
:question: |
:+1: |
f32x4.floor |
0xd9 |
:question: |
:+1: |
f32x4.trunc |
0xda |
:question: |
:+1: |
f32x4.nearest |
0xdb |
:question: |
:+1: |
f32x4.abs |
0xe0 |
:+1: |
:+1: |
f32x4.neg |
0xe1 |
:+1: |
:+1: |
---- round ---- |
0xe2 |
-- |
|
f32x4.sqrt |
0xe3 |
:+1: |
:+1: |
f32x4.add |
0xe4 |
:+1: |
:+1: |
f32x4.sub |
0xe5 |
:+1: |
:+1: |
f32x4.mul |
0xe6 |
:+1: |
:+1: |
f32x4.div |
0xe7 |
:+1: |
:+1: |
f32x4.min |
0xe8 |
:+1: |
:+1: |
f32x4.max |
0xe9 |
:+1: |
:+1: |
f32x4.pmin |
0xea |
:question: |
:+1: |
f32x4.pmax |
0xeb |
:question: |
:+1: |
f64x2 Op |
Opcode |
Old Backend Status |
VCode Status |
f64x2.ceil |
0xdc |
:question: |
:+1: |
f64x2.floor |
0xdd |
:question: |
:+1: |
f64x2.trunc |
0xde |
:question: |
:+1: |
f64x2.nearest |
0xdf |
:question: |
:+1: |
f64x2.abs |
0xec |
:+1: |
:+1: |
f64x2.neg |
0xed |
:+1: |
:+1: |
---- round ---- |
0xee |
-- |
|
f64x2.sqrt |
0xef |
:+1: |
:+1: |
f64x2.add |
0xf0 |
:+1: |
:+1: |
f64x2.sub |
0xf1 |
:+1: |
:+1: |
f64x2.mul |
0xf2 |
:+1: |
:+1: |
f64x2.div |
0xf3 |
:+1: |
:+1: |
f64x2.min |
0xf4 |
:+1: |
:+1: |
f64x2.max |
0xf5 |
:+1: |
:+1: |
f64x2.pmin |
0xf6 |
:question: |
:+1: |
f64x2.pmax |
0xf7 |
:question: |
:+1: |
Conversion Op |
Opcode |
Old Backend Status |
VCode Status |
i32x4.trunc_sat_f32x4_s |
0xf8 |
:question: |
:+1: |
i32x4.trunc_sat_f32x4_u |
0xf9 |
:question: |
:+1: |
f32x4.convert_i32x4_s |
0xfa |
:+1: |
:+1: |
f32x4.convert_i32x4_u |
0xfb |
:question: |
:+1: |
jlb6740 edited Issue #2272:
Last Update: 1/14/2021
Loads |
Opcode |
Old Backend Status |
VCode Status |
v128.load |
0x00 |
:+1: |
:+1: |
v128.load32_zero |
0xfc |
-- |
:+1: |
v128.load64_zero |
0xfd |
-- |
:+1: |
v128.load8x8_s |
0x01 |
:+1: |
:+1: |
v128.load8x8_u |
0x02 |
:+1: |
:+1: |
v128.load16x4_s |
0x03 |
:+1: |
:+1: |
v128.load16x4_u |
0x04 |
:+1: |
:+1: |
v128.load32x2_s |
0x05 |
:+1: |
:+1: |
v128.load32x2_u |
0x06 |
:+1: |
:+1: |
v128.load8_splat |
0x07 |
:+1: |
:+1: |
v128.load16_splat |
0x08 |
:+1: |
:+1: |
v128.load32_splat |
0x09 |
:+1: |
:+1: |
v128.load64_splat |
0x0a |
:+1: |
:+1: |
Stores |
Opcode |
Old Backend Status |
VCode Status |
v128.store |
0x0b |
:+1: |
:+1: |
Basic operation |
Opcode |
Old Backend Status |
VCode Status |
v128.const |
0x0c |
:+1: |
:+1: |
i8x16.shuffle |
0x0d |
:+1: |
:+1: |
i8x16.swizzle |
0x0e |
:+1: |
:+1: |
Splat operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.splat |
0x0f |
:+1: |
:+1: |
i16x8.splat |
0x10 |
:+1: |
:+1: |
i32x4.splat |
0x11 |
:+1: |
:+1: |
i64x2.splat |
0x12 |
:+1: |
:+1: |
f32x4.splat |
0x13 |
:+1: |
:+1: |
f64x2.splat |
0x14 |
:+1: |
:+1: |
Lane operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.extract_lane_s |
0x15 |
:+1: |
:+1: |
i8x16.extract_lane_u |
0x16 |
:+1: |
:+1: |
i8x16.replace_lane |
0x17 |
:+1: |
:+1: |
i16x8.extract_lane_s |
0x18 |
:+1: |
:+1: |
i16x8.extract_lane_u |
0x19 |
:+1: |
:+1: |
i16x8.replace_lane |
0x1a |
:+1: |
:+1: |
i32x4.extract_lane |
0x1b |
:+1: |
:+1: |
i32x4.replace_lane |
0x1c |
:+1: |
:+1: |
i64x2.extract_lane |
0x1d |
:+1: |
:+1: |
i64x2.replace_lane |
0x1e |
:+1: |
:+1: |
f32x4.extract_lane |
0x1f |
:+1: |
:+1: |
f32x4.replace_lane |
0x20 |
:+1: |
:+1: |
f64x2.extract_lane |
0x21 |
:+1: |
:+1: |
f64x2.replace_lane |
0x22 |
:+1: |
:+1: |
Integer Cmp |
Opcode |
Old Backend Status |
VCode Status |
i8x16.eq |
0x23 |
:+1: |
:+1: |
i8x16.ne |
0x24 |
:+1: |
:+1: |
i8x16.lt_s |
0x25 |
:+1: |
:+1: |
i8x16.lt_u |
0x26 |
:+1: |
:+1: |
i8x16.gt_s |
0x27 |
:+1: |
:+1: |
i8x16.gt_u |
0x28 |
:+1: |
:+1: |
i8x16.le_s |
0x29 |
:+1: |
:+1: |
i8x16.le_u |
0x2a |
:+1: |
:+1: |
i8x16.ge_s |
0x2b |
:+1: |
:+1: |
i8x16.ge_u |
0x2c |
:+1: |
:+1: |
i16x8.eq |
0x2d |
:+1: |
:+1: |
i16x8.ne |
0x2e |
:+1: |
:+1: |
i16x8.lt_s |
0x2f |
:+1: |
:+1: |
i16x8.lt_u |
0x30 |
:+1: |
:+1: |
i16x8.gt_s |
0x31 |
:+1: |
:+1: |
i16x8.gt_u |
0x32 |
:+1: |
:+1: |
i16x8.le_s |
0x33 |
:+1: |
:+1: |
i16x8.le_u |
0x34 |
:+1: |
:+1: |
i16x8.ge_s |
0x35 |
:+1: |
:+1: |
i16x8.ge_u |
0x36 |
:+1: |
:+1: |
i32x4.eq |
0x37 |
:+1: |
:+1: |
i32x4.ne |
0x38 |
:+1: |
:+1: |
i32x4.lt_s |
0x39 |
:+1: |
:+1: |
i32x4.lt_u |
0x3a |
:+1: |
:+1: |
i32x4.gt_s |
0x3b |
:+1: |
:+1: |
i32x4.gt_u |
0x3c |
:+1: |
:+1: |
i32x4.le_s |
0x3d |
:+1: |
:+1: |
i32x4.le_u |
0x3e |
:+1: |
:+1: |
i32x4.ge_s |
0x3f |
:+1: |
:+1: |
i32x4.ge_u |
0x40 |
:+1: |
:+1: |
Float Cmp |
Opcode |
Old Backend Status |
VCode Status |
f32x4.eq |
0x41 |
:+1: |
:+1: |
f32x4.ne |
0x42 |
:+1: |
:+1: |
f32x4.lt |
0x43 |
:+1: |
:+1: |
f32x4.gt |
0x44 |
:+1: |
:+1: |
f32x4.le |
0x45 |
:+1: |
:+1: |
f32x4.ge |
0x46 |
:+1: |
:+1: |
f64x2.eq |
0x47 |
:+1: |
:+1: |
f64x2.ne |
0x48 |
:+1: |
:+1: |
f64x2.lt |
0x49 |
:+1: |
:+1: |
f64x2.gt |
0x4a |
:+1: |
:+1: |
f64x2.le |
0x4b |
:+1: |
:+1: |
f64x2.ge |
0x4c |
:+1: |
:+1: |
v128 Op |
Opcode |
Old Backend Status |
VCode Status |
v128.not |
0x4d |
:+1: |
:+1: |
v128.and |
0x4e |
:+1: |
:+1: |
v128.andnot |
0x4f |
:+1: |
:+1: |
v128.or |
0x50 |
:+1: |
:+1: |
v128.xor |
0x51 |
:+1: |
:+1: |
v128.bitselect |
0x52 |
:+1: |
:+1: |
i8x16 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i8x16.abs |
0x60 |
:+1: |
:+1: |
i8x16.neg |
0x61 |
:+1: |
:+1: |
i8x16.any_true |
0x62 |
:+1: |
:+1: |
i8x16.all_true |
0x63 |
:+1: |
:+1: |
i8x16.bitmask |
0x64 |
:question: |
:+1: |
i8x16.narrow_i16x8_s |
0x65 |
:+1: |
:+1: |
i8x16.narrow_i16x8_u |
0x66 |
:+1: |
:+1: |
---- widen ---- |
0x67 |
-- |
|
---- widen ---- |
0x68 |
-- |
|
---- widen ---- |
0x69 |
-- |
|
---- widen ---- |
0x6a |
-- |
|
i8x16.shl |
0x6b |
:+1: |
:+1: |
i8x16.shr_s |
0x6c |
:+1: |
:+1: |
i8x16.shr_u |
0x6d |
:+1: |
:+1: |
i8x16.add |
0x6e |
:+1: |
:+1: |
i8x16.add_sat_s |
0x6f |
:+1: |
:+1: |
i8x16.add_sat_u |
0x70 |
:+1: |
:+1: |
i8x16.sub |
0x71 |
:+1: |
:+1: |
i8x16.sub_sat_s |
0x72 |
:+1: |
:+1: |
i8x16.sub_sat_u |
0x73 |
:+1: |
:+1: |
---- dot ---- |
0x74 |
-- |
|
---- mul ---- |
0x75 |
:question: |
|
i8x16.min_s |
0x76 |
:+1: |
:+1: |
i8x16.min_u |
0x77 |
:+1: |
:+1: |
i8x16.max_s |
0x78 |
:+1: |
:+1: |
i8x16.max_u |
0x79 |
:+1: |
:+1: |
---- avgr_s ---- |
0x7a |
-- |
|
i8x16.avgr_u |
0x7b |
:+1: |
:+1: |
i16x8 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i16x8.abs |
0x80 |
:+1: |
:+1: |
i16x8.neg |
0x81 |
:+1: |
:+1: |
i16x8.any_true |
0x82 |
:+1: |
:+1: |
i16x8.all_true |
0x83 |
:+1: |
:+1: |
i16x8.bitmask |
0x84 |
:question: |
:+1: |
i16x8.narrow_i32x4_s |
0x85 |
:+1: |
:+1: |
i16x8.narrow_i32x4_u |
0x86 |
:+1: |
:+1: |
i16x8.widen_low_i8x16_s |
0x87 |
:+1: |
:+1: |
i16x8.widen_high_i8x16_s |
0x88 |
:+1: |
:+1: |
i16x8.widen_low_i8x16_u |
0x89 |
:+1: |
:+1: |
i16x8.widen_high_i8x16_u |
0x8a |
:+1: |
:+1: |
i16x8.shl |
0x8b |
:+1: |
:+1: |
i16x8.shr_s |
0x8c |
:+1: |
:+1: |
i16x8.shr_u |
0x8d |
:+1: |
:+1: |
i16x8.add |
0x8e |
:+1: |
:+1: |
i16x8.add_sat_s |
0x8f |
:+1: |
:+1: |
i16x8.add_sat_u |
0x90 |
:+1: |
:+1: |
i16x8.sub |
0x91 |
:+1: |
:+1: |
i16x8.sub_sat_s |
0x92 |
:+1: |
:+1: |
i16x8.sub_sat_u |
0x93 |
:+1: |
:+1: |
---- dot ---- |
0x94 |
-- |
@abrown |
i16x8.mul |
0x95 |
:+1: |
:+1: |
i16x8.min_s |
0x96 |
:+1: |
:+1: |
i16x8.min_u |
0x97 |
:+1: |
:+1: |
i16x8.max_s |
0x98 |
:+1: |
:+1: |
i16x8.max_u |
0x99 |
:+1: |
:+1: |
---- avgr_s ---- |
0x9a |
-- |
|
i16x8.avgr_u |
0x9b |
:+1: |
:+1: |
i32x4 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i32x4.abs |
0xa0 |
:+1: |
:+1: |
i32x4.neg |
0xa1 |
:+1: |
:+1: |
i32x4.any_true |
0xa2 |
:+1: |
:+1: |
i32x4.all_true |
0xa3 |
:+1: |
:+1: |
i32x4.bitmask |
0xa4 |
:question: |
:+1: |
---- narrow ---- |
0xa5 |
-- |
|
---- narrow ---- |
0xa6 |
-- |
|
i32x4.widen_low_i16x8_s |
0xa7 |
:+1: |
:+1: |
i32x4.widen_high_i16x8_s |
0xa8 |
:+1: |
:+1: |
i32x4.widen_low_i16x8_u |
0xa9 |
:+1: |
:+1: |
i32x4.widen_high_i16x8_u |
0xaa |
:+1: |
:+1: |
i32x4.shl |
0xab |
:+1: |
:+1: |
i32x4.shr_s |
0xac |
:+1: |
:+1: |
i32x4.shr_u |
0xad |
:+1: |
:+1: |
i32x4.add |
0xae |
:+1: |
:+1: |
---- add_sat ---- |
0xaf |
-- |
|
---- add_sat ---- |
0xb0 |
-- |
|
i32x4.sub |
0xb1 |
:+1: |
:+1: |
---- sub_sat ---- |
0xb2 |
-- |
|
---- sub_sat ---- |
0xb3 |
-- |
|
---- dot ---- |
0xb4 |
-- |
|
i32x4.mul |
0xb5 |
:+1: |
:+1: |
i32x4.min_s |
0xb6 |
:+1: |
:+1: |
i32x4.min_u |
0xb7 |
:+1: |
:+1: |
i32x4.max_s |
0xb8 |
:+1: |
:+1: |
i32x4.max_u |
0xb9 |
:+1: |
:+1: |
---- avgr_s ---- |
0xba |
-- |
|
---- avgr_u ---- |
0xbb |
-- |
|
i64x2 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
---- |
0xc0 |
-- |
|
i64x2.neg |
0xc1 |
:+1: |
:+1: |
---- |
0xc2 |
-- |
|
---- |
0xc3 |
-- |
|
---- |
0xc4 |
-- |
|
---- |
0xc5 |
-- |
|
---- |
0xc6 |
-- |
|
---- |
0xc7 |
-- |
|
---- |
0xc8 |
-- |
|
---- |
0xc9 |
-- |
|
---- |
0xca |
-- |
|
i64x2.shl |
0xcb |
:+1: |
:+1: |
i64x2.shr_s |
0xcc |
:+1: |
:+1: |
i64x2.shr_u |
0xcd |
:+1: |
:+1: |
i64x2.add |
0xce |
:+1: |
:+1: |
---- |
0xcf |
-- |
|
---- |
0xd0 |
-- |
|
i64x2.sub |
0xd1 |
:+1: |
:+1: |
---- |
0xd2 |
-- |
|
---- |
0xd3 |
-- |
|
---- |
0xd4 |
-- |
|
i64x2.mul |
0xd5 |
:+1: |
:+1: |
---- |
0xd6 |
-- |
|
---- |
0xd7 |
-- |
|
f32x4 Op |
Opcode |
Old Backend Status |
VCode Status |
f32x4.ceil |
0xd8 |
:question: |
:+1: |
f32x4.floor |
0xd9 |
:question: |
:+1: |
f32x4.trunc |
0xda |
:question: |
:+1: |
f32x4.nearest |
0xdb |
:question: |
:+1: |
f32x4.abs |
0xe0 |
:+1: |
:+1: |
f32x4.neg |
0xe1 |
:+1: |
:+1: |
---- round ---- |
0xe2 |
-- |
|
f32x4.sqrt |
0xe3 |
:+1: |
:+1: |
f32x4.add |
0xe4 |
:+1: |
:+1: |
f32x4.sub |
0xe5 |
:+1: |
:+1: |
f32x4.mul |
0xe6 |
:+1: |
:+1: |
f32x4.div |
0xe7 |
:+1: |
:+1: |
f32x4.min |
0xe8 |
:+1: |
:+1: |
f32x4.max |
0xe9 |
:+1: |
:+1: |
f32x4.pmin |
0xea |
:question: |
:+1: |
f32x4.pmax |
0xeb |
:question: |
:+1: |
f64x2 Op |
Opcode |
Old Backend Status |
VCode Status |
f64x2.ceil |
0xdc |
:question: |
:+1: |
f64x2.floor |
0xdd |
:question: |
:+1: |
f64x2.trunc |
0xde |
:question: |
:+1: |
f64x2.nearest |
0xdf |
:question: |
:+1: |
f64x2.abs |
0xec |
:+1: |
:+1: |
f64x2.neg |
0xed |
:+1: |
:+1: |
---- round ---- |
0xee |
-- |
|
f64x2.sqrt |
0xef |
:+1: |
:+1: |
f64x2.add |
0xf0 |
:+1: |
:+1: |
f64x2.sub |
0xf1 |
:+1: |
:+1: |
f64x2.mul |
0xf2 |
:+1: |
:+1: |
f64x2.div |
0xf3 |
:+1: |
:+1: |
f64x2.min |
0xf4 |
:+1: |
:+1: |
f64x2.max |
0xf5 |
:+1: |
:+1: |
f64x2.pmin |
0xf6 |
:question: |
:+1: |
f64x2.pmax |
0xf7 |
:question: |
:+1: |
Conversion Op |
Opcode |
Old Backend Status |
VCode Status |
i32x4.trunc_sat_f32x4_s |
0xf8 |
:question: |
:+1: |
i32x4.trunc_sat_f32x4_u |
0xf9 |
:question: |
:+1: |
f32x4.convert_i32x4_s |
0xfa |
:+1: |
:+1: |
f32x4.convert_i32x4_u |
0xfb |
:question: |
:+1: |
jlb6740 edited Issue #2272:
Last Update: 1/14/2021
Loads |
Opcode |
Old Backend Status |
VCode Status |
v128.load |
0x00 |
:+1: |
:+1: |
v128.load32_zero |
0xfc |
-- |
:+1: |
v128.load64_zero |
0xfd |
-- |
:+1: |
v128.load8x8_s |
0x01 |
:+1: |
:+1: |
v128.load8x8_u |
0x02 |
:+1: |
:+1: |
v128.load16x4_s |
0x03 |
:+1: |
:+1: |
v128.load16x4_u |
0x04 |
:+1: |
:+1: |
v128.load32x2_s |
0x05 |
:+1: |
:+1: |
v128.load32x2_u |
0x06 |
:+1: |
:+1: |
v128.load8_splat |
0x07 |
:+1: |
:+1: |
v128.load16_splat |
0x08 |
:+1: |
:+1: |
v128.load32_splat |
0x09 |
:+1: |
:+1: |
v128.load64_splat |
0x0a |
:+1: |
:+1: |
v128.load32_zero |
0xfc |
:+1: |
@jlb6740 |
v128.load64_zero |
0xfd |
:+1: |
@jlb6740 |
Stores |
Opcode |
Old Backend Status |
VCode Status |
v128.store |
0x0b |
:+1: |
:+1: |
Basic operation |
Opcode |
Old Backend Status |
VCode Status |
v128.const |
0x0c |
:+1: |
:+1: |
i8x16.shuffle |
0x0d |
:+1: |
:+1: |
i8x16.swizzle |
0x0e |
:+1: |
:+1: |
Splat operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.splat |
0x0f |
:+1: |
:+1: |
i16x8.splat |
0x10 |
:+1: |
:+1: |
i32x4.splat |
0x11 |
:+1: |
:+1: |
i64x2.splat |
0x12 |
:+1: |
:+1: |
f32x4.splat |
0x13 |
:+1: |
:+1: |
f64x2.splat |
0x14 |
:+1: |
:+1: |
Lane operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.extract_lane_s |
0x15 |
:+1: |
:+1: |
i8x16.extract_lane_u |
0x16 |
:+1: |
:+1: |
i8x16.replace_lane |
0x17 |
:+1: |
:+1: |
i16x8.extract_lane_s |
0x18 |
:+1: |
:+1: |
i16x8.extract_lane_u |
0x19 |
:+1: |
:+1: |
i16x8.replace_lane |
0x1a |
:+1: |
:+1: |
i32x4.extract_lane |
0x1b |
:+1: |
:+1: |
i32x4.replace_lane |
0x1c |
:+1: |
:+1: |
i64x2.extract_lane |
0x1d |
:+1: |
:+1: |
i64x2.replace_lane |
0x1e |
:+1: |
:+1: |
f32x4.extract_lane |
0x1f |
:+1: |
:+1: |
f32x4.replace_lane |
0x20 |
:+1: |
:+1: |
f64x2.extract_lane |
0x21 |
:+1: |
:+1: |
f64x2.replace_lane |
0x22 |
:+1: |
:+1: |
Integer Cmp |
Opcode |
Old Backend Status |
VCode Status |
i8x16.eq |
0x23 |
:+1: |
:+1: |
i8x16.ne |
0x24 |
:+1: |
:+1: |
i8x16.lt_s |
0x25 |
:+1: |
:+1: |
i8x16.lt_u |
0x26 |
:+1: |
:+1: |
i8x16.gt_s |
0x27 |
:+1: |
:+1: |
i8x16.gt_u |
0x28 |
:+1: |
:+1: |
i8x16.le_s |
0x29 |
:+1: |
:+1: |
i8x16.le_u |
0x2a |
:+1: |
:+1: |
i8x16.ge_s |
0x2b |
:+1: |
:+1: |
i8x16.ge_u |
0x2c |
:+1: |
:+1: |
i16x8.eq |
0x2d |
:+1: |
:+1: |
i16x8.ne |
0x2e |
:+1: |
:+1: |
i16x8.lt_s |
0x2f |
:+1: |
:+1: |
i16x8.lt_u |
0x30 |
:+1: |
:+1: |
i16x8.gt_s |
0x31 |
:+1: |
:+1: |
i16x8.gt_u |
0x32 |
:+1: |
:+1: |
i16x8.le_s |
0x33 |
:+1: |
:+1: |
i16x8.le_u |
0x34 |
:+1: |
:+1: |
i16x8.ge_s |
0x35 |
:+1: |
:+1: |
i16x8.ge_u |
0x36 |
:+1: |
:+1: |
i32x4.eq |
0x37 |
:+1: |
:+1: |
i32x4.ne |
0x38 |
:+1: |
:+1: |
i32x4.lt_s |
0x39 |
:+1: |
:+1: |
i32x4.lt_u |
0x3a |
:+1: |
:+1: |
i32x4.gt_s |
0x3b |
:+1: |
:+1: |
i32x4.gt_u |
0x3c |
:+1: |
:+1: |
i32x4.le_s |
0x3d |
:+1: |
:+1: |
i32x4.le_u |
0x3e |
:+1: |
:+1: |
i32x4.ge_s |
0x3f |
:+1: |
:+1: |
i32x4.ge_u |
0x40 |
:+1: |
:+1: |
Float Cmp |
Opcode |
Old Backend Status |
VCode Status |
f32x4.eq |
0x41 |
:+1: |
:+1: |
f32x4.ne |
0x42 |
:+1: |
:+1: |
f32x4.lt |
0x43 |
:+1: |
:+1: |
f32x4.gt |
0x44 |
:+1: |
:+1: |
f32x4.le |
0x45 |
:+1: |
:+1: |
f32x4.ge |
0x46 |
:+1: |
:+1: |
f64x2.eq |
0x47 |
:+1: |
:+1: |
f64x2.ne |
0x48 |
:+1: |
:+1: |
f64x2.lt |
0x49 |
:+1: |
:+1: |
f64x2.gt |
0x4a |
:+1: |
:+1: |
f64x2.le |
0x4b |
:+1: |
:+1: |
f64x2.ge |
0x4c |
:+1: |
:+1: |
v128 Op |
Opcode |
Old Backend Status |
VCode Status |
v128.not |
0x4d |
:+1: |
:+1: |
v128.and |
0x4e |
:+1: |
:+1: |
v128.andnot |
0x4f |
:+1: |
:+1: |
v128.or |
0x50 |
:+1: |
:+1: |
v128.xor |
0x51 |
:+1: |
:+1: |
v128.bitselect |
0x52 |
:+1: |
:+1: |
i8x16 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i8x16.abs |
0x60 |
:+1: |
:+1: |
i8x16.neg |
0x61 |
:+1: |
:+1: |
i8x16.any_true |
0x62 |
:+1: |
:+1: |
i8x16.all_true |
0x63 |
:+1: |
:+1: |
i8x16.bitmask |
0x64 |
:question: |
:+1: |
i8x16.narrow_i16x8_s |
0x65 |
:+1: |
:+1: |
i8x16.narrow_i16x8_u |
0x66 |
:+1: |
:+1: |
---- widen ---- |
0x67 |
-- |
|
---- widen ---- |
0x68 |
-- |
|
---- widen ---- |
0x69 |
-- |
|
---- widen ---- |
0x6a |
-- |
|
i8x16.shl |
0x6b |
:+1: |
:+1: |
i8x16.shr_s |
0x6c |
:+1: |
:+1: |
i8x16.shr_u |
0x6d |
:+1: |
:+1: |
i8x16.add |
0x6e |
:+1: |
:+1: |
i8x16.add_sat_s |
0x6f |
:+1: |
:+1: |
i8x16.add_sat_u |
0x70 |
:+1: |
:+1: |
i8x16.sub |
0x71 |
:+1: |
:+1: |
i8x16.sub_sat_s |
0x72 |
:+1: |
:+1: |
i8x16.sub_sat_u |
0x73 |
:+1: |
:+1: |
------------ |
0x74 |
-- |
-- |
---- mul ---- |
0x75 |
:question: |
|
i8x16.min_s |
0x76 |
:+1: |
:+1: |
i8x16.min_u |
0x77 |
:+1: |
:+1: |
i8x16.max_s |
0x78 |
:+1: |
:+1: |
i8x16.max_u |
0x79 |
:+1: |
:+1: |
------------ |
0x7a |
-- |
|
i8x16.avgr_u |
0x7b |
:+1: |
:+1: |
i16x8 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i16x8.abs |
0x80 |
:+1: |
:+1: |
i16x8.neg |
0x81 |
:+1: |
:+1: |
i16x8.any_true |
0x82 |
:+1: |
:+1: |
i16x8.all_true |
0x83 |
:+1: |
:+1: |
i16x8.bitmask |
0x84 |
:question: |
:+1: |
i16x8.narrow_i32x4_s |
0x85 |
:+1: |
:+1: |
i16x8.narrow_i32x4_u |
0x86 |
:+1: |
:+1: |
i16x8.widen_low_i8x16_s |
0x87 |
:+1: |
:+1: |
i16x8.widen_high_i8x16_s |
0x88 |
:+1: |
:+1: |
i16x8.widen_low_i8x16_u |
0x89 |
:+1: |
:+1: |
i16x8.widen_high_i8x16_u |
0x8a |
:+1: |
:+1: |
i16x8.shl |
0x8b |
:+1: |
:+1: |
i16x8.shr_s |
0x8c |
:+1: |
:+1: |
i16x8.shr_u |
0x8d |
:+1: |
:+1: |
i16x8.add |
0x8e |
:+1: |
:+1: |
i16x8.add_sat_s |
0x8f |
:+1: |
:+1: |
i16x8.add_sat_u |
0x90 |
:+1: |
:+1: |
i16x8.sub |
0x91 |
:+1: |
:+1: |
i16x8.sub_sat_s |
0x92 |
:+1: |
:+1: |
i16x8.sub_sat_u |
0x93 |
:+1: |
:+1: |
------------ |
0x94 |
-- |
-- |
i16x8.mul |
0x95 |
:+1: |
:+1: |
i16x8.min_s |
0x96 |
:+1: |
:+1: |
i16x8.min_u |
0x97 |
:+1: |
:+1: |
i16x8.max_s |
0x98 |
:+1: |
:+1: |
i16x8.max_u |
0x99 |
:+1: |
:+1: |
----------- |
0x9a |
-- |
|
i16x8.avgr_u |
0x9b |
:+1: |
:+1: |
i32x4 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i32x4.abs |
0xa0 |
:+1: |
:+1: |
i32x4.neg |
0xa1 |
:+1: |
:+1: |
i32x4.any_true |
0xa2 |
:+1: |
:+1: |
i32x4.all_true |
0xa3 |
:+1: |
:+1: |
i32x4.bitmask |
0xa4 |
:question: |
:+1: |
---- narrow ---- |
0xa5 |
-- |
|
---- narrow ---- |
0xa6 |
-- |
|
i32x4.widen_low_i16x8_s |
0xa7 |
:+1: |
:+1: |
i32x4.widen_high_i16x8_s |
0xa8 |
:+1: |
:+1: |
i32x4.widen_low_i16x8_u |
0xa9 |
:+1: |
:+1: |
i32x4.widen_high_i16x8_u |
0xaa |
:+1: |
:+1: |
i32x4.shl |
0xab |
:+1: |
:+1: |
i32x4.shr_s |
0xac |
:+1: |
:+1: |
i32x4.shr_u |
0xad |
:+1: |
:+1: |
i32x4.add |
0xae |
:+1: |
:+1: |
---- add_sat ---- |
0xaf |
-- |
|
---- add_sat ---- |
0xb0 |
-- |
|
i32x4.sub |
0xb1 |
:+1: |
:+1: |
---- sub_sat ---- |
0xb2 |
-- |
|
---- sub_sat ---- |
0xb3 |
-- |
|
---- dot ---- |
0xb4 |
-- |
|
i32x4.mul |
0xb5 |
:+1: |
:+1: |
i32x4.min_s |
0xb6 |
:+1: |
:+1: |
i32x4.min_u |
0xb7 |
:+1: |
:+1: |
i32x4.max_s |
0xb8 |
:+1: |
:+1: |
i32x4.max_u |
0xb9 |
:+1: |
:+1: |
i32x4.dot_i16x8_s |
0xba |
-- |
|
---- avgr_u ---- |
0xbb |
-- |
|
i64x2 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
---- |
0xc0 |
-- |
|
i64x2.neg |
0xc1 |
:+1: |
:+1: |
---- |
0xc2 |
-- |
|
---- |
0xc3 |
-- |
|
---- |
0xc4 |
-- |
|
---- |
0xc5 |
-- |
|
---- |
0xc6 |
-- |
|
---- |
0xc7 |
-- |
|
---- |
0xc8 |
-- |
|
---- |
0xc9 |
-- |
|
---- |
0xca |
-- |
|
i64x2.shl |
0xcb |
:+1: |
:+1: |
i64x2.shr_s |
0xcc |
:+1: |
:+1: |
i64x2.shr_u |
0xcd |
:+1: |
:+1: |
i64x2.add |
0xce |
:+1: |
:+1: |
---- |
0xcf |
-- |
|
---- |
0xd0 |
-- |
|
i64x2.sub |
0xd1 |
:+1: |
:+1: |
---- |
0xd2 |
-- |
|
---- |
0xd3 |
-- |
|
---- |
0xd4 |
-- |
|
i64x2.mul |
0xd5 |
:+1: |
:+1: |
---- |
0xd6 |
-- |
|
---- |
0xd7 |
-- |
|
f32x4 Op |
Opcode |
Old Backend Status |
VCode Status |
f32x4.ceil |
0xd8 |
:question: |
:+1: |
f32x4.floor |
0xd9 |
:question: |
:+1: |
f32x4.trunc |
0xda |
:question: |
:+1: |
f32x4.nearest |
0xdb |
:question: |
:+1: |
f32x4.abs |
0xe0 |
:+1: |
:+1: |
f32x4.neg |
0xe1 |
:+1: |
:+1: |
---- round ---- |
0xe2 |
-- |
|
f32x4.sqrt |
0xe3 |
:+1: |
:+1: |
f32x4.add |
0xe4 |
:+1: |
:+1: |
f32x4.sub |
0xe5 |
:+1: |
:+1: |
f32x4.mul |
0xe6 |
:+1: |
:+1: |
f32x4.div |
0xe7 |
:+1: |
:+1: |
f32x4.min |
0xe8 |
:+1: |
:+1: |
f32x4.max |
0xe9 |
:+1: |
:+1: |
f32x4.pmin |
0xea |
:question: |
:+1: |
f32x4.pmax |
0xeb |
:question: |
:+1: |
f64x2 Op |
Opcode |
Old Backend Status |
VCode Status |
f64x2.ceil |
0xdc |
:question: |
:+1: |
f64x2.floor |
0xdd |
:question: |
:+1: |
f64x2.trunc |
0xde |
:question: |
:+1: |
f64x2.nearest |
0xdf |
:question: |
:+1: |
f64x2.abs |
0xec |
:+1: |
:+1: |
f64x2.neg |
0xed |
:+1: |
:+1: |
---- round ---- |
0xee |
-- |
|
f64x2.sqrt |
0xef |
:+1: |
:+1: |
f64x2.add |
0xf0 |
:+1: |
:+1: |
f64x2.sub |
0xf1 |
:+1: |
:+1: |
f64x2.mul |
0xf2 |
:+1: |
:+1: |
f64x2.div |
0xf3 |
:+1: |
:+1: |
f64x2.min |
0xf4 |
:+1: |
:+1: |
f64x2.max |
0xf5 |
:+1: |
:+1: |
f64x2.pmin |
0xf6 |
:question: |
:+1: |
f64x2.pmax |
0xf7 |
:question: |
:+1: |
Conversion Op |
Opcode |
Old Backend Status |
VCode Status |
i32x4.trunc_sat_f32x4_s |
0xf8 |
:question: |
:+1: |
i32x4.trunc_sat_f32x4_u |
0xf9 |
:question: |
:+1: |
f32x4.convert_i32x4_s |
0xfa |
:+1: |
:+1: |
f32x4.convert_i32x4_u |
0xfb |
:question: |
:+1: |
jlb6740 edited Issue #2272:
Last Update: 1/14/2021
Loads |
Opcode |
Old Backend Status |
VCode Status |
v128.load |
0x00 |
:+1: |
:+1: |
v128.load32_zero |
0xfc |
-- |
:+1: |
v128.load64_zero |
0xfd |
-- |
:+1: |
v128.load8x8_s |
0x01 |
:+1: |
:+1: |
v128.load8x8_u |
0x02 |
:+1: |
:+1: |
v128.load16x4_s |
0x03 |
:+1: |
:+1: |
v128.load16x4_u |
0x04 |
:+1: |
:+1: |
v128.load32x2_s |
0x05 |
:+1: |
:+1: |
v128.load32x2_u |
0x06 |
:+1: |
:+1: |
v128.load8_splat |
0x07 |
:+1: |
:+1: |
v128.load16_splat |
0x08 |
:+1: |
:+1: |
v128.load32_splat |
0x09 |
:+1: |
:+1: |
v128.load64_splat |
0x0a |
:+1: |
:+1: |
v128.load32_zero |
0xfc |
:+1: |
@jlb6740 |
v128.load64_zero |
0xfd |
:+1: |
@jlb6740 |
Stores |
Opcode |
Old Backend Status |
VCode Status |
v128.store |
0x0b |
:+1: |
:+1: |
Basic operation |
Opcode |
Old Backend Status |
VCode Status |
v128.const |
0x0c |
:+1: |
:+1: |
i8x16.shuffle |
0x0d |
:+1: |
:+1: |
i8x16.swizzle |
0x0e |
:+1: |
:+1: |
Splat operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.splat |
0x0f |
:+1: |
:+1: |
i16x8.splat |
0x10 |
:+1: |
:+1: |
i32x4.splat |
0x11 |
:+1: |
:+1: |
i64x2.splat |
0x12 |
:+1: |
:+1: |
f32x4.splat |
0x13 |
:+1: |
:+1: |
f64x2.splat |
0x14 |
:+1: |
:+1: |
Lane operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.extract_lane_s |
0x15 |
:+1: |
:+1: |
i8x16.extract_lane_u |
0x16 |
:+1: |
:+1: |
i8x16.replace_lane |
0x17 |
:+1: |
:+1: |
i16x8.extract_lane_s |
0x18 |
:+1: |
:+1: |
i16x8.extract_lane_u |
0x19 |
:+1: |
:+1: |
i16x8.replace_lane |
0x1a |
:+1: |
:+1: |
i32x4.extract_lane |
0x1b |
:+1: |
:+1: |
i32x4.replace_lane |
0x1c |
:+1: |
:+1: |
i64x2.extract_lane |
0x1d |
:+1: |
:+1: |
i64x2.replace_lane |
0x1e |
:+1: |
:+1: |
f32x4.extract_lane |
0x1f |
:+1: |
:+1: |
f32x4.replace_lane |
0x20 |
:+1: |
:+1: |
f64x2.extract_lane |
0x21 |
:+1: |
:+1: |
f64x2.replace_lane |
0x22 |
:+1: |
:+1: |
Integer Cmp |
Opcode |
Old Backend Status |
VCode Status |
i8x16.eq |
0x23 |
:+1: |
:+1: |
i8x16.ne |
0x24 |
:+1: |
:+1: |
i8x16.lt_s |
0x25 |
:+1: |
:+1: |
i8x16.lt_u |
0x26 |
:+1: |
:+1: |
i8x16.gt_s |
0x27 |
:+1: |
:+1: |
i8x16.gt_u |
0x28 |
:+1: |
:+1: |
i8x16.le_s |
0x29 |
:+1: |
:+1: |
i8x16.le_u |
0x2a |
:+1: |
:+1: |
i8x16.ge_s |
0x2b |
:+1: |
:+1: |
i8x16.ge_u |
0x2c |
:+1: |
:+1: |
i16x8.eq |
0x2d |
:+1: |
:+1: |
i16x8.ne |
0x2e |
:+1: |
:+1: |
i16x8.lt_s |
0x2f |
:+1: |
:+1: |
i16x8.lt_u |
0x30 |
:+1: |
:+1: |
i16x8.gt_s |
0x31 |
:+1: |
:+1: |
i16x8.gt_u |
0x32 |
:+1: |
:+1: |
i16x8.le_s |
0x33 |
:+1: |
:+1: |
i16x8.le_u |
0x34 |
:+1: |
:+1: |
i16x8.ge_s |
0x35 |
:+1: |
:+1: |
i16x8.ge_u |
0x36 |
:+1: |
:+1: |
i32x4.eq |
0x37 |
:+1: |
:+1: |
i32x4.ne |
0x38 |
:+1: |
:+1: |
i32x4.lt_s |
0x39 |
:+1: |
:+1: |
i32x4.lt_u |
0x3a |
:+1: |
:+1: |
i32x4.gt_s |
0x3b |
:+1: |
:+1: |
i32x4.gt_u |
0x3c |
:+1: |
:+1: |
i32x4.le_s |
0x3d |
:+1: |
:+1: |
i32x4.le_u |
0x3e |
:+1: |
:+1: |
i32x4.ge_s |
0x3f |
:+1: |
:+1: |
i32x4.ge_u |
0x40 |
:+1: |
:+1: |
Float Cmp |
Opcode |
Old Backend Status |
VCode Status |
f32x4.eq |
0x41 |
:+1: |
:+1: |
f32x4.ne |
0x42 |
:+1: |
:+1: |
f32x4.lt |
0x43 |
:+1: |
:+1: |
f32x4.gt |
0x44 |
:+1: |
:+1: |
f32x4.le |
0x45 |
:+1: |
:+1: |
f32x4.ge |
0x46 |
:+1: |
:+1: |
f64x2.eq |
0x47 |
:+1: |
:+1: |
f64x2.ne |
0x48 |
:+1: |
:+1: |
f64x2.lt |
0x49 |
:+1: |
:+1: |
f64x2.gt |
0x4a |
:+1: |
:+1: |
f64x2.le |
0x4b |
:+1: |
:+1: |
f64x2.ge |
0x4c |
:+1: |
:+1: |
v128 Op |
Opcode |
Old Backend Status |
VCode Status |
v128.not |
0x4d |
:+1: |
:+1: |
v128.and |
0x4e |
:+1: |
:+1: |
v128.andnot |
0x4f |
:+1: |
:+1: |
v128.or |
0x50 |
:+1: |
:+1: |
v128.xor |
0x51 |
:+1: |
:+1: |
v128.bitselect |
0x52 |
:+1: |
:+1: |
i8x16 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i8x16.abs |
0x60 |
:+1: |
:+1: |
i8x16.neg |
0x61 |
:+1: |
:+1: |
i8x16.any_true |
0x62 |
:+1: |
:+1: |
i8x16.all_true |
0x63 |
:+1: |
:+1: |
i8x16.bitmask |
0x64 |
:question: |
:+1: |
i8x16.narrow_i16x8_s |
0x65 |
:+1: |
:+1: |
i8x16.narrow_i16x8_u |
0x66 |
:+1: |
:+1: |
---- widen ---- |
0x67 |
-- |
|
---- widen ---- |
0x68 |
-- |
|
---- widen ---- |
0x69 |
-- |
|
---- widen ---- |
0x6a |
-- |
|
i8x16.shl |
0x6b |
:+1: |
:+1: |
i8x16.shr_s |
0x6c |
:+1: |
:+1: |
i8x16.shr_u |
0x6d |
:+1: |
:+1: |
i8x16.add |
0x6e |
:+1: |
:+1: |
i8x16.add_sat_s |
0x6f |
:+1: |
:+1: |
i8x16.add_sat_u |
0x70 |
:+1: |
:+1: |
i8x16.sub |
0x71 |
:+1: |
:+1: |
i8x16.sub_sat_s |
0x72 |
:+1: |
:+1: |
i8x16.sub_sat_u |
0x73 |
:+1: |
:+1: |
------------ |
0x74 |
-- |
-- |
---- mul ---- |
0x75 |
:question: |
|
i8x16.min_s |
0x76 |
:+1: |
:+1: |
i8x16.min_u |
0x77 |
:+1: |
:+1: |
i8x16.max_s |
0x78 |
:+1: |
:+1: |
i8x16.max_u |
0x79 |
:+1: |
:+1: |
------------ |
0x7a |
-- |
|
i8x16.avgr_u |
0x7b |
:+1: |
:+1: |
i16x8 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i16x8.abs |
0x80 |
:+1: |
:+1: |
i16x8.neg |
0x81 |
:+1: |
:+1: |
i16x8.any_true |
0x82 |
:+1: |
:+1: |
i16x8.all_true |
0x83 |
:+1: |
:+1: |
i16x8.bitmask |
0x84 |
:question: |
:+1: |
i16x8.narrow_i32x4_s |
0x85 |
:+1: |
:+1: |
i16x8.narrow_i32x4_u |
0x86 |
:+1: |
:+1: |
i16x8.widen_low_i8x16_s |
0x87 |
:+1: |
:+1: |
i16x8.widen_high_i8x16_s |
0x88 |
:+1: |
:+1: |
i16x8.widen_low_i8x16_u |
0x89 |
:+1: |
:+1: |
i16x8.widen_high_i8x16_u |
0x8a |
:+1: |
:+1: |
i16x8.shl |
0x8b |
:+1: |
:+1: |
i16x8.shr_s |
0x8c |
:+1: |
:+1: |
i16x8.shr_u |
0x8d |
:+1: |
:+1: |
i16x8.add |
0x8e |
:+1: |
:+1: |
i16x8.add_sat_s |
0x8f |
:+1: |
:+1: |
i16x8.add_sat_u |
0x90 |
:+1: |
:+1: |
i16x8.sub |
0x91 |
:+1: |
:+1: |
i16x8.sub_sat_s |
0x92 |
:+1: |
:+1: |
i16x8.sub_sat_u |
0x93 |
:+1: |
:+1: |
------------ |
0x94 |
-- |
-- |
i16x8.mul |
0x95 |
:+1: |
:+1: |
i16x8.min_s |
0x96 |
:+1: |
:+1: |
i16x8.min_u |
0x97 |
:+1: |
:+1: |
i16x8.max_s |
0x98 |
:+1: |
:+1: |
i16x8.max_u |
0x99 |
:+1: |
:+1: |
----------- |
0x9a |
-- |
|
i16x8.avgr_u |
0x9b |
:+1: |
:+1: |
i32x4 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i32x4.abs |
0xa0 |
:+1: |
:+1: |
i32x4.neg |
0xa1 |
:+1: |
:+1: |
i32x4.any_true |
0xa2 |
:+1: |
:+1: |
i32x4.all_true |
0xa3 |
:+1: |
:+1: |
i32x4.bitmask |
0xa4 |
:question: |
:+1: |
---- narrow ---- |
0xa5 |
-- |
|
---- narrow ---- |
0xa6 |
-- |
|
i32x4.widen_low_i16x8_s |
0xa7 |
:+1: |
:+1: |
i32x4.widen_high_i16x8_s |
0xa8 |
:+1: |
:+1: |
i32x4.widen_low_i16x8_u |
0xa9 |
:+1: |
:+1: |
i32x4.widen_high_i16x8_u |
0xaa |
:+1: |
:+1: |
i32x4.shl |
0xab |
:+1: |
:+1: |
i32x4.shr_s |
0xac |
:+1: |
:+1: |
i32x4.shr_u |
0xad |
:+1: |
:+1: |
i32x4.add |
0xae |
:+1: |
:+1: |
---- add_sat ---- |
0xaf |
-- |
|
---- add_sat ---- |
0xb0 |
-- |
|
i32x4.sub |
0xb1 |
:+1: |
:+1: |
---- sub_sat ---- |
0xb2 |
-- |
|
---- sub_sat ---- |
0xb3 |
-- |
|
---- dot ---- |
0xb4 |
-- |
|
i32x4.mul |
0xb5 |
:+1: |
:+1: |
i32x4.min_s |
0xb6 |
:+1: |
:+1: |
i32x4.min_u |
0xb7 |
:+1: |
:+1: |
i32x4.max_s |
0xb8 |
:+1: |
:+1: |
i32x4.max_u |
0xb9 |
:+1: |
:+1: |
i32x4.dot_i16x8_s |
0xba |
-- |
@abrown |
---- avgr_u ---- |
0xbb |
-- |
|
i64x2 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
---- |
0xc0 |
-- |
|
i64x2.neg |
0xc1 |
:+1: |
:+1: |
---- |
0xc2 |
-- |
|
---- |
0xc3 |
-- |
|
---- |
0xc4 |
-- |
|
---- |
0xc5 |
-- |
|
---- |
0xc6 |
-- |
|
---- |
0xc7 |
-- |
|
---- |
0xc8 |
-- |
|
---- |
0xc9 |
-- |
|
---- |
0xca |
-- |
|
i64x2.shl |
0xcb |
:+1: |
:+1: |
i64x2.shr_s |
0xcc |
:+1: |
:+1: |
i64x2.shr_u |
0xcd |
:+1: |
:+1: |
i64x2.add |
0xce |
:+1: |
:+1: |
---- |
0xcf |
-- |
|
---- |
0xd0 |
-- |
|
i64x2.sub |
0xd1 |
:+1: |
:+1: |
---- |
0xd2 |
-- |
|
---- |
0xd3 |
-- |
|
---- |
0xd4 |
-- |
|
i64x2.mul |
0xd5 |
:+1: |
:+1: |
---- |
0xd6 |
-- |
|
---- |
0xd7 |
-- |
|
f32x4 Op |
Opcode |
Old Backend Status |
VCode Status |
f32x4.ceil |
0xd8 |
:question: |
:+1: |
f32x4.floor |
0xd9 |
:question: |
:+1: |
f32x4.trunc |
0xda |
:question: |
:+1: |
f32x4.nearest |
0xdb |
:question: |
:+1: |
f32x4.abs |
0xe0 |
:+1: |
:+1: |
f32x4.neg |
0xe1 |
:+1: |
:+1: |
---- round ---- |
0xe2 |
-- |
|
f32x4.sqrt |
0xe3 |
:+1: |
:+1: |
f32x4.add |
0xe4 |
:+1: |
:+1: |
f32x4.sub |
0xe5 |
:+1: |
:+1: |
f32x4.mul |
0xe6 |
:+1: |
:+1: |
f32x4.div |
0xe7 |
:+1: |
:+1: |
f32x4.min |
0xe8 |
:+1: |
:+1: |
f32x4.max |
0xe9 |
:+1: |
:+1: |
f32x4.pmin |
0xea |
:question: |
:+1: |
f32x4.pmax |
0xeb |
:question: |
:+1: |
f64x2 Op |
Opcode |
Old Backend Status |
VCode Status |
f64x2.ceil |
0xdc |
:question: |
:+1: |
f64x2.floor |
0xdd |
:question: |
:+1: |
f64x2.trunc |
0xde |
:question: |
:+1: |
f64x2.nearest |
0xdf |
:question: |
:+1: |
f64x2.abs |
0xec |
:+1: |
:+1: |
f64x2.neg |
0xed |
:+1: |
:+1: |
---- round ---- |
0xee |
-- |
|
f64x2.sqrt |
0xef |
:+1: |
:+1: |
f64x2.add |
0xf0 |
:+1: |
:+1: |
f64x2.sub |
0xf1 |
:+1: |
:+1: |
f64x2.mul |
0xf2 |
:+1: |
:+1: |
f64x2.div |
0xf3 |
:+1: |
:+1: |
f64x2.min |
0xf4 |
:+1: |
:+1: |
f64x2.max |
0xf5 |
:+1: |
:+1: |
f64x2.pmin |
0xf6 |
:question: |
:+1: |
f64x2.pmax |
0xf7 |
:question: |
:+1: |
Conversion Op |
Opcode |
Old Backend Status |
VCode Status |
i32x4.trunc_sat_f32x4_s |
0xf8 |
:question: |
:+1: |
i32x4.trunc_sat_f32x4_u |
0xf9 |
:question: |
:+1: |
f32x4.convert_i32x4_s |
0xfa |
:+1: |
:+1: |
f32x4.convert_i32x4_u |
0xfb |
:question: |
:+1: |
jlb6740 edited Issue #2272:
Last Update: 1/14/2021
Loads |
Opcode |
Old Backend Status |
VCode Status |
v128.load |
0x00 |
:+1: |
:+1: |
v128.load32_zero |
0xfc |
-- |
:+1: |
v128.load64_zero |
0xfd |
-- |
:+1: |
v128.load8x8_s |
0x01 |
:+1: |
:+1: |
v128.load8x8_u |
0x02 |
:+1: |
:+1: |
v128.load16x4_s |
0x03 |
:+1: |
:+1: |
v128.load16x4_u |
0x04 |
:+1: |
:+1: |
v128.load32x2_s |
0x05 |
:+1: |
:+1: |
v128.load32x2_u |
0x06 |
:+1: |
:+1: |
v128.load8_splat |
0x07 |
:+1: |
:+1: |
v128.load16_splat |
0x08 |
:+1: |
:+1: |
v128.load32_splat |
0x09 |
:+1: |
:+1: |
v128.load64_splat |
0x0a |
:+1: |
:+1: |
v128.load32_zero |
0xfc |
:+1: |
@jlb6740 |
v128.load64_zero |
0xfd |
:+1: |
@jlb6740 |
Stores |
Opcode |
Old Backend Status |
VCode Status |
v128.store |
0x0b |
:+1: |
:+1: |
Basic operation |
Opcode |
Old Backend Status |
VCode Status |
v128.const |
0x0c |
:+1: |
:+1: |
i8x16.shuffle |
0x0d |
:+1: |
:+1: |
i8x16.swizzle |
0x0e |
:+1: |
:+1: |
Splat operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.splat |
0x0f |
:+1: |
:+1: |
i16x8.splat |
0x10 |
:+1: |
:+1: |
i32x4.splat |
0x11 |
:+1: |
:+1: |
i64x2.splat |
0x12 |
:+1: |
:+1: |
f32x4.splat |
0x13 |
:+1: |
:+1: |
f64x2.splat |
0x14 |
:+1: |
:+1: |
Lane operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.extract_lane_s |
0x15 |
:+1: |
:+1: |
i8x16.extract_lane_u |
0x16 |
:+1: |
:+1: |
i8x16.replace_lane |
0x17 |
:+1: |
:+1: |
i16x8.extract_lane_s |
0x18 |
:+1: |
:+1: |
i16x8.extract_lane_u |
0x19 |
:+1: |
:+1: |
i16x8.replace_lane |
0x1a |
:+1: |
:+1: |
i32x4.extract_lane |
0x1b |
:+1: |
:+1: |
i32x4.replace_lane |
0x1c |
:+1: |
:+1: |
i64x2.extract_lane |
0x1d |
:+1: |
:+1: |
i64x2.replace_lane |
0x1e |
:+1: |
:+1: |
f32x4.extract_lane |
0x1f |
:+1: |
:+1: |
f32x4.replace_lane |
0x20 |
:+1: |
:+1: |
f64x2.extract_lane |
0x21 |
:+1: |
:+1: |
f64x2.replace_lane |
0x22 |
:+1: |
:+1: |
Integer Cmp |
Opcode |
Old Backend Status |
VCode Status |
i8x16.eq |
0x23 |
:+1: |
:+1: |
i8x16.ne |
0x24 |
:+1: |
:+1: |
i8x16.lt_s |
0x25 |
:+1: |
:+1: |
i8x16.lt_u |
0x26 |
:+1: |
:+1: |
i8x16.gt_s |
0x27 |
:+1: |
:+1: |
i8x16.gt_u |
0x28 |
:+1: |
:+1: |
i8x16.le_s |
0x29 |
:+1: |
:+1: |
i8x16.le_u |
0x2a |
:+1: |
:+1: |
i8x16.ge_s |
0x2b |
:+1: |
:+1: |
i8x16.ge_u |
0x2c |
:+1: |
:+1: |
i16x8.eq |
0x2d |
:+1: |
:+1: |
i16x8.ne |
0x2e |
:+1: |
:+1: |
i16x8.lt_s |
0x2f |
:+1: |
:+1: |
i16x8.lt_u |
0x30 |
:+1: |
:+1: |
i16x8.gt_s |
0x31 |
:+1: |
:+1: |
i16x8.gt_u |
0x32 |
:+1: |
:+1: |
i16x8.le_s |
0x33 |
:+1: |
:+1: |
i16x8.le_u |
0x34 |
:+1: |
:+1: |
i16x8.ge_s |
0x35 |
:+1: |
:+1: |
i16x8.ge_u |
0x36 |
:+1: |
:+1: |
i32x4.eq |
0x37 |
:+1: |
:+1: |
i32x4.ne |
0x38 |
:+1: |
:+1: |
i32x4.lt_s |
0x39 |
:+1: |
:+1: |
i32x4.lt_u |
0x3a |
:+1: |
:+1: |
i32x4.gt_s |
0x3b |
:+1: |
:+1: |
i32x4.gt_u |
0x3c |
:+1: |
:+1: |
i32x4.le_s |
0x3d |
:+1: |
:+1: |
i32x4.le_u |
0x3e |
:+1: |
:+1: |
i32x4.ge_s |
0x3f |
:+1: |
:+1: |
i32x4.ge_u |
0x40 |
:+1: |
:+1: |
Float Cmp |
Opcode |
Old Backend Status |
VCode Status |
f32x4.eq |
0x41 |
:+1: |
:+1: |
f32x4.ne |
0x42 |
:+1: |
:+1: |
f32x4.lt |
0x43 |
:+1: |
:+1: |
f32x4.gt |
0x44 |
:+1: |
:+1: |
f32x4.le |
0x45 |
:+1: |
:+1: |
f32x4.ge |
0x46 |
:+1: |
:+1: |
f64x2.eq |
0x47 |
:+1: |
:+1: |
f64x2.ne |
0x48 |
:+1: |
:+1: |
f64x2.lt |
0x49 |
:+1: |
:+1: |
f64x2.gt |
0x4a |
:+1: |
:+1: |
f64x2.le |
0x4b |
:+1: |
:+1: |
f64x2.ge |
0x4c |
:+1: |
:+1: |
v128 Op |
Opcode |
Old Backend Status |
VCode Status |
v128.not |
0x4d |
:+1: |
:+1: |
v128.and |
0x4e |
:+1: |
:+1: |
v128.andnot |
0x4f |
:+1: |
:+1: |
v128.or |
0x50 |
:+1: |
:+1: |
v128.xor |
0x51 |
:+1: |
:+1: |
v128.bitselect |
0x52 |
:+1: |
:+1: |
i8x16 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i8x16.abs |
0x60 |
:+1: |
:+1: |
i8x16.neg |
0x61 |
:+1: |
:+1: |
i8x16.any_true |
0x62 |
:+1: |
:+1: |
i8x16.all_true |
0x63 |
:+1: |
:+1: |
i8x16.bitmask |
0x64 |
:question: |
:+1: |
i8x16.narrow_i16x8_s |
0x65 |
:+1: |
:+1: |
i8x16.narrow_i16x8_u |
0x66 |
:+1: |
:+1: |
---- widen ---- |
0x67 |
-- |
|
---- widen ---- |
0x68 |
-- |
|
---- widen ---- |
0x69 |
-- |
|
---- widen ---- |
0x6a |
-- |
|
i8x16.shl |
0x6b |
:+1: |
:+1: |
i8x16.shr_s |
0x6c |
:+1: |
:+1: |
i8x16.shr_u |
0x6d |
:+1: |
:+1: |
i8x16.add |
0x6e |
:+1: |
:+1: |
i8x16.add_sat_s |
0x6f |
:+1: |
:+1: |
i8x16.add_sat_u |
0x70 |
:+1: |
:+1: |
i8x16.sub |
0x71 |
:+1: |
:+1: |
i8x16.sub_sat_s |
0x72 |
:+1: |
:+1: |
i8x16.sub_sat_u |
0x73 |
:+1: |
:+1: |
------------ |
0x74 |
-- |
-- |
---- mul ---- |
0x75 |
:question: |
|
i8x16.min_s |
0x76 |
:+1: |
:+1: |
i8x16.min_u |
0x77 |
:+1: |
:+1: |
i8x16.max_s |
0x78 |
:+1: |
:+1: |
i8x16.max_u |
0x79 |
:+1: |
:+1: |
------------ |
0x7a |
-- |
|
i8x16.avgr_u |
0x7b |
:+1: |
:+1: |
i16x8 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i16x8.abs |
0x80 |
:+1: |
:+1: |
i16x8.neg |
0x81 |
:+1: |
:+1: |
i16x8.any_true |
0x82 |
:+1: |
:+1: |
i16x8.all_true |
0x83 |
:+1: |
:+1: |
i16x8.bitmask |
0x84 |
:question: |
:+1: |
i16x8.narrow_i32x4_s |
0x85 |
:+1: |
:+1: |
i16x8.narrow_i32x4_u |
0x86 |
:+1: |
:+1: |
i16x8.widen_low_i8x16_s |
0x87 |
:+1: |
:+1: |
i16x8.widen_high_i8x16_s |
0x88 |
:+1: |
:+1: |
i16x8.widen_low_i8x16_u |
0x89 |
:+1: |
:+1: |
i16x8.widen_high_i8x16_u |
0x8a |
:+1: |
:+1: |
i16x8.shl |
0x8b |
:+1: |
:+1: |
i16x8.shr_s |
0x8c |
:+1: |
:+1: |
i16x8.shr_u |
0x8d |
:+1: |
:+1: |
i16x8.add |
0x8e |
:+1: |
:+1: |
i16x8.add_sat_s |
0x8f |
:+1: |
:+1: |
i16x8.add_sat_u |
0x90 |
:+1: |
:+1: |
i16x8.sub |
0x91 |
:+1: |
:+1: |
i16x8.sub_sat_s |
0x92 |
:+1: |
:+1: |
i16x8.sub_sat_u |
0x93 |
:+1: |
:+1: |
------------ |
0x94 |
-- |
-- |
i16x8.mul |
0x95 |
:+1: |
:+1: |
i16x8.min_s |
0x96 |
:+1: |
:+1: |
i16x8.min_u |
0x97 |
:+1: |
:+1: |
i16x8.max_s |
0x98 |
:+1: |
:+1: |
i16x8.max_u |
0x99 |
:+1: |
:+1: |
----------- |
0x9a |
-- |
|
i16x8.avgr_u |
0x9b |
:+1: |
:+1: |
i32x4 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i32x4.abs |
0xa0 |
:+1: |
:+1: |
i32x4.neg |
0xa1 |
:+1: |
:+1: |
i32x4.any_true |
0xa2 |
:+1: |
:+1: |
i32x4.all_true |
0xa3 |
:+1: |
:+1: |
i32x4.bitmask |
0xa4 |
:question: |
:+1: |
---- narrow ---- |
0xa5 |
-- |
|
---- narrow ---- |
0xa6 |
-- |
|
i32x4.widen_low_i16x8_s |
0xa7 |
:+1: |
:+1: |
i32x4.widen_high_i16x8_s |
0xa8 |
:+1: |
:+1: |
i32x4.widen_low_i16x8_u |
0xa9 |
:+1: |
:+1: |
i32x4.widen_high_i16x8_u |
0xaa |
:+1: |
:+1: |
i32x4.shl |
0xab |
:+1: |
:+1: |
i32x4.shr_s |
0xac |
:+1: |
:+1: |
i32x4.shr_u |
0xad |
:+1: |
:+1: |
i32x4.add |
0xae |
:+1: |
:+1: |
---- add_sat ---- |
0xaf |
-- |
|
---- add_sat ---- |
0xb0 |
-- |
|
i32x4.sub |
0xb1 |
:+1: |
:+1: |
---- sub_sat ---- |
0xb2 |
-- |
|
---- sub_sat ---- |
0xb3 |
-- |
|
---- dot ---- |
0xb4 |
-- |
|
i32x4.mul |
0xb5 |
:+1: |
:+1: |
i32x4.min_s |
0xb6 |
:+1: |
:+1: |
i32x4.min_u |
0xb7 |
:+1: |
:+1: |
i32x4.max_s |
0xb8 |
:+1: |
:+1: |
i32x4.max_u |
0xb9 |
:+1: |
:+1: |
i32x4.dot_i16x8_s |
0xba |
-- |
@abrown |
---- avgr_u ---- |
0xbb |
-- |
|
i64x2 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
---- |
0xc0 |
-- |
|
i64x2.neg |
0xc1 |
:+1: |
:+1: |
---- |
0xc2 |
-- |
|
---- |
0xc3 |
-- |
|
i64x2.bitmask |
0xc4 |
-- |
-- |
---- |
0xc5 |
-- |
|
---- |
0xc6 |
-- |
|
---- |
0xc7 |
-- |
|
---- |
0xc8 |
-- |
|
---- |
0xc9 |
-- |
|
---- |
0xca |
-- |
|
i64x2.shl |
0xcb |
:+1: |
:+1: |
i64x2.shr_s |
0xcc |
:+1: |
:+1: |
i64x2.shr_u |
0xcd |
:+1: |
:+1: |
i64x2.add |
0xce |
:+1: |
:+1: |
---- |
0xcf |
-- |
|
---- |
0xd0 |
-- |
|
i64x2.sub |
0xd1 |
:+1: |
:+1: |
---- |
0xd2 |
-- |
|
---- |
0xd3 |
-- |
|
---- |
0xd4 |
-- |
|
i64x2.mul |
0xd5 |
:+1: |
:+1: |
---- |
0xd6 |
-- |
|
---- |
0xd7 |
-- |
|
f32x4 Op |
Opcode |
Old Backend Status |
VCode Status |
f32x4.ceil |
0xd8 |
:question: |
:+1: |
f32x4.floor |
0xd9 |
:question: |
:+1: |
f32x4.trunc |
0xda |
:question: |
:+1: |
f32x4.nearest |
0xdb |
:question: |
:+1: |
f32x4.abs |
0xe0 |
:+1: |
:+1: |
f32x4.neg |
0xe1 |
:+1: |
:+1: |
---- round ---- |
0xe2 |
-- |
|
f32x4.sqrt |
0xe3 |
:+1: |
:+1: |
f32x4.add |
0xe4 |
:+1: |
:+1: |
f32x4.sub |
0xe5 |
:+1: |
:+1: |
f32x4.mul |
0xe6 |
:+1: |
:+1: |
f32x4.div |
0xe7 |
:+1: |
:+1: |
f32x4.min |
0xe8 |
:+1: |
:+1: |
f32x4.max |
0xe9 |
:+1: |
:+1: |
f32x4.pmin |
0xea |
:question: |
:+1: |
f32x4.pmax |
0xeb |
:question: |
:+1: |
f64x2 Op |
Opcode |
Old Backend Status |
VCode Status |
f64x2.ceil |
0xdc |
:question: |
:+1: |
f64x2.floor |
0xdd |
:question: |
:+1: |
f64x2.trunc |
0xde |
:question: |
:+1: |
f64x2.nearest |
0xdf |
:question: |
:+1: |
f64x2.abs |
0xec |
:+1: |
:+1: |
f64x2.neg |
0xed |
:+1: |
:+1: |
---- round ---- |
0xee |
-- |
|
f64x2.sqrt |
0xef |
:+1: |
:+1: |
f64x2.add |
0xf0 |
:+1: |
:+1: |
f64x2.sub |
0xf1 |
:+1: |
:+1: |
f64x2.mul |
0xf2 |
:+1: |
:+1: |
f64x2.div |
0xf3 |
:+1: |
:+1: |
f64x2.min |
0xf4 |
:+1: |
:+1: |
f64x2.max |
0xf5 |
:+1: |
:+1: |
f64x2.pmin |
0xf6 |
:question: |
:+1: |
f64x2.pmax |
0xf7 |
:question: |
:+1: |
Conversion Op |
Opcode |
Old Backend Status |
VCode Status |
i32x4.trunc_sat_f32x4_s |
0xf8 |
:question: |
:+1: |
i32x4.trunc_sat_f32x4_u |
0xf9 |
:question: |
:+1: |
f32x4.convert_i32x4_s |
0xfa |
:+1: |
:+1: |
f32x4.convert_i32x4_u |
0xfb |
:question: |
:+1: |
jlb6740 edited Issue #2272:
Last Update: 1/14/2021
Loads |
Opcode |
Old Backend Status |
VCode Status |
v128.load |
0x00 |
:+1: |
:+1: |
v128.load32_zero |
0xfc |
-- |
:+1: |
v128.load64_zero |
0xfd |
-- |
:+1: |
v128.load8x8_s |
0x01 |
:+1: |
:+1: |
v128.load8x8_u |
0x02 |
:+1: |
:+1: |
v128.load16x4_s |
0x03 |
:+1: |
:+1: |
v128.load16x4_u |
0x04 |
:+1: |
:+1: |
v128.load32x2_s |
0x05 |
:+1: |
:+1: |
v128.load32x2_u |
0x06 |
:+1: |
:+1: |
v128.load8_splat |
0x07 |
:+1: |
:+1: |
v128.load16_splat |
0x08 |
:+1: |
:+1: |
v128.load32_splat |
0x09 |
:+1: |
:+1: |
v128.load64_splat |
0x0a |
:+1: |
:+1: |
v128.load32_zero |
0xfc |
:+1: |
@jlb6740 |
v128.load64_zero |
0xfd |
:+1: |
@jlb6740 |
Stores |
Opcode |
Old Backend Status |
VCode Status |
v128.store |
0x0b |
:+1: |
:+1: |
Basic operation |
Opcode |
Old Backend Status |
VCode Status |
v128.const |
0x0c |
:+1: |
:+1: |
i8x16.shuffle |
0x0d |
:+1: |
:+1: |
i8x16.swizzle |
0x0e |
:+1: |
:+1: |
Splat operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.splat |
0x0f |
:+1: |
:+1: |
i16x8.splat |
0x10 |
:+1: |
:+1: |
i32x4.splat |
0x11 |
:+1: |
:+1: |
i64x2.splat |
0x12 |
:+1: |
:+1: |
f32x4.splat |
0x13 |
:+1: |
:+1: |
f64x2.splat |
0x14 |
:+1: |
:+1: |
Lane operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.extract_lane_s |
0x15 |
:+1: |
:+1: |
i8x16.extract_lane_u |
0x16 |
:+1: |
:+1: |
i8x16.replace_lane |
0x17 |
:+1: |
:+1: |
i16x8.extract_lane_s |
0x18 |
:+1: |
:+1: |
i16x8.extract_lane_u |
0x19 |
:+1: |
:+1: |
i16x8.replace_lane |
0x1a |
:+1: |
:+1: |
i32x4.extract_lane |
0x1b |
:+1: |
:+1: |
i32x4.replace_lane |
0x1c |
:+1: |
:+1: |
i64x2.extract_lane |
0x1d |
:+1: |
:+1: |
i64x2.replace_lane |
0x1e |
:+1: |
:+1: |
f32x4.extract_lane |
0x1f |
:+1: |
:+1: |
f32x4.replace_lane |
0x20 |
:+1: |
:+1: |
f64x2.extract_lane |
0x21 |
:+1: |
:+1: |
f64x2.replace_lane |
0x22 |
:+1: |
:+1: |
Integer Cmp |
Opcode |
Old Backend Status |
VCode Status |
i8x16.eq |
0x23 |
:+1: |
:+1: |
i8x16.ne |
0x24 |
:+1: |
:+1: |
i8x16.lt_s |
0x25 |
:+1: |
:+1: |
i8x16.lt_u |
0x26 |
:+1: |
:+1: |
i8x16.gt_s |
0x27 |
:+1: |
:+1: |
i8x16.gt_u |
0x28 |
:+1: |
:+1: |
i8x16.le_s |
0x29 |
:+1: |
:+1: |
i8x16.le_u |
0x2a |
:+1: |
:+1: |
i8x16.ge_s |
0x2b |
:+1: |
:+1: |
i8x16.ge_u |
0x2c |
:+1: |
:+1: |
i16x8.eq |
0x2d |
:+1: |
:+1: |
i16x8.ne |
0x2e |
:+1: |
:+1: |
i16x8.lt_s |
0x2f |
:+1: |
:+1: |
i16x8.lt_u |
0x30 |
:+1: |
:+1: |
i16x8.gt_s |
0x31 |
:+1: |
:+1: |
i16x8.gt_u |
0x32 |
:+1: |
:+1: |
i16x8.le_s |
0x33 |
:+1: |
:+1: |
i16x8.le_u |
0x34 |
:+1: |
:+1: |
i16x8.ge_s |
0x35 |
:+1: |
:+1: |
i16x8.ge_u |
0x36 |
:+1: |
:+1: |
i32x4.eq |
0x37 |
:+1: |
:+1: |
i32x4.ne |
0x38 |
:+1: |
:+1: |
i32x4.lt_s |
0x39 |
:+1: |
:+1: |
i32x4.lt_u |
0x3a |
:+1: |
:+1: |
i32x4.gt_s |
0x3b |
:+1: |
:+1: |
i32x4.gt_u |
0x3c |
:+1: |
:+1: |
i32x4.le_s |
0x3d |
:+1: |
:+1: |
i32x4.le_u |
0x3e |
:+1: |
:+1: |
i32x4.ge_s |
0x3f |
:+1: |
:+1: |
i32x4.ge_u |
0x40 |
:+1: |
:+1: |
Float Cmp |
Opcode |
Old Backend Status |
VCode Status |
f32x4.eq |
0x41 |
:+1: |
:+1: |
f32x4.ne |
0x42 |
:+1: |
:+1: |
f32x4.lt |
0x43 |
:+1: |
:+1: |
f32x4.gt |
0x44 |
:+1: |
:+1: |
f32x4.le |
0x45 |
:+1: |
:+1: |
f32x4.ge |
0x46 |
:+1: |
:+1: |
f64x2.eq |
0x47 |
:+1: |
:+1: |
f64x2.ne |
0x48 |
:+1: |
:+1: |
f64x2.lt |
0x49 |
:+1: |
:+1: |
f64x2.gt |
0x4a |
:+1: |
:+1: |
f64x2.le |
0x4b |
:+1: |
:+1: |
f64x2.ge |
0x4c |
:+1: |
:+1: |
v128 Op |
Opcode |
Old Backend Status |
VCode Status |
v128.not |
0x4d |
:+1: |
:+1: |
v128.and |
0x4e |
:+1: |
:+1: |
v128.andnot |
0x4f |
:+1: |
:+1: |
v128.or |
0x50 |
:+1: |
:+1: |
v128.xor |
0x51 |
:+1: |
:+1: |
v128.bitselect |
0x52 |
:+1: |
:+1: |
i8x16 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i8x16.abs |
0x60 |
:+1: |
:+1: |
i8x16.neg |
0x61 |
:+1: |
:+1: |
i8x16.any_true |
0x62 |
:+1: |
:+1: |
i8x16.all_true |
0x63 |
:+1: |
:+1: |
i8x16.bitmask |
0x64 |
:question: |
:+1: |
i8x16.narrow_i16x8_s |
0x65 |
:+1: |
:+1: |
i8x16.narrow_i16x8_u |
0x66 |
:+1: |
:+1: |
---- widen ---- |
0x67 |
-- |
|
---- widen ---- |
0x68 |
-- |
|
---- widen ---- |
0x69 |
-- |
|
---- widen ---- |
0x6a |
-- |
|
i8x16.shl |
0x6b |
:+1: |
:+1: |
i8x16.shr_s |
0x6c |
:+1: |
:+1: |
i8x16.shr_u |
0x6d |
:+1: |
:+1: |
i8x16.add |
0x6e |
:+1: |
:+1: |
i8x16.add_sat_s |
0x6f |
:+1: |
:+1: |
i8x16.add_sat_u |
0x70 |
:+1: |
:+1: |
i8x16.sub |
0x71 |
:+1: |
:+1: |
i8x16.sub_sat_s |
0x72 |
:+1: |
:+1: |
i8x16.sub_sat_u |
0x73 |
:+1: |
:+1: |
------------ |
0x74 |
-- |
-- |
---- mul ---- |
0x75 |
:question: |
|
i8x16.min_s |
0x76 |
:+1: |
:+1: |
i8x16.min_u |
0x77 |
:+1: |
:+1: |
i8x16.max_s |
0x78 |
:+1: |
:+1: |
i8x16.max_u |
0x79 |
:+1: |
:+1: |
------------ |
0x7a |
-- |
|
i8x16.avgr_u |
0x7b |
:+1: |
:+1: |
i16x8 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i16x8.abs |
0x80 |
:+1: |
:+1: |
i16x8.neg |
0x81 |
:+1: |
:+1: |
i16x8.any_true |
0x82 |
:+1: |
:+1: |
i16x8.all_true |
0x83 |
:+1: |
:+1: |
i16x8.bitmask |
0x84 |
:question: |
:+1: |
i16x8.narrow_i32x4_s |
0x85 |
:+1: |
:+1: |
i16x8.narrow_i32x4_u |
0x86 |
:+1: |
:+1: |
i16x8.widen_low_i8x16_s |
0x87 |
:+1: |
:+1: |
i16x8.widen_high_i8x16_s |
0x88 |
:+1: |
:+1: |
i16x8.widen_low_i8x16_u |
0x89 |
:+1: |
:+1: |
i16x8.widen_high_i8x16_u |
0x8a |
:+1: |
:+1: |
i16x8.shl |
0x8b |
:+1: |
:+1: |
i16x8.shr_s |
0x8c |
:+1: |
:+1: |
i16x8.shr_u |
0x8d |
:+1: |
:+1: |
i16x8.add |
0x8e |
:+1: |
:+1: |
i16x8.add_sat_s |
0x8f |
:+1: |
:+1: |
i16x8.add_sat_u |
0x90 |
:+1: |
:+1: |
i16x8.sub |
0x91 |
:+1: |
:+1: |
i16x8.sub_sat_s |
0x92 |
:+1: |
:+1: |
i16x8.sub_sat_u |
0x93 |
:+1: |
:+1: |
------------ |
0x94 |
-- |
-- |
i16x8.mul |
0x95 |
:+1: |
:+1: |
i16x8.min_s |
0x96 |
:+1: |
:+1: |
i16x8.min_u |
0x97 |
:+1: |
:+1: |
i16x8.max_s |
0x98 |
:+1: |
:+1: |
i16x8.max_u |
0x99 |
:+1: |
:+1: |
----------- |
0x9a |
-- |
|
i16x8.avgr_u |
0x9b |
:+1: |
:+1: |
i32x4 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i32x4.abs |
0xa0 |
:+1: |
:+1: |
i32x4.neg |
0xa1 |
:+1: |
:+1: |
i32x4.any_true |
0xa2 |
:+1: |
:+1: |
i32x4.all_true |
0xa3 |
:+1: |
:+1: |
i32x4.bitmask |
0xa4 |
:question: |
:+1: |
---- narrow ---- |
0xa5 |
-- |
|
---- narrow ---- |
0xa6 |
-- |
|
i32x4.widen_low_i16x8_s |
0xa7 |
:+1: |
:+1: |
i32x4.widen_high_i16x8_s |
0xa8 |
:+1: |
:+1: |
i32x4.widen_low_i16x8_u |
0xa9 |
:+1: |
:+1: |
i32x4.widen_high_i16x8_u |
0xaa |
:+1: |
:+1: |
i32x4.shl |
0xab |
:+1: |
:+1: |
i32x4.shr_s |
0xac |
:+1: |
:+1: |
i32x4.shr_u |
0xad |
:+1: |
:+1: |
i32x4.add |
0xae |
:+1: |
:+1: |
---- add_sat ---- |
0xaf |
-- |
|
---- add_sat ---- |
0xb0 |
-- |
|
i32x4.sub |
0xb1 |
:+1: |
:+1: |
---- sub_sat ---- |
0xb2 |
-- |
|
---- sub_sat ---- |
0xb3 |
-- |
|
---- dot ---- |
0xb4 |
-- |
|
i32x4.mul |
0xb5 |
:+1: |
:+1: |
i32x4.min_s |
0xb6 |
:+1: |
:+1: |
i32x4.min_u |
0xb7 |
:+1: |
:+1: |
i32x4.max_s |
0xb8 |
:+1: |
:+1: |
i32x4.max_u |
0xb9 |
:+1: |
:+1: |
i32x4.dot_i16x8_s |
0xba |
-- |
@abrown |
---- avgr_u ---- |
0xbb |
-- |
|
i64x2 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
---- |
0xc0 |
-- |
|
i64x2.neg |
0xc1 |
:+1: |
:+1: |
---- |
0xc2 |
-- |
|
---- |
0xc3 |
-- |
|
i64x2.bitmask |
0xc4 |
-- |
? |
---- |
0xc5 |
-- |
|
---- |
0xc6 |
-- |
|
i64x2.widen_low_i32x4_s |
0xc7 |
-- |
? |
i64x2.widen_high_i32x4_s |
0xc8 |
-- |
? |
i64x2.widen_low_i32x4_u |
0xc9 |
-- |
? |
i64x2.widen_high_i32x4_u |
0xca |
-- |
? |
i64x2.shl |
0xcb |
:+1: |
:+1: |
i64x2.shr_s |
0xcc |
:+1: |
:+1: |
i64x2.shr_u |
0xcd |
:+1: |
:+1: |
i64x2.add |
0xce |
:+1: |
:+1: |
---- |
0xcf |
-- |
|
---- |
0xd0 |
-- |
|
i64x2.sub |
0xd1 |
:+1: |
:+1: |
---- |
0xd2 |
-- |
|
---- |
0xd3 |
-- |
|
---- |
0xd4 |
-- |
|
i64x2.mul |
0xd5 |
:+1: |
:+1: |
---- |
0xd6 |
-- |
|
---- |
0xd7 |
-- |
|
f32x4 Op |
Opcode |
Old Backend Status |
VCode Status |
f32x4.ceil |
0xd8 |
:question: |
:+1: |
f32x4.floor |
0xd9 |
:question: |
:+1: |
f32x4.trunc |
0xda |
:question: |
:+1: |
f32x4.nearest |
0xdb |
:question: |
:+1: |
f32x4.abs |
0xe0 |
:+1: |
:+1: |
f32x4.neg |
0xe1 |
:+1: |
:+1: |
---- round ---- |
0xe2 |
-- |
|
f32x4.sqrt |
0xe3 |
:+1: |
:+1: |
f32x4.add |
0xe4 |
:+1: |
:+1: |
f32x4.sub |
0xe5 |
:+1: |
:+1: |
f32x4.mul |
0xe6 |
:+1: |
:+1: |
f32x4.div |
0xe7 |
:+1: |
:+1: |
f32x4.min |
0xe8 |
:+1: |
:+1: |
f32x4.max |
0xe9 |
:+1: |
:+1: |
f32x4.pmin |
0xea |
:question: |
:+1: |
f32x4.pmax |
0xeb |
:question: |
:+1: |
f64x2 Op |
Opcode |
Old Backend Status |
VCode Status |
f64x2.ceil |
0xdc |
:question: |
:+1: |
f64x2.floor |
0xdd |
:question: |
:+1: |
f64x2.trunc |
0xde |
:question: |
:+1: |
f64x2.nearest |
0xdf |
:question: |
:+1: |
f64x2.abs |
0xec |
:+1: |
:+1: |
f64x2.neg |
0xed |
:+1: |
:+1: |
---- round ---- |
0xee |
-- |
|
f64x2.sqrt |
0xef |
:+1: |
:+1: |
f64x2.add |
0xf0 |
:+1: |
:+1: |
f64x2.sub |
0xf1 |
:+1: |
:+1: |
f64x2.mul |
0xf2 |
:+1: |
:+1: |
f64x2.div |
0xf3 |
:+1: |
:+1: |
f64x2.min |
0xf4 |
:+1: |
:+1: |
f64x2.max |
0xf5 |
:+1: |
:+1: |
f64x2.pmin |
0xf6 |
:question: |
:+1: |
f64x2.pmax |
0xf7 |
:question: |
:+1: |
Conversion Op |
Opcode |
Old Backend Status |
VCode Status |
i32x4.trunc_sat_f32x4_s |
0xf8 |
:question: |
:+1: |
i32x4.trunc_sat_f32x4_u |
0xf9 |
:question: |
:+1: |
f32x4.convert_i32x4_s |
0xfa |
:+1: |
:+1: |
f32x4.convert_i32x4_u |
0xfb |
:question: |
:+1: |
jlb6740 edited Issue #2272:
Last Update: 1/14/2021
Loads |
Opcode |
Old Backend Status |
VCode Status |
v128.load |
0x00 |
:+1: |
:+1: |
v128.load32_zero |
0xfc |
-- |
:+1: |
v128.load64_zero |
0xfd |
-- |
:+1: |
v128.load8x8_s |
0x01 |
:+1: |
:+1: |
v128.load8x8_u |
0x02 |
:+1: |
:+1: |
v128.load16x4_s |
0x03 |
:+1: |
:+1: |
v128.load16x4_u |
0x04 |
:+1: |
:+1: |
v128.load32x2_s |
0x05 |
:+1: |
:+1: |
v128.load32x2_u |
0x06 |
:+1: |
:+1: |
v128.load8_splat |
0x07 |
:+1: |
:+1: |
v128.load16_splat |
0x08 |
:+1: |
:+1: |
v128.load32_splat |
0x09 |
:+1: |
:+1: |
v128.load64_splat |
0x0a |
:+1: |
:+1: |
Stores |
Opcode |
Old Backend Status |
VCode Status |
v128.store |
0x0b |
:+1: |
:+1: |
Basic operation |
Opcode |
Old Backend Status |
VCode Status |
v128.const |
0x0c |
:+1: |
:+1: |
i8x16.shuffle |
0x0d |
:+1: |
:+1: |
i8x16.swizzle |
0x0e |
:+1: |
:+1: |
Splat operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.splat |
0x0f |
:+1: |
:+1: |
i16x8.splat |
0x10 |
:+1: |
:+1: |
i32x4.splat |
0x11 |
:+1: |
:+1: |
i64x2.splat |
0x12 |
:+1: |
:+1: |
f32x4.splat |
0x13 |
:+1: |
:+1: |
f64x2.splat |
0x14 |
:+1: |
:+1: |
Lane operation |
Opcode |
Old Backend Status |
VCode Status |
i8x16.extract_lane_s |
0x15 |
:+1: |
:+1: |
i8x16.extract_lane_u |
0x16 |
:+1: |
:+1: |
i8x16.replace_lane |
0x17 |
:+1: |
:+1: |
i16x8.extract_lane_s |
0x18 |
:+1: |
:+1: |
i16x8.extract_lane_u |
0x19 |
:+1: |
:+1: |
i16x8.replace_lane |
0x1a |
:+1: |
:+1: |
i32x4.extract_lane |
0x1b |
:+1: |
:+1: |
i32x4.replace_lane |
0x1c |
:+1: |
:+1: |
i64x2.extract_lane |
0x1d |
:+1: |
:+1: |
i64x2.replace_lane |
0x1e |
:+1: |
:+1: |
f32x4.extract_lane |
0x1f |
:+1: |
:+1: |
f32x4.replace_lane |
0x20 |
:+1: |
:+1: |
f64x2.extract_lane |
0x21 |
:+1: |
:+1: |
f64x2.replace_lane |
0x22 |
:+1: |
:+1: |
Integer Cmp |
Opcode |
Old Backend Status |
VCode Status |
i8x16.eq |
0x23 |
:+1: |
:+1: |
i8x16.ne |
0x24 |
:+1: |
:+1: |
i8x16.lt_s |
0x25 |
:+1: |
:+1: |
i8x16.lt_u |
0x26 |
:+1: |
:+1: |
i8x16.gt_s |
0x27 |
:+1: |
:+1: |
i8x16.gt_u |
0x28 |
:+1: |
:+1: |
i8x16.le_s |
0x29 |
:+1: |
:+1: |
i8x16.le_u |
0x2a |
:+1: |
:+1: |
i8x16.ge_s |
0x2b |
:+1: |
:+1: |
i8x16.ge_u |
0x2c |
:+1: |
:+1: |
i16x8.eq |
0x2d |
:+1: |
:+1: |
i16x8.ne |
0x2e |
:+1: |
:+1: |
i16x8.lt_s |
0x2f |
:+1: |
:+1: |
i16x8.lt_u |
0x30 |
:+1: |
:+1: |
i16x8.gt_s |
0x31 |
:+1: |
:+1: |
i16x8.gt_u |
0x32 |
:+1: |
:+1: |
i16x8.le_s |
0x33 |
:+1: |
:+1: |
i16x8.le_u |
0x34 |
:+1: |
:+1: |
i16x8.ge_s |
0x35 |
:+1: |
:+1: |
i16x8.ge_u |
0x36 |
:+1: |
:+1: |
i32x4.eq |
0x37 |
:+1: |
:+1: |
i32x4.ne |
0x38 |
:+1: |
:+1: |
i32x4.lt_s |
0x39 |
:+1: |
:+1: |
i32x4.lt_u |
0x3a |
:+1: |
:+1: |
i32x4.gt_s |
0x3b |
:+1: |
:+1: |
i32x4.gt_u |
0x3c |
:+1: |
:+1: |
i32x4.le_s |
0x3d |
:+1: |
:+1: |
i32x4.le_u |
0x3e |
:+1: |
:+1: |
i32x4.ge_s |
0x3f |
:+1: |
:+1: |
i32x4.ge_u |
0x40 |
:+1: |
:+1: |
Float Cmp |
Opcode |
Old Backend Status |
VCode Status |
f32x4.eq |
0x41 |
:+1: |
:+1: |
f32x4.ne |
0x42 |
:+1: |
:+1: |
f32x4.lt |
0x43 |
:+1: |
:+1: |
f32x4.gt |
0x44 |
:+1: |
:+1: |
f32x4.le |
0x45 |
:+1: |
:+1: |
f32x4.ge |
0x46 |
:+1: |
:+1: |
f64x2.eq |
0x47 |
:+1: |
:+1: |
f64x2.ne |
0x48 |
:+1: |
:+1: |
f64x2.lt |
0x49 |
:+1: |
:+1: |
f64x2.gt |
0x4a |
:+1: |
:+1: |
f64x2.le |
0x4b |
:+1: |
:+1: |
f64x2.ge |
0x4c |
:+1: |
:+1: |
v128 Op |
Opcode |
Old Backend Status |
VCode Status |
v128.not |
0x4d |
:+1: |
:+1: |
v128.and |
0x4e |
:+1: |
:+1: |
v128.andnot |
0x4f |
:+1: |
:+1: |
v128.or |
0x50 |
:+1: |
:+1: |
v128.xor |
0x51 |
:+1: |
:+1: |
v128.bitselect |
0x52 |
:+1: |
:+1: |
i8x16 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i8x16.abs |
0x60 |
:+1: |
:+1: |
i8x16.neg |
0x61 |
:+1: |
:+1: |
i8x16.any_true |
0x62 |
:+1: |
:+1: |
i8x16.all_true |
0x63 |
:+1: |
:+1: |
i8x16.bitmask |
0x64 |
:question: |
:+1: |
i8x16.narrow_i16x8_s |
0x65 |
:+1: |
:+1: |
i8x16.narrow_i16x8_u |
0x66 |
:+1: |
:+1: |
---- widen ---- |
0x67 |
-- |
|
---- widen ---- |
0x68 |
-- |
|
---- widen ---- |
0x69 |
-- |
|
---- widen ---- |
0x6a |
-- |
|
i8x16.shl |
0x6b |
:+1: |
:+1: |
i8x16.shr_s |
0x6c |
:+1: |
:+1: |
i8x16.shr_u |
0x6d |
:+1: |
:+1: |
i8x16.add |
0x6e |
:+1: |
:+1: |
i8x16.add_sat_s |
0x6f |
:+1: |
:+1: |
i8x16.add_sat_u |
0x70 |
:+1: |
:+1: |
i8x16.sub |
0x71 |
:+1: |
:+1: |
i8x16.sub_sat_s |
0x72 |
:+1: |
:+1: |
i8x16.sub_sat_u |
0x73 |
:+1: |
:+1: |
------------ |
0x74 |
-- |
-- |
---- mul ---- |
0x75 |
:question: |
|
i8x16.min_s |
0x76 |
:+1: |
:+1: |
i8x16.min_u |
0x77 |
:+1: |
:+1: |
i8x16.max_s |
0x78 |
:+1: |
:+1: |
i8x16.max_u |
0x79 |
:+1: |
:+1: |
------------ |
0x7a |
-- |
|
i8x16.avgr_u |
0x7b |
:+1: |
:+1: |
i16x8 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i16x8.abs |
0x80 |
:+1: |
:+1: |
i16x8.neg |
0x81 |
:+1: |
:+1: |
i16x8.any_true |
0x82 |
:+1: |
:+1: |
i16x8.all_true |
0x83 |
:+1: |
:+1: |
i16x8.bitmask |
0x84 |
:question: |
:+1: |
i16x8.narrow_i32x4_s |
0x85 |
:+1: |
:+1: |
i16x8.narrow_i32x4_u |
0x86 |
:+1: |
:+1: |
i16x8.widen_low_i8x16_s |
0x87 |
:+1: |
:+1: |
i16x8.widen_high_i8x16_s |
0x88 |
:+1: |
:+1: |
i16x8.widen_low_i8x16_u |
0x89 |
:+1: |
:+1: |
i16x8.widen_high_i8x16_u |
0x8a |
:+1: |
:+1: |
i16x8.shl |
0x8b |
:+1: |
:+1: |
i16x8.shr_s |
0x8c |
:+1: |
:+1: |
i16x8.shr_u |
0x8d |
:+1: |
:+1: |
i16x8.add |
0x8e |
:+1: |
:+1: |
i16x8.add_sat_s |
0x8f |
:+1: |
:+1: |
i16x8.add_sat_u |
0x90 |
:+1: |
:+1: |
i16x8.sub |
0x91 |
:+1: |
:+1: |
i16x8.sub_sat_s |
0x92 |
:+1: |
:+1: |
i16x8.sub_sat_u |
0x93 |
:+1: |
:+1: |
------------ |
0x94 |
-- |
-- |
i16x8.mul |
0x95 |
:+1: |
:+1: |
i16x8.min_s |
0x96 |
:+1: |
:+1: |
i16x8.min_u |
0x97 |
:+1: |
:+1: |
i16x8.max_s |
0x98 |
:+1: |
:+1: |
i16x8.max_u |
0x99 |
:+1: |
:+1: |
----------- |
0x9a |
-- |
|
i16x8.avgr_u |
0x9b |
:+1: |
:+1: |
i32x4 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
i32x4.abs |
0xa0 |
:+1: |
:+1: |
i32x4.neg |
0xa1 |
:+1: |
:+1: |
i32x4.any_true |
0xa2 |
:+1: |
:+1: |
i32x4.all_true |
0xa3 |
:+1: |
:+1: |
i32x4.bitmask |
0xa4 |
:question: |
:+1: |
---- narrow ---- |
0xa5 |
-- |
|
---- narrow ---- |
0xa6 |
-- |
|
i32x4.widen_low_i16x8_s |
0xa7 |
:+1: |
:+1: |
i32x4.widen_high_i16x8_s |
0xa8 |
:+1: |
:+1: |
i32x4.widen_low_i16x8_u |
0xa9 |
:+1: |
:+1: |
i32x4.widen_high_i16x8_u |
0xaa |
:+1: |
:+1: |
i32x4.shl |
0xab |
:+1: |
:+1: |
i32x4.shr_s |
0xac |
:+1: |
:+1: |
i32x4.shr_u |
0xad |
:+1: |
:+1: |
i32x4.add |
0xae |
:+1: |
:+1: |
---- add_sat ---- |
0xaf |
-- |
|
---- add_sat ---- |
0xb0 |
-- |
|
i32x4.sub |
0xb1 |
:+1: |
:+1: |
---- sub_sat ---- |
0xb2 |
-- |
|
---- sub_sat ---- |
0xb3 |
-- |
|
---- dot ---- |
0xb4 |
-- |
|
i32x4.mul |
0xb5 |
:+1: |
:+1: |
i32x4.min_s |
0xb6 |
:+1: |
:+1: |
i32x4.min_u |
0xb7 |
:+1: |
:+1: |
i32x4.max_s |
0xb8 |
:+1: |
:+1: |
i32x4.max_u |
0xb9 |
:+1: |
:+1: |
i32x4.dot_i16x8_s |
0xba |
-- |
@abrown |
---- avgr_u ---- |
0xbb |
-- |
|
i64x2 Arith Op |
Opcode |
Old Backend Status |
VCode Status |
---- |
0xc0 |
-- |
|
i64x2.neg |
0xc1 |
:+1: |
:+1: |
---- |
0xc2 |
-- |
|
---- |
0xc3 |
-- |
|
i64x2.bitmask |
0xc4 |
-- |
? |
---- |
0xc5 |
-- |
|
---- |
0xc6 |
-- |
|
i64x2.widen_low_i32x4_s |
0xc7 |
-- |
? |
i64x2.widen_high_i32x4_s |
0xc8 |
-- |
? |
i64x2.widen_low_i32x4_u |
0xc9 |
-- |
? |
i64x2.widen_high_i32x4_u |
0xca |
-- |
? |
i64x2.shl |
0xcb |
:+1: |
:+1: |
i64x2.shr_s |
0xcc |
:+1: |
:+1: |
i64x2.shr_u |
0xcd |
:+1: |
:+1: |
i64x2.add |
0xce |
:+1: |
:+1: |
---- |
0xcf |
-- |
|
---- |
0xd0 |
-- |
|
i64x2.sub |
0xd1 |
:+1: |
:+1: |
---- |
0xd2 |
-- |
|
---- |
0xd3 |
-- |
|
---- |
0xd4 |
-- |
|
i64x2.mul |
0xd5 |
:+1: |
:+1: |
---- |
0xd6 |
-- |
|
---- |
0xd7 |
-- |
|
f32x4 Op |
Opcode |
Old Backend Status |
VCode Status |
f32x4.ceil |
0xd8 |
:question: |
:+1: |
f32x4.floor |
0xd9 |
:question: |
:+1: |
f32x4.trunc |
0xda |
:question: |
:+1: |
f32x4.nearest |
0xdb |
:question: |
:+1: |
f32x4.abs |
0xe0 |
:+1: |
:+1: |
f32x4.neg |
0xe1 |
:+1: |
:+1: |
---- round ---- |
0xe2 |
-- |
|
f32x4.sqrt |
0xe3 |
:+1: |
:+1: |
f32x4.add |
0xe4 |
:+1: |
:+1: |
f32x4.sub |
0xe5 |
:+1: |
:+1: |
f32x4.mul |
0xe6 |
:+1: |
:+1: |
f32x4.div |
0xe7 |
:+1: |
:+1: |
f32x4.min |
0xe8 |
:+1: |
:+1: |
f32x4.max |
0xe9 |
:+1: |
:+1: |
f32x4.pmin |
0xea |
:question: |
:+1: |
f32x4.pmax |
0xeb |
:question: |
:+1: |
f64x2 Op |
Opcode |
Old Backend Status |
VCode Status |
f64x2.ceil |
0xdc |
:question: |
:+1: |
f64x2.floor |
0xdd |
:question: |
:+1: |
f64x2.trunc |
0xde |
:question: |
:+1: |
f64x2.nearest |
0xdf |
:question: |
:+1: |
f64x2.abs |
0xec |
:+1: |
:+1: |
f64x2.neg |
0xed |
:+1: |
:+1: |
---- round ---- |
0xee |
-- |
|
f64x2.sqrt |
0xef |
:+1: |
:+1: |
f64x2.add |
0xf0 |
:+1: |
:+1: |
f64x2.sub |
0xf1 |
:+1: |
:+1: |
f64x2.mul |
0xf2 |
:+1: |
:+1: |
f64x2.div |
0xf3 |
:+1: |
:+1: |
f64x2.min |
0xf4 |
:+1: |
:+1: |
f64x2.max |
0xf5 |
:+1: |
:+1: |
f64x2.pmin |
0xf6 |
:question: |
:+1: |
f64x2.pmax |
0xf7 |
:question: |
:+1: |
Conversion Op |
Opcode |
Old Backend Status |
VCode Status |
i32x4.trunc_sat_f32x4_s |
0xf8 |
:question: |
:+1: |
i32x4.trunc_sat_f32x4_u |
0xf9 |
:question: |
:+1: |
f32x4.convert_i32x4_s |
0xfa |
:+1: |
:+1: |
f32x4.convert_i32x4_u |
0xfb |
:question: |
:+1: |
Last updated: Nov 22 2024 at 16:03 UTC