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bnjbvr commented on Issue #2136:
(Sorry for the slowness, lgtm too. As a general question, what was the reasoning behind having one SseOpcode enum per lane size vs one single SseOpcode for all, and the lane size in the Vcode inst?)
jlb6740 commented on Issue #2136:
(Sorry for the slowness, lgtm too. As a general question, what was the reasoning behind having one SseOpcode enum per lane size vs one single SseOpcode for all, and the lane size in the Vcode inst?)
Hi @bnjbvr .. no slowness, thanks for the review! This question on per lane vs no lane in the enum is a good one. I think we discussed it in a recent cranelift meeting and is something that can be changed in the future if we think that is best. I think we said the benefits for having one SseOpcode per lane (how it is now) were just (1) the explicitness that made the code easier to read, less to infer, less to chase down what a lowering was ultimately doing, and (2) the explicitness prevents the creation of lowering nonsensical instructions. So that was general thought, but you were out and obviously enumerating each instruction is maybe not desired and maybe removes some sort of flexibility and so ultimately this is something that is still an open and can be refactored if that's the better direction.
jlb6740 edited a comment on Issue #2136:
(Sorry for the slowness, lgtm too. As a general question, what was the reasoning behind having one SseOpcode enum per lane size vs one single SseOpcode for all, and the lane size in the Vcode inst?)
Hi @bnjbvr .. no slowness, thanks for the review! This question of one instruction per lane vs no lane in the enum is a good one. I think we discussed it in a recent cranelift meeting and is something that can be changed in the future if we think that is best. I think we said the benefits for having one SseOpcode per lane (how it is now) were just (1) the explicitness that made the code easier to read, less to infer, less to chase down what a lowering was ultimately doing, and (2) the explicitness prevents the creation of lowering nonsensical instructions. So that was general thought, but you were out and obviously enumerating each instruction is maybe not desired and maybe removes some sort of flexibility and so ultimately this is something that is still an open and can be refactored if that's the better direction.
jlb6740 edited a comment on Issue #2136:
(Sorry for the slowness, lgtm too. As a general question, what was the reasoning behind having one SseOpcode enum per lane size vs one single SseOpcode for all, and the lane size in the Vcode inst?)
Hi @bnjbvr .. no slowness, thanks for the review! This question of one instruction per lane vs no lane in the enum is a good one. I think we discussed it in a recent cranelift meeting and is something that can be changed in the future if we think that is best. I think we said the benefits for having one SseOpcode per lane (how it is now) were just (1) the explicitness that made the code easier to read, less to infer, less to chase down what a lowering was ultimately doing, and (2) the explicitness prevents the creation of lowering nonsensical instructions. So that was general thought, but you were out and obviously enumerating each instruction is maybe not desired/unwieldy and maybe removes some sort of flexibility and so ultimately this is something that is still an open and can be refactored if that's the better direction.
Last updated: Dec 23 2024 at 12:05 UTC