Stream: git-wasmtime

Topic: wasmtime / Issue #1424 Fix the order of the rex2 register...

view this post on Zulip Wasmtime GitHub notifications bot (Mar 27 2020 at 20:28):

bjorn3 commented on Issue #1424:

https://github.com/bytecodealliance/wasmtime/issues/1423#issuecomment-605295620

Could you add an x86_pextr binemit test

Is the last commit ok, or do you want to test more cases?

view this post on Zulip Wasmtime GitHub notifications bot (Mar 27 2020 at 20:47):

github-actions[bot] commented on Issue #1424:

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view this post on Zulip Wasmtime GitHub notifications bot (Mar 28 2020 at 13:45):

bjorn3 commented on Issue #1424:

With this I can finally store SIMD vectors in SSA values, rather than memory. This improves performance for tokei from ~50% overhead compared to cg_llvm to ~30% overhead.

view this post on Zulip Wasmtime GitHub notifications bot (Mar 28 2020 at 21:10):

abrown commented on Issue #1424:

I don't know if this will give you more flexibility, but note that in #1377 I have added support for declaring constants in the function preamble instead of only through vconst. This also should make it easier to use constants of sizes other than 128-bit. Take a look at
64c8cbf and let me know if you can think of any changes to that that would help cg_clif.

view this post on Zulip Wasmtime GitHub notifications bot (Mar 28 2020 at 21:10):

abrown edited a comment on Issue #1424:

I don't know if this will give you more flexibility, but note that in #1377 I have added support for declaring constants in the function preamble instead of only through vconst. This also should make it easier to use constants of sizes other than 128-bit. Take a look at 64c8cbf and let me know if you can think of any changes to that that would help cg_clif.

view this post on Zulip Wasmtime GitHub notifications bot (Mar 28 2020 at 21:37):

bjorn3 commented on Issue #1424:

I don't think any of that PR will help me. At least for now. Creating SIMD values is currently very slow anyway as at MIR level all lanes get assigned separately, meaning that I have to use vconst 0 + insertlane. I will obviously need to optimize this :)

Last updated: Oct 23 2024 at 20:03 UTC