Wasmtime GitHub notifications bot (Feb 03 2021 at 17:01): Wasmtime GitHub notifications bot (Feb 03 2021 at 17:01):bjorn3 commented on Issue #1048:
The concept of tied constraints doesn't exist for the new backend framework.
Wasmtime GitHub notifications bot (Feb 03 2021 at 17:28):cfallin commented on Issue #1048:
Yes, closing now; addressed with regalloc.rs.
Wasmtime GitHub notifications bot (Feb 03 2021 at 17:28):cfallin closed Issue #1048:
Tied constraints are when an input to an instruction has to be in the same register as an output, as is the case for most arithmetic instructions on x86.
Currently, Cranelift's register allocator handles this constraint in the coloring pass. However, the coloring pass is very late, when a lot decisions have already been made, and a lot of other constraints have been saved up to be solved at once.
One idea for doing this would be to extend the concept of CSSA form produced by the coalescing pass. CSSA is essentially about putting "phi-related" values into sets which can be allocated the same virtual register, because whenever the input to a phi and the output to a phi can occupy the same register, we avoid a copy. Tied constraints are very similar: we want the input to an instruction and the output to be in the same register, so coalescing them would also avoid requiring a copy.
In cases where the input and output register conflict, we could insert an explicit copy.
And since coalescing happens before spilling or coloring, this should mean that coloring wouldn't have to worry about these constraints.
Last updated: Dec 23 2024 at 12:05 UTC