Stream: git-cranelift

Topic: cranelift / PR #1388 Infer REX prefix for SIMD `store` an...


view this post on Zulip GitHub (Feb 12 2020 at 23:08):

abrown requested iximeow for a review on PR #1388.

view this post on Zulip GitHub (Feb 12 2020 at 23:08):

abrown opened PR #1388 from infer-rex-for-simd to master:

<!-- Please ensure all communication adheres to the code of conduct. -->

view this post on Zulip GitHub (Feb 12 2020 at 23:09):

abrown edited PR #1388 from infer-rex-for-simd to master:

__enc_32_64__: fstDisp8, fstDisp32, fld, fldDisp8, fldDisp32, fspillSib32, fregspill32, ffillSib32, fregfill32, frmov, furm, fa, fax, f_ib
__enc_32_64_maybe_isap__: r_ib_unsigned_r, fa_ib, fa, r_ib_unsigned_gpr, fcmp, icscc_fpr
__enc_both__: frurm, pfcmp, fa, furm

<!-- Please ensure all communication adheres to the code of conduct. -->

view this post on Zulip GitHub (Feb 13 2020 at 02:47):

iximeow submitted PR Review.

view this post on Zulip GitHub (Feb 13 2020 at 02:47):

iximeow submitted PR Review.

view this post on Zulip GitHub (Feb 13 2020 at 02:47):

iximeow created PR Review Comment:

:tada:

view this post on Zulip GitHub (Feb 13 2020 at 02:47):

iximeow created PR Review Comment:

I think this also needs a || test_input(1, inst, divert, func, is_extended_reg) in the case that the base register is r8-r15? I have admit I'm not sure which order registers are specified but the other part of the recipe this is used in has me suspect. I'm also not sure how well our tests cover getting less-likely encodings like that - I'd not think about it if I didn't just try to do [r11] a few days ago.

view this post on Zulip GitHub (Feb 13 2020 at 18:34):

abrown updated PR #1388 from infer-rex-for-simd to master:

__enc_32_64__: fstDisp8, fstDisp32, fld, fldDisp8, fldDisp32, fspillSib32, fregspill32, ffillSib32, fregfill32, frmov, furm, fa, fax, f_ib
__enc_32_64_maybe_isap__: r_ib_unsigned_r, fa_ib, fa, r_ib_unsigned_gpr, fcmp, icscc_fpr
__enc_both__: frurm, pfcmp, fa, furm

<!-- Please ensure all communication adheres to the code of conduct. -->

view this post on Zulip GitHub (Feb 13 2020 at 18:48):

abrown updated PR #1388 from infer-rex-for-simd to master:

__enc_32_64__: fstDisp8, fstDisp32, fld, fldDisp8, fldDisp32, fspillSib32, fregspill32, ffillSib32, fregfill32, frmov, furm, fa, fax, f_ib
__enc_32_64_maybe_isap__: r_ib_unsigned_r, fa_ib, fa, r_ib_unsigned_gpr, fcmp, icscc_fpr
__enc_both__: frurm, pfcmp, fa, furm

<!-- Please ensure all communication adheres to the code of conduct. -->

view this post on Zulip GitHub (Feb 13 2020 at 23:08):

iximeow submitted PR Review.

view this post on Zulip GitHub (Feb 19 2020 at 17:24):

abrown merged PR #1388.


Last updated: Dec 23 2024 at 13:07 UTC