GitHub (Feb 28 2020 at 23:25): GitHub (Feb 28 2020 at 23:25):alexcrichton transferred Issue #728:
Some architectures make use of branch delay slots, such as MIPS and SPARC; some even more exotic ones have load delay slots as well. Often enough there are also instructions with results only usable after certain number of cycles.
I'm trying to port Cranelift to MIPS64. I glanced over the codebase and found no support for filling the delay slots; I had to emit NOPs after every branch in the meantime. (Indeed I didn't expect any because all currently supported architectures have no delay slots.)
So what's the current plan regarding this? A roadmap or implementation guide would be great!
Last updated: Nov 22 2024 at 16:03 UTC