alexcrichton transferred Issue #27:
Suppose we want to compare 8-bit ints on a 32-bit RISC:
widen32.legalize( a << icmp('ult', x, y), Rtl( wx << uextend.i32(x), wy << uextend.i32(y), a << icmp('ult', wx, wy), ))We want to generalize this pattern, but this transformation is only valid for the unsigned or sign-neutral condition codes, so this is wrong:
widen32.legalize( a << icmp(cc, x, y), Rtl( wx << uextend.i32(x), wy << uextend.i32(y), a << icmp(cc, wx, wy), ))We need a way of specifying a predicate on the immediate
cc
. Ideally, this mechanism should share representation with the instruction predicates already supported by instruction encodings.(Also note that the first example doesn't work either—we can't even require a fixed immediate value in the input pattern.)
Last updated: Dec 23 2024 at 13:07 UTC