Stream: cranelift

Topic: regalloc2: mutually exclusive registers


view this post on Zulip T0b1 (Dec 07 2022 at 23:26):

Hey, I've been working a bit on support for 8 bit operands for ALU instructions on x64 for a project of mine and I was wondering whether regalloc supports mutually exclusive register allocation since for example add ah, dil is not encodable. So I would need a way to tell regalloc that if it allocates e.g. ah for one operand it cannot allocate dil, sil, bpl, r8b, ... for the other. Is that possible?
(I don't know if this is the right place to ask but there doesn't seem to be a channel for regalloc on this zulip)

view this post on Zulip Chris Fallin (Dec 07 2022 at 23:28):

Unfortunately no, such a constraint isn't possible to encode right now. It's conceptually possible (the first of those to be allocated would impose a condition when looking for a register for the second one) but I'd have to think through how it impacts backtracking...

view this post on Zulip Chris Fallin (Dec 07 2022 at 23:28):

the simple (if inefficient) solution for now would be to settle on just allocating one kind of 8-bit register (e.g. only the low 8 bits) so you never allocate ah

view this post on Zulip T0b1 (Dec 07 2022 at 23:30):

Okay, thanks.


Last updated: Jan 10 2026 at 20:04 UTC