Dominik Behr (Aug 30 2026 at 02:44): Dominik Behr (Aug 30 2026 at 02:44):hello everyone. I have been using cranelift extensively in my (mostly vibe coded) Rust SGI Indy emulator, https://github.com/techomancer/iris . It is used both for acceleating CPU emulation and to build specialized "shaders" for emulating the drawing engine in Newport graphics REX3 chip.
I have been accessing the members of mips core (registers and cpu state) struct via base pointer + offset, which works well, but I have realized (since im emulating just single cpu) all offsets and callbacks to rust are effectively constants at compile time. The use of constants for base addresses of memory and arrays and for callbacks to Rust seems to be a good optimization at this point, but for register access it will generate loads and stores using full 64 bit address which will be nightmare for code size/density. So it seems a better approach is a base register + offset. But thatalso means burning a register for the base address which may be easily reloaded from constant. Is there any way to express something like this in IR?
Also, 2nd, possibly idiotic question. My JIT has 2 modes, one with function per entry address in a code page, and one where whole page gets compiled with dispatch table at the beginning. The tradeoff is replicated statically reachable code from multiple entrypoint, vs one single function with dispatch table that needs to do a branch to begin execution. I think it would be insteresting if it was possible to compile a single function with multiple entry points?
Finally, I ended up creating a proxy object(s) for memory arena and doing deferred sealing of functions compiled from multiple compile threads sharing single arena, mostly so I dont waste space sealing functions that do not cover full pages. This may be silly, but I wonder if my approach is the "correct" way to do it. Or are there better ways?
Last updated: Aug 30 2026 at 09:07 UTC