Erddorn (Oct 07 2026 at 21:21): Erddorn (Oct 07 2026 at 21:21):I just noticed on the Bytecode Alliance homepage for Cranelift it says yall are running this in production to run untrusted code. Would it be possible, and what kind of slowdown are we talking about, if I wanted to, outside of critical loops, use Cranelift to switch between hardware architectures on the fly as a poor man's way to prevent copy-paste shellcode?
Chris Fallin (Oct 07 2026 at 21:40):What do you mean by "switch between hardware architectures"? It's not clear to me the context of your question. Do you want to emulate one ISA on another?
mac (Oct 08 2026 at 18:46):I'm guessing he means something like https://github.com/ssrg-vt/HeterSec but eddorn cranelift is a compiler, if you are considering binary inputs you need to look elsewhere ; remill/anvill on llvm would be your lift from eg x86 and you could then use cranelift as the drop onto a different isa
Erddorn (Oct 14 2026 at 08:33):Chris Fallin said:
What do you mean by "switch between hardware architectures"? It's not clear to me the context of your question. Do you want to emulate one ISA on another?
lift an x86-64 binary into RISC-V machine code, basic block by basic block
e.g. x86-64 → iced-x86 → Cranelift IR → RV64
watch it happen live: https://ski.public.computer/
Chris Fallin (Oct 14 2026 at 14:49):ah, ok, so dynamic binary translation (DBT) like Dynamo or qemu TCG
Except that in the end you're interpreting the riscv64 instructions? It's not clear to me why you wouldn't write a sandboxed x86-64 interpreter instead if you're not actually running on riscv64 hardware (put bounds on memory and control flow destinations directly), if your goal is SFI/CFI. Anyway, cool project, let us know if you have Cranelift-specific questions...
Last updated: Oct 31 2026 at 23:03 UTC