Vulcain (Jul 25 2024 at 08:06): Vulcain (Jul 25 2024 at 08:06):Hey !
I'm implementing aarch64 comparison instructions for winch. So I've made a simple example to see what cranelift outputs, and I don't understand the use of uxtb.
Where does it come from ? I see some uextend_maybe in cranelift/codegen/src/opts/icmp.isle, but it seems to be used for nested comparisons.
Why is it useful ? cset is not producing a byte
Capture-décran-2024-07-25-à-09.58.09.png
T0b1 (Jul 25 2024 at 09:42):From what I can see, there is simply no isle-pattern matching just icmp+uextend (there is one for select + uextend + icmp and brif + uextend + icmp) so it‘s lowered as two separate instructions
Vulcain (Jul 25 2024 at 10:09):It comes from this code:
https://github.com/bytecodealliance/wasmtime/blob/5d0d61602f2dfa5478ef120a86a9009d74ac56bb/cranelift/wasm/src/code_translator.rs#L3033
T0b1 (Jul 25 2024 at 15:50):Yes, because on the IR-Level, icmp produces an i8
(missing in the docs for icmp but I assume it has the same semantics as icmp_imm which has a documented return type: <https://docs.rs/cranelift-codegen/0.110.1/cranelift_codegen/ir/trait.InstBuilder.html#method.icmp_imm>
Vulcain (Jul 25 2024 at 15:51):Ok, thank you :grinning:
Chris Fallin (Jul 25 2024 at 16:22):Indeed, and icmp produces an i8 because on x86 the SETcc instructions only set an 8-bit register (and leave the rest of the register unchanged) -- fairly frustrating but this was our compromise. In a perfect world and/or if we rework the x86 backend's lowering scheme somewhat we could probably eventually transition to i32 (or polymorphic any-int) results from icmp
Last updated: Dec 23 2024 at 13:07 UTC