Support ARM Cortex-M ISA · cranelift

Hello there & happy holidays :palm_tree:
a while ago I was looking into adding Cortex-M support to cranelift, but I couldn't find any documentation for writing a new ISA layer. Reading existing source provided me with a rough idea, though not enough to get going. Is there anything I have missed? Also: is C-M even a feasible target? It's a 32bit embedded architecture and typical RAM size is around 64-128kb

bjorn3 (Dec 24 2025 at 19:54):

Cranelift: arm32 support · Issue #1173 · bytecodealliance/wasmtime

What is the feature or code improvement you would like to do in Cranelift? I would like to add ARM support by implementing ARM (not Thumb) encodings/recipes and abi. I am especially interested in a...

bjorn3 (Dec 24 2025 at 19:55):

I don't think there is any documentation. You could probably start by copying the existing arm64 backend and adapt it.

bjorn3 (Dec 24 2025 at 19:55):

Anatol Ulrich (Dec 25 2025 at 12:53):

ok, so I guess asking here when I'm stuck is my best bet? (I kinda sorta know my way around things but I'm by no means a compiler or assembly pro, most of my professional developer life has been high level)

the simple answer is thumb - what exactly that means for codegen is probably going to be fun though, judging from the support matrix x this SO explainer :grimacing:

ARM Cortex-M - Wikipedia

The ARM Cortex-M is a group of 32-bit RISC ARM processor cores licensed by ARM Limited. These cores are optimized for low-cost and energy-efficient integrated circuits, which have been embedded in tens of billions of consumer devices.[1] Though they are most often the main component of microcontroller chips, sometimes they are embedded inside other types of chips too. The Cortex-M family consists of Cortex-M0,[2] Cortex-M0+,[3] Cortex-M1,[4] Cortex-M3,[5] Cortex-M4,[6] Cortex-M7,[7] Cortex-M23,[8] Cortex-M33,[9] Cortex-M35P,[10] Cortex-M52,[11] Cortex-M55,[12] Cortex-M85.[13] A floating-point unit (FPU) option is available for Cortex-M4 / M7 / M33 / M35P / M52 / M55 / M85 cores, and when included in the silicon these cores are sometimes known as "Cortex-MxF", where 'x' is the core variant.

What is the difference between the ARM, Thumb and Thumb 2 instruction encodings?

I am a bit confused about instruction sets. There are Thumb, ARM and Thumb 2. From what I have read Thumb instructions are all 16-bit but inside the ARMv7M user manual (page vi) there are Thumb 16-...

Stream: cranelift

Topic: Support ARM Cortex-M ISA

Anatol Ulrich (Dec 24 2025 at 16:08):

bjorn3 (Dec 24 2025 at 19:54):

bjorn3 (Dec 24 2025 at 19:55):

bjorn3 (Dec 24 2025 at 19:55):

Anatol Ulrich (Dec 25 2025 at 12:53):